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staging: add ath6kl driver for AR6003 chip

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AR6003 is a single stream, SDIO based 802.11 chipset from
Atheros optimized for mobile and embedded devices. ath6kl is a
cfg80211 driver for AR6003 and supports both the station and
AP mode of operation.

Station mode supports 802.11 a/b/g/n with HT20 on 2.4/5GHz and
HT40 only on 5GHz. Some of the other features include WPA/WPA2,
WPS, WMM, WMM-PS, and BT coexistence. AP mode can be operated
only in b/g mode with support for a subset of features mentioned
above.

The driver supports cfg80211 but comes with its own set of
wext ioctls which have historically supported some of our
customers with features like BT 3.0 and AP mode of operation.

For further details, please refer to:

http://wireless.kernel.org/en/users/Drivers/ath6kl

The driver requires firmware that runs on the chip's network
processor. The majority of it is stored in ROM. The binaries
that are downloaded and executed from RAM are as follows:

1) Patch against the code in ROM for bug fixes and feature
   enhancements.
2) Code to copy the data from the OTP region of the memory
   into RAM.
3) Calibration file carrying board specific data.

The above files need to be present in the directory
'/lib/firmware/ath6k/AR6003/hw2.0/' for the driver to initialize
the chip upon enumeration. The files can be downloaded from the
link specified at the following location:

http://wireless.kernel.org/en/users/Drivers/ath6kl#Download

This driver is only provided in the interim while we work on
the mac80211 replacement, ath6k. Once the mac80211 driver
achieves feature parity with the ath6kl driver, the ath6kl will
be deprecated and removed from staging.

Signed-off-by: Vipin Mehta <vmehta@atheros.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This commit is contained in:
Vipin Mehta 2010-09-01 12:06:33 -07:00 committed by Greg Kroah-Hartman
parent 9b9913d80b
commit 30295c8936
162 changed files with 92419 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
drivers/staging/Kconfig
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@ -157,5 +157,7 @@ source "drivers/staging/westbridge/Kconfig"
source "drivers/staging/sbe-2t3e3/Kconfig"
source "drivers/staging/ath6kl/Kconfig"
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING

1
drivers/staging/Makefile
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@ -59,3 +59,4 @@ obj-$(CONFIG_TIDSPBRIDGE) += tidspbridge/
obj-$(CONFIG_ACPI_QUICKSTART) += quickstart/
obj-$(CONFIG_WESTBRIDGE_ASTORIA) += westbridge/astoria/
obj-$(CONFIG_SBE_2T3E3) += sbe-2t3e3/
obj-$(CONFIG_ATH6K_LEGACY) += ath6kl/

163
drivers/staging/ath6kl/Kconfig Normal file
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@ -0,0 +1,163 @@
config ATH6K_LEGACY
tristate "Atheros AR6003 support (non mac80211)"
depends on MMC && WLAN
select WIRELESS_EXT
select WEXT_PRIV
help
This module adds support for wireless adapters based on Atheros AR6003 chipset running over SDIO. If you choose to build it as a module, it will be called ath6kl. Pls note that AR6002 and AR6001 are not supported by this driver.
choice
prompt "AR6003 Board Data Configuration"
depends on ATH6K_LEGACY
default AR600x_SD31_XXX
help
Select the appropriate board data template from the list below that matches your AR6003 based reference design.
config AR600x_SD31_XXX
bool "SD31-xxx"
help
Board Data file for a standard SD31 reference design (File: bdata.SD31.bin)
config AR600x_WB31_XXX
bool "WB31-xxx"
help
Board Data file for a standard WB31 (BT/WiFi) reference design (File: bdata.WB31.bin)
config AR600x_SD32_XXX
bool "SD32-xxx"
help
Board Data file for a standard SD32 (5GHz) reference design (File: bdata.SD32.bin)
config AR600x_CUSTOM_XXX
bool "CUSTOM-xxx"
help
Board Data file for a custom reference design (File: should be named as bdata.CUSTOM.bin)
endchoice
config ATH6KL_ENABLE_COEXISTENCE
bool "BT Coexistence support"
depends on ATH6K_LEGACY
help
Enables WLAN/BT coexistence support. Select the apprpriate configuration from below.
choice
prompt "Front-End Antenna Configuration"
depends on ATH6KL_ENABLE_COEXISTENCE
default AR600x_DUAL_ANTENNA
help
Indicates the number of antennas being used by BT and WLAN. Select the appropriate configuration from the list below that matches your AR6003 based reference design.
config AR600x_DUAL_ANTENNA
bool "Dual Antenna"
help
Dual Antenna Design
config AR600x_SINGLE_ANTENNA
bool "Single Antenna"
help
Single Antenna Design
endchoice
choice
prompt "Collocated Bluetooth Type"
depends on ATH6KL_ENABLE_COEXISTENCE
default AR600x_BT_AR3001
help
Select the appropriate configuration from the list below that matches your AR6003 based reference design.
config AR600x_BT_QCOM
bool "Qualcomm BTS4020X"
help
Qualcomm BT (3 Wire PTA)
config AR600x_BT_CSR
bool "CSR BC06"
help
CSR BT (3 Wire PTA)
config AR600x_BT_AR3001
bool "Atheros AR3001"
help
Atheros BT (3 Wire PTA)
endchoice
config ATH6KL_HCI_BRIDGE
bool "HCI over SDIO support"
depends on ATH6K_LEGACY
help
Enables BT over SDIO. Applicable only for combo designs (eg: WB31)
config ATH6KL_CONFIG_GPIO_BT_RESET
bool "Configure BT Reset GPIO"
depends on ATH6KL_HCI_BRIDGE
help
Configure a WLAN GPIO for use with BT.
config AR600x_BT_RESET_PIN
int "GPIO"
depends on ATH6KL_CONFIG_GPIO_BT_RESET
default 22
help
WLAN GPIO to be used for resetting BT
config ATH6KL_CFG80211
bool "CFG80211 support"
depends on ATH6K_LEGACY
help
Enables support for CFG80211 APIs. The default option is to use WEXT. Even with this option enabled, WEXT is not explicitly disabled and the onus of not exercising WEXT lies on the application(s) running in the user space.
config ATH6KL_HTC_RAW_INTERFACE
bool "RAW HTC support"
depends on ATH6K_LEGACY
help
Enables raw HTC interface. Allows application to directly talk to the HTC interface via the ioctl interface
config ATH6KL_VIRTUAL_SCATTER_GATHER
bool "Virtual Scatter-Gather support"
depends on ATH6K_LEGACY
help
Enables virtual scatter gather support for the hardware that does not support it natively.
config ATH6KL_SKIP_ABI_VERSION_CHECK
bool "Skip ABI version check support"
depends on ATH6K_LEGACY
help
Forces the driver to disable ABI version check. Caution: Incompatilbity between the host driver and target firmware may lead to unknown side effects.
config ATH6KL_BT_UART_FC_POLARITY
int "UART Flow Control Polarity"
depends on ATH6KL_LEGACY
default 0
help
Configures the polarity of UART Flow Control. A value of 0 implies active low and is the default setting. Set it to 1 for active high.
config ATH6KL_DEBUG
bool "Debug support"
depends on ATH6K_LEGACY
help
Enables debug support
config ATH6KL_ENABLE_HOST_DEBUG
bool "Host Debug support"
depends on ATH6KL_DEBUG
help
Enables debug support in the driver
config ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
bool "Target Debug support - Enable UART prints"
depends on ATH6KL_DEBUG
help
Enables uart prints
config AR600x_DEBUG_UART_TX_PIN
int "GPIO"
depends on ATH6KL_ENABLE_TARGET_DEBUG_PRINTS
default 8
help
WLAN GPIO to be used for Debug UART (Tx)
config ATH6KL_DISABLE_TARGET_DBGLOGS
bool "Target Debug support - Disable Debug logs"
depends on ATH6KL_DEBUG
help
Enables debug logs

159
drivers/staging/ath6kl/Makefile Normal file
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@ -0,0 +1,159 @@
#------------------------------------------------------------------------------
# Copyright (c) 2004-2010 Atheros Communications Inc.
# All rights reserved.
#
#
#
# Permission to use, copy, modify, and/or distribute this software for any
# purpose with or without fee is hereby granted, provided that the above
# copyright notice and this permission notice appear in all copies.
#
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
#
#
#
# Author(s): ="Atheros"
#------------------------------------------------------------------------------
ccflags-y += -I$(obj)/include
ccflags-y += -I$(obj)/include/common
ccflags-y += -I$(obj)/wlan/include
ccflags-y += -I$(obj)/os/linux/include
ccflags-y += -I$(obj)/os
ccflags-y += -I$(obj)/bmi/include
ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
ifeq ($(CONFIG_AR600x_SD31_XXX),y)
ccflags-y += -DAR600x_SD31_XXX
endif
ifeq ($(CONFIG_AR600x_WB31_XXX),y)
ccflags-y += -DAR600x_WB31_XXX
endif
ifeq ($(CONFIG_AR600x_SD32_XXX),y)
ccflags-y += -DAR600x_SD32_XXX
endif
ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
ccflags-y += -DAR600x_CUSTOM_XXX
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
ccflags-y += -DENABLE_COEXISTENCE
endif
ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
ccflags-y += -DAR600x_DUAL_ANTENNA
endif
ifeq ($(CONFIG_AR600x_SINGLE_ANTENNA),y)
ccflags-y += -DAR600x_SINGLE_ANTENNA
endif
ifeq ($(CONFIG_AR600x_BT_QCOM),y)
ccflags-y += -DAR600x_BT_QCOM
endif
ifeq ($(CONFIG_AR600x_BT_CSR),y)
ccflags-y += -DAR600x_BT_CSR
endif
ifeq ($(CONFIG_AR600x_BT_AR3001),y)
ccflags-y += -DAR600x_BT_AR3001
endif
ifeq ($(CONFIG_ATH6KL_HCI_BRIDGE),y)
ccflags-y += -DATH_AR6K_ENABLE_GMBOX
ccflags-y += -DHCI_TRANSPORT_SDIO
ccflags-y += -DSETUPHCI_ENABLED
ccflags-y += -DSETUPBTDEV_ENABLED
ath6kl-y += htc2/AR6000/ar6k_gmbox.o
ath6kl-y += htc2/AR6000/ar6k_gmbox_hciuart.o
ath6kl-y += miscdrv/ar3kconfig.o
ath6kl-y += miscdrv/ar3kps/ar3kpsconfig.o
ath6kl-y += miscdrv/ar3kps/ar3kpsparser.o
endif
ifeq ($(CONFIG_ATH6KL_CONFIG_GPIO_BT_RESET),y)
ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
endif
ifeq ($(CONFIG_ATH6KL_CFG80211),y)
ccflags-y += -DATH6K_CONFIG_CFG80211
ath6kl-y += os/linux/cfg80211.o
endif
ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
ccflags-y += -DHTC_RAW_INTERFACE
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_HOST_DEBUG),y)
ccflags-y += -DDEBUG
ccflags-y += -DATH_DEBUG_MODULE
endif
ifeq ($(CONFIG_ATH6KL_ENABLE_TARGET_DEBUG_PRINTS),y)
ccflags-y += -DENABLEUARTPRINT_SET
endif
ifeq ($(CONFIG_ATH6KL_DISABLE_TARGET_DBGLOGS),y)
ccflags-y += -DATH6KL_DISABLE_TARGET_DBGLOGS
endif
ifeq ($(CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER),y)
ccflags-y += -DATH6KL_CONFIG_HIF_VIRTUAL_SCATTER
endif
ifeq ($(CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK),y)
ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
endif
ccflags-y += -DLINUX -DKERNEL_2_6
ccflags-y += -DTCMD
ccflags-y += -DSEND_EVENT_TO_APP
ccflags-y += -DUSER_KEYS
ccflags-y += -DNO_SYNC_FLUSH
ccflags-y += -DHTC_EP_STAT_PROFILING
ccflags-y += -DATH_AR6K_11N_SUPPORT
ccflags-y += -DWAPI_ENABLE
ccflags-y += -DCHECKSUM_OFFLOAD
ccflags-y += -DWLAN_HEADERS
ccflags-y += -DINIT_MODE_DRV_ENABLED
ccflags-y += -DBMIENABLE_SET
obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
ath6kl-y += htc2/AR6000/ar6k.o
ath6kl-y += htc2/AR6000/ar6k_events.o
ath6kl-y += htc2/htc_send.o
ath6kl-y += htc2/htc_recv.o
ath6kl-y += htc2/htc_services.o
ath6kl-y += htc2/htc.o
ath6kl-y += bmi/src/bmi.o
ath6kl-y += os/linux/ar6000_drv.o
ath6kl-y += os/linux/ar6000_raw_if.o
ath6kl-y += os/linux/ar6000_pm.o
ath6kl-y += os/linux/netbuf.o
ath6kl-y += os/linux/wireless_ext.o
ath6kl-y += os/linux/ioctl.o
ath6kl-y += os/linux/hci_bridge.o
ath6kl-y += os/linux/ar6k_pal.o
ath6kl-y += miscdrv/common_drv.o
ath6kl-y += miscdrv/credit_dist.o
ath6kl-y += wmi/wmi.o
ath6kl-y += reorder/rcv_aggr.o
ath6kl-y += wlan/src/wlan_node.o
ath6kl-y += wlan/src/wlan_recv_beacon.o
ath6kl-y += wlan/src/wlan_utils.o
# ATH_HIF_TYPE := sdio
ccflags-y += -I$(obj)/hif/sdio/linux_sdio/include
ccflags-y += -DSDIO
ath6kl-y += hif/sdio/linux_sdio/src/hif.o
ath6kl-y += hif/sdio/linux_sdio/src/hif_scatter.o

8
drivers/staging/ath6kl/TODO Normal file
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@ -0,0 +1,8 @@
- The driver is a stop-gap measure until a proper mac80211 driver is available.
- The driver does not conform to the Linux coding style.
- The driver has been tested on a wide variety of embedded platforms running different versions of the Linux kernel but may still have bringup/performance issues with a new platform.
- Pls use the following link to get information about the driver's architecture, exposed APIs, supported features, limitations, testing, hardware availability and other details.
http://wireless.kernel.org/en/users/Drivers/ath6kl
- Pls send any patches to
- Greg Kroah-Hartman <greg@kroah.com>
- Vipin Mehta <vmehta@atheros.com>

55
drivers/staging/ath6kl/bmi/include/bmi_internal.h Normal file
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@ -0,0 +1,55 @@
//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef BMI_INTERNAL_H
#define BMI_INTERNAL_H
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME bmi
#include "a_debug.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "bmi_msg.h"
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
#define BMI_COMMUNICATION_TIMEOUT 100000
/* ------ Global Variable Declarations ------- */
static A_BOOL bmiDone;
A_STATUS
bmiBufferSend(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
bmiBufferReceive(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length,
A_BOOL want_timeout);
#endif

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drivers/staging/ath6kl/bmi/src/bmi.c Normal file
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87
drivers/staging/ath6kl/hif/common/hif_sdio_common.h Normal file
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//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// common header file for HIF modules designed for SDIO
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef HIF_SDIO_COMMON_H_
#define HIF_SDIO_COMMON_H_
/* SDIO manufacturer ID and Codes */
#define MANUFACTURER_ID_AR6002_BASE 0x200
#define MANUFACTURER_ID_AR6003_BASE 0x300
#define MANUFACTURER_ID_AR6K_BASE_MASK 0xFF00
#define FUNCTION_CLASS 0x0
#define MANUFACTURER_CODE 0x271 /* Atheros */
/* Mailbox address in SDIO address space */
#define HIF_MBOX_BASE_ADDR 0x800
#define HIF_MBOX_WIDTH 0x800
#define HIF_MBOX_START_ADDR(mbox) \
( HIF_MBOX_BASE_ADDR + mbox * HIF_MBOX_WIDTH)
#define HIF_MBOX_END_ADDR(mbox) \
(HIF_MBOX_START_ADDR(mbox) + HIF_MBOX_WIDTH - 1)
/* extended MBOX address for larger MBOX writes to MBOX 0*/
#define HIF_MBOX0_EXTENDED_BASE_ADDR 0x2800
#define HIF_MBOX0_EXTENDED_WIDTH_AR6002 (6*1024)
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003 (18*1024)
/* version 1 of the chip has only a 12K extended mbox range */
#define HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1 0x4000
#define HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1 (12*1024)
/* GMBOX addresses */
#define HIF_GMBOX_BASE_ADDR 0x7000
#define HIF_GMBOX_WIDTH 0x4000
/* for SDIO we recommend a 128-byte block size */
#define HIF_DEFAULT_IO_BLOCK_SIZE 128
/* set extended MBOX window information for SDIO interconnects */
static INLINE void SetExtendedMboxWindowInfo(A_UINT16 Manfid, HIF_DEVICE_MBOX_INFO *pInfo)
{
switch (Manfid & MANUFACTURER_ID_AR6K_BASE_MASK) {
case MANUFACTURER_ID_AR6002_BASE :
/* MBOX 0 has an extended range */
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR;
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6002;
break;
case MANUFACTURER_ID_AR6003_BASE :
/* MBOX 0 has an extended range */
pInfo->MboxProp[0].ExtendedAddress = HIF_MBOX0_EXTENDED_BASE_ADDR_AR6003_V1;
pInfo->MboxProp[0].ExtendedSize = HIF_MBOX0_EXTENDED_WIDTH_AR6003_V1;
pInfo->GMboxAddress = HIF_GMBOX_BASE_ADDR;
pInfo->GMboxSize = HIF_GMBOX_WIDTH;
break;
default:
A_ASSERT(FALSE);
break;
}
}
/* special CCCR (func 0) registers */
#define CCCR_SDIO_IRQ_MODE_REG 0xF0 /* interrupt mode register */
#define SDIO_IRQ_MODE_ASYNC_4BIT_IRQ (1 << 0) /* mode to enable special 4-bit interrupt assertion without clock*/
#endif /*HIF_SDIO_COMMON_H_*/

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//------------------------------------------------------------------------------
// <copyright file="hif_internal.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// internal header file for hif layer
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _HIF_INTERNAL_H_
#define _HIF_INTERNAL_H_
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "hif.h"
#include "../../../common/hif_sdio_common.h"
#include <linux/scatterlist.h>
#define HIF_LINUX_MMC_SCATTER_SUPPORT
#define BUS_REQUEST_MAX_NUM 64
#define SDIO_CLOCK_FREQUENCY_DEFAULT 25000000
#define SDWLAN_ENABLE_DISABLE_TIMEOUT 20
#define FLAGS_CARD_ENAB 0x02
#define FLAGS_CARD_IRQ_UNMSK 0x04
#define HIF_MBOX_BLOCK_SIZE HIF_DEFAULT_IO_BLOCK_SIZE
#define HIF_MBOX0_BLOCK_SIZE 1
#define HIF_MBOX1_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX2_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
#define HIF_MBOX3_BLOCK_SIZE HIF_MBOX_BLOCK_SIZE
struct _HIF_SCATTER_REQ_PRIV;
typedef struct bus_request {
struct bus_request *next; /* link list of available requests */
struct bus_request *inusenext; /* link list of in use requests */
struct semaphore sem_req;
A_UINT32 address; /* request data */
A_UCHAR *buffer;
A_UINT32 length;
A_UINT32 request;
void *context;
A_STATUS status;
struct _HIF_SCATTER_REQ_PRIV *pScatterReq; /* this request is a scatter request */
} BUS_REQUEST;
struct hif_device {
struct sdio_func *func;
spinlock_t asynclock;
struct task_struct* async_task; /* task to handle async commands */
struct semaphore sem_async; /* wake up for async task */
int async_shutdown; /* stop the async task */
struct completion async_completion; /* thread completion */
BUS_REQUEST *asyncreq; /* request for async tasklet */
BUS_REQUEST *taskreq; /* async tasklet data */
spinlock_t lock;
BUS_REQUEST *s_busRequestFreeQueue; /* free list */
BUS_REQUEST busRequest[BUS_REQUEST_MAX_NUM]; /* available bus requests */
void *claimedContext;
HTC_CALLBACKS htcCallbacks;
A_UINT8 *dma_buffer;
DL_LIST ScatterReqHead; /* scatter request list head */
A_BOOL scatter_enabled; /* scatter enabled flag */
A_BOOL is_suspend;
A_BOOL is_disabled;
atomic_t irqHandling;
HIF_DEVICE_POWER_CHANGE_TYPE powerConfig;
const struct sdio_device_id *id;
};
#define HIF_DMA_BUFFER_SIZE (32 * 1024)
#define CMD53_FIXED_ADDRESS 1
#define CMD53_INCR_ADDRESS 2
BUS_REQUEST *hifAllocateBusRequest(HIF_DEVICE *device);
void hifFreeBusRequest(HIF_DEVICE *device, BUS_REQUEST *busrequest);
void AddToAsyncList(HIF_DEVICE *device, BUS_REQUEST *busrequest);
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define MAX_SCATTER_REQUESTS 4
#define MAX_SCATTER_ENTRIES_PER_REQ 16
#define MAX_SCATTER_REQ_TRANSFER_SIZE 32*1024
typedef struct _HIF_SCATTER_REQ_PRIV {
HIF_SCATTER_REQ *pHifScatterReq; /* HIF scatter request with allocated entries */
HIF_DEVICE *device; /* this device */
BUS_REQUEST *busrequest; /* request associated with request */
/* scatter list for linux */
struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ];
} HIF_SCATTER_REQ_PRIV;
#define ATH_DEBUG_SCATTER ATH_DEBUG_MAKE_MODULE_MASK(0)
A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo);
void CleanupHIFScatterResources(HIF_DEVICE *device);
A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest);
#else // HIF_LINUX_MMC_SCATTER_SUPPORT
static inline A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
{
return A_ENOTSUP;
}
static inline A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
{
return A_ENOTSUP;
}
#define CleanupHIFScatterResources(d) { }
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT
#endif // _HIF_INTERNAL_H_

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//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// HIF scatter implementation
//
// Author(s): ="Atheros"
//==============================================================================
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
#include <linux/mmc/sdio.h>
#include <linux/kthread.h>
#include "hif_internal.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
#ifdef HIF_LINUX_MMC_SCATTER_SUPPORT
#define _CMD53_ARG_READ 0
#define _CMD53_ARG_WRITE 1
#define _CMD53_ARG_BLOCK_BASIS 1
#define _CMD53_ARG_FIXED_ADDRESS 0
#define _CMD53_ARG_INCR_ADDRESS 1
#define SDIO_SET_CMD53_ARG(arg,rw,func,mode,opcode,address,bytes_blocks) \
(arg) = (((rw) & 1) << 31) | \
(((func) & 0x7) << 28) | \
(((mode) & 1) << 27) | \
(((opcode) & 1) << 26) | \
(((address) & 0x1FFFF) << 9) | \
((bytes_blocks) & 0x1FF)
static void FreeScatterReq(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
{
unsigned long flag;
spin_lock_irqsave(&device->lock, flag);
DL_ListInsertTail(&device->ScatterReqHead, &pReq->ListLink);
spin_unlock_irqrestore(&device->lock, flag);
}
static HIF_SCATTER_REQ *AllocScatterReq(HIF_DEVICE *device)
{
DL_LIST *pItem;
unsigned long flag;
spin_lock_irqsave(&device->lock, flag);
pItem = DL_ListRemoveItemFromHead(&device->ScatterReqHead);
spin_unlock_irqrestore(&device->lock, flag);
if (pItem != NULL) {
return A_CONTAINING_STRUCT(pItem, HIF_SCATTER_REQ, ListLink);
}
return NULL;
}
/* called by async task to perform the operation synchronously using direct MMC APIs */
A_STATUS DoHifReadWriteScatter(HIF_DEVICE *device, BUS_REQUEST *busrequest)
{
int i;
A_UINT8 rw;
A_UINT8 opcode;
struct mmc_request mmcreq;
struct mmc_command cmd;
struct mmc_data data;
HIF_SCATTER_REQ_PRIV *pReqPriv;
HIF_SCATTER_REQ *pReq;
A_STATUS status = A_OK;
struct scatterlist *pSg;
pReqPriv = busrequest->pScatterReq;
A_ASSERT(pReqPriv != NULL);
pReq = pReqPriv->pHifScatterReq;
memset(&mmcreq, 0, sizeof(struct mmc_request));
memset(&cmd, 0, sizeof(struct mmc_command));
memset(&data, 0, sizeof(struct mmc_data));
data.blksz = HIF_MBOX_BLOCK_SIZE;
data.blocks = pReq->TotalLength / HIF_MBOX_BLOCK_SIZE;
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: (%s) Address: 0x%X, (BlockLen: %d, BlockCount: %d) , (tot:%d,sg:%d)\n",
(pReq->Request & HIF_WRITE) ? "WRITE":"READ", pReq->Address, data.blksz, data.blocks,
pReq->TotalLength,pReq->ValidScatterEntries));
if (pReq->Request & HIF_WRITE) {
rw = _CMD53_ARG_WRITE;
data.flags = MMC_DATA_WRITE;
} else {
rw = _CMD53_ARG_READ;
data.flags = MMC_DATA_READ;
}
if (pReq->Request & HIF_FIXED_ADDRESS) {
opcode = _CMD53_ARG_FIXED_ADDRESS;
} else {
opcode = _CMD53_ARG_INCR_ADDRESS;
}
/* fill SG entries */
pSg = pReqPriv->sgentries;
sg_init_table(pSg, pReq->ValidScatterEntries);
/* assemble SG list */
for (i = 0 ; i < pReq->ValidScatterEntries ; i++, pSg++) {
/* setup each sg entry */
if ((unsigned long)pReq->ScatterList[i].pBuffer & 0x3) {
/* note some scatter engines can handle unaligned buffers, print this
* as informational only */
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER,
("HIF: (%s) Scatter Buffer is unaligned 0x%lx\n",
pReq->Request & HIF_WRITE ? "WRITE":"READ",
(unsigned long)pReq->ScatterList[i].pBuffer));
}
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, (" %d: Addr:0x%lX, Len:%d \n",
i,(unsigned long)pReq->ScatterList[i].pBuffer,pReq->ScatterList[i].Length));
sg_set_buf(pSg, pReq->ScatterList[i].pBuffer, pReq->ScatterList[i].Length);
}
/* set scatter-gather table for request */
data.sg = pReqPriv->sgentries;
data.sg_len = pReq->ValidScatterEntries;
/* set command argument */
SDIO_SET_CMD53_ARG(cmd.arg,
rw,
device->func->num,
_CMD53_ARG_BLOCK_BASIS,
opcode,
pReq->Address,
data.blocks);
cmd.opcode = SD_IO_RW_EXTENDED;
cmd.flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_ADTC;
mmcreq.cmd = &cmd;
mmcreq.data = &data;
mmc_set_data_timeout(&data, device->func->card);
/* synchronous call to process request */
mmc_wait_for_req(device->func->card->host, &mmcreq);
if (cmd.error) {
status = A_ERROR;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: cmd error: %d \n",cmd.error));
}
if (data.error) {
status = A_ERROR;
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: data error: %d \n",data.error));
}
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("HIF-SCATTER: FAILED!!! (%s) Address: 0x%X, Block mode (BlockLen: %d, BlockCount: %d)\n",
(pReq->Request & HIF_WRITE) ? "WRITE":"READ",pReq->Address, data.blksz, data.blocks));
}
/* set completion status, fail or success */
pReq->CompletionStatus = status;
if (pReq->Request & HIF_ASYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: async_task completion routine req: 0x%lX (%d)\n",(unsigned long)busrequest, status));
/* complete the request */
A_ASSERT(pReq->CompletionRoutine != NULL);
pReq->CompletionRoutine(pReq);
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER async_task upping busrequest : 0x%lX (%d)\n", (unsigned long)busrequest,status));
/* signal wait */
up(&busrequest->sem_req);
}
return status;
}
/* callback to issue a read-write scatter request */
static A_STATUS HifReadWriteScatter(HIF_DEVICE *device, HIF_SCATTER_REQ *pReq)
{
A_STATUS status = A_EINVAL;
A_UINT32 request = pReq->Request;
HIF_SCATTER_REQ_PRIV *pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
do {
A_ASSERT(pReqPriv != NULL);
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: total len: %d Scatter Entries: %d\n",
pReq->TotalLength, pReq->ValidScatterEntries));
if (!(request & HIF_EXTENDED_IO)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid command type: 0x%08x\n", request));
break;
}
if (!(request & (HIF_SYNCHRONOUS | HIF_ASYNCHRONOUS))) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid execution mode: 0x%08x\n", request));
break;
}
if (!(request & HIF_BLOCK_BASIS)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid data mode: 0x%08x\n", request));
break;
}
if (pReq->TotalLength > MAX_SCATTER_REQ_TRANSFER_SIZE) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,
("HIF-SCATTER: Invalid length: %d \n", pReq->TotalLength));
break;
}
if (pReq->TotalLength == 0) {
A_ASSERT(FALSE);
break;
}
/* add bus request to the async list for the async I/O thread to process */
AddToAsyncList(device, pReqPriv->busrequest);
if (request & HIF_SYNCHRONOUS) {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued sync req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
/* signal thread and wait */
up(&device->sem_async);
if (down_interruptible(&pReqPriv->busrequest->sem_req) != 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR,("HIF-SCATTER: interrupted! \n"));
/* interrupted, exit */
status = A_ERROR;
break;
} else {
status = pReq->CompletionStatus;
}
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_SCATTER, ("HIF-SCATTER: queued async req: 0x%lX\n", (unsigned long)pReqPriv->busrequest));
/* wake thread, it will process and then take care of the async callback */
up(&device->sem_async);
status = A_OK;
}
} while (FALSE);
if (A_FAILED(status) && (request & HIF_ASYNCHRONOUS)) {
pReq->CompletionStatus = status;
pReq->CompletionRoutine(pReq);
status = A_OK;
}
return status;
}
/* setup of HIF scatter resources */
A_STATUS SetupHIFScatterSupport(HIF_DEVICE *device, HIF_DEVICE_SCATTER_SUPPORT_INFO *pInfo)
{
A_STATUS status = A_ERROR;
int i;
HIF_SCATTER_REQ_PRIV *pReqPriv;
BUS_REQUEST *busrequest;
do {
/* check if host supports scatter requests and it meets our requirements */
if (device->func->card->host->max_hw_segs < MAX_SCATTER_ENTRIES_PER_REQ) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : host only supports scatter of : %d entries, need: %d \n",
device->func->card->host->max_hw_segs, MAX_SCATTER_ENTRIES_PER_REQ));
status = A_ENOTSUP;
break;
}
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,("HIF-SCATTER Enabled: max scatter req : %d entries: %d \n",
MAX_SCATTER_REQUESTS, MAX_SCATTER_ENTRIES_PER_REQ));
for (i = 0; i < MAX_SCATTER_REQUESTS; i++) {
/* allocate the private request blob */
pReqPriv = (HIF_SCATTER_REQ_PRIV *)A_MALLOC(sizeof(HIF_SCATTER_REQ_PRIV));
if (NULL == pReqPriv) {
break;
}
A_MEMZERO(pReqPriv, sizeof(HIF_SCATTER_REQ_PRIV));
/* save the device instance*/
pReqPriv->device = device;
/* allocate the scatter request */
pReqPriv->pHifScatterReq = (HIF_SCATTER_REQ *)A_MALLOC(sizeof(HIF_SCATTER_REQ) +
(MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(HIF_SCATTER_ITEM)));
if (NULL == pReqPriv->pHifScatterReq) {
A_FREE(pReqPriv);
break;
}
/* just zero the main part of the scatter request */
A_MEMZERO(pReqPriv->pHifScatterReq, sizeof(HIF_SCATTER_REQ));
/* back pointer to the private struct */
pReqPriv->pHifScatterReq->HIFPrivate[0] = pReqPriv;
/* allocate a bus request for this scatter request */
busrequest = hifAllocateBusRequest(device);
if (NULL == busrequest) {
A_FREE(pReqPriv->pHifScatterReq);
A_FREE(pReqPriv);
break;
}
/* assign the scatter request to this bus request */
busrequest->pScatterReq = pReqPriv;
/* point back to the request */
pReqPriv->busrequest = busrequest;
/* add it to the scatter pool */
FreeScatterReq(device,pReqPriv->pHifScatterReq);
}
if (i != MAX_SCATTER_REQUESTS) {
status = A_NO_MEMORY;
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HIF-SCATTER : failed to alloc scatter resources !\n"));
break;
}
/* set scatter function pointers */
pInfo->pAllocateReqFunc = AllocScatterReq;
pInfo->pFreeReqFunc = FreeScatterReq;
pInfo->pReadWriteScatterFunc = HifReadWriteScatter;
pInfo->MaxScatterEntries = MAX_SCATTER_ENTRIES_PER_REQ;
pInfo->MaxTransferSizePerScatterReq = MAX_SCATTER_REQ_TRANSFER_SIZE;
status = A_OK;
} while (FALSE);
if (A_FAILED(status)) {
CleanupHIFScatterResources(device);
}
return status;
}
/* clean up scatter support */
void CleanupHIFScatterResources(HIF_DEVICE *device)
{
HIF_SCATTER_REQ_PRIV *pReqPriv;
HIF_SCATTER_REQ *pReq;
/* empty the free list */
while (1) {
pReq = AllocScatterReq(device);
if (NULL == pReq) {
break;
}
pReqPriv = (HIF_SCATTER_REQ_PRIV *)pReq->HIFPrivate[0];
A_ASSERT(pReqPriv != NULL);
if (pReqPriv->busrequest != NULL) {
pReqPriv->busrequest->pScatterReq = NULL;
/* free bus request */
hifFreeBusRequest(device, pReqPriv->busrequest);
pReqPriv->busrequest = NULL;
}
if (pReqPriv->pHifScatterReq != NULL) {
A_FREE(pReqPriv->pHifScatterReq);
pReqPriv->pHifScatterReq = NULL;
}
A_FREE(pReqPriv);
}
}
#endif // HIF_LINUX_MMC_SCATTER_SUPPORT

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//------------------------------------------------------------------------------
// <copyright file="ar6k.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// AR6K device layer that handles register level I/O
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef AR6K_H_
#define AR6K_H_
#include "hci_transport_api.h"
#include "../htc_debug.h"
#define AR6K_MAILBOXES 4
/* HTC runs over mailbox 0 */
#define HTC_MAILBOX 0
#define AR6K_TARGET_DEBUG_INTR_MASK 0x01
#define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
INT_STATUS_ENABLE_CPU_MASK | \
INT_STATUS_ENABLE_COUNTER_MASK)
//#define MBOXHW_UNIT_TEST 1
#include "athstartpack.h"
typedef PREPACK struct _AR6K_IRQ_PROC_REGISTERS {
A_UINT8 host_int_status;
A_UINT8 cpu_int_status;
A_UINT8 error_int_status;
A_UINT8 counter_int_status;
A_UINT8 mbox_frame;
A_UINT8 rx_lookahead_valid;
A_UINT8 host_int_status2;
A_UINT8 gmbox_rx_avail;
A_UINT32 rx_lookahead[2];
A_UINT32 rx_gmbox_lookahead_alias[2];
} POSTPACK AR6K_IRQ_PROC_REGISTERS;
#define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
typedef PREPACK struct _AR6K_IRQ_ENABLE_REGISTERS {
A_UINT8 int_status_enable;
A_UINT8 cpu_int_status_enable;
A_UINT8 error_status_enable;
A_UINT8 counter_int_status_enable;
} POSTPACK AR6K_IRQ_ENABLE_REGISTERS;
typedef PREPACK struct _AR6K_GMBOX_CTRL_REGISTERS {
A_UINT8 int_status_enable;
} POSTPACK AR6K_GMBOX_CTRL_REGISTERS;
#include "athendpack.h"
#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
#define AR6K_REG_IO_BUFFER_SIZE 32
#define AR6K_MAX_REG_IO_BUFFERS 8
#define FROM_DMA_BUFFER TRUE
#define TO_DMA_BUFFER FALSE
#define AR6K_SCATTER_ENTRIES_PER_REQ 16
#define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
#define AR6K_SCATTER_REQS 4
#define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
#ifndef A_CACHE_LINE_PAD
#define A_CACHE_LINE_PAD 128
#endif
#define AR6K_MIN_SCATTER_ENTRIES_PER_REQ 2
#define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER 4*1024
/* buffers for ASYNC I/O */
typedef struct AR6K_ASYNC_REG_IO_BUFFER {
HTC_PACKET HtcPacket; /* we use an HTC packet as a wrapper for our async register-based I/O */
A_UINT8 _Pad1[A_CACHE_LINE_PAD];
A_UINT8 Buffer[AR6K_REG_IO_BUFFER_SIZE]; /* cache-line safe with pads around */
A_UINT8 _Pad2[A_CACHE_LINE_PAD];
} AR6K_ASYNC_REG_IO_BUFFER;
typedef struct _AR6K_GMBOX_INFO {
void *pProtocolContext;
A_STATUS (*pMessagePendingCallBack)(void *pContext, A_UINT8 LookAheadBytes[], int ValidBytes);
A_STATUS (*pCreditsPendingCallback)(void *pContext, int NumCredits, A_BOOL CreditIRQEnabled);
void (*pTargetFailureCallback)(void *pContext, A_STATUS Status);
void (*pStateDumpCallback)(void *pContext);
A_BOOL CreditCountIRQEnabled;
} AR6K_GMBOX_INFO;
typedef struct _AR6K_DEVICE {
A_MUTEX_T Lock;
A_UINT8 _Pad1[A_CACHE_LINE_PAD];
AR6K_IRQ_PROC_REGISTERS IrqProcRegisters; /* cache-line safe with pads around */
A_UINT8 _Pad2[A_CACHE_LINE_PAD];
AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters; /* cache-line safe with pads around */
A_UINT8 _Pad3[A_CACHE_LINE_PAD];
void *HIFDevice;
A_UINT32 BlockSize;
A_UINT32 BlockMask;
HIF_DEVICE_MBOX_INFO MailBoxInfo;
HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc;
void *HTCContext;
HTC_PACKET_QUEUE RegisterIOList;
AR6K_ASYNC_REG_IO_BUFFER RegIOBuffers[AR6K_MAX_REG_IO_BUFFERS];
void (*TargetFailureCallback)(void *Context);
A_STATUS (*MessagePendingCallback)(void *Context,
A_UINT32 LookAheads[],
int NumLookAheads,
A_BOOL *pAsyncProc,
int *pNumPktsFetched);
HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode;
HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent;
A_BOOL HifAttached;
HIF_DEVICE_IRQ_YIELD_PARAMS HifIRQYieldParams;
A_BOOL DSRCanYield;
int CurrentDSRRecvCount;
HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo;
DL_LIST ScatterReqHead;
A_BOOL ScatterIsVirtual;
int MaxRecvBundleSize;
int MaxSendBundleSize;
AR6K_GMBOX_INFO GMboxInfo;
A_BOOL GMboxEnabled;
AR6K_GMBOX_CTRL_REGISTERS GMboxControlRegisters;
int RecheckIRQStatusCnt;
} AR6K_DEVICE;
#define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
#define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
#define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
A_STATUS DevSetup(AR6K_DEVICE *pDev);
void DevCleanup(AR6K_DEVICE *pDev);
A_STATUS DevUnmaskInterrupts(AR6K_DEVICE *pDev);
A_STATUS DevMaskInterrupts(AR6K_DEVICE *pDev);
A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
A_UINT32 *pLookAhead,
int TimeoutMS);
A_STATUS DevRWCompletionHandler(void *context, A_STATUS status);
A_STATUS DevDsrHandler(void *context);
A_STATUS DevCheckPendingRecvMsgsAsync(void *context);
void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev);
void DevDumpRegisters(AR6K_DEVICE *pDev,
AR6K_IRQ_PROC_REGISTERS *pIrqProcRegs,
AR6K_IRQ_ENABLE_REGISTERS *pIrqEnableRegs);
#define DEV_STOP_RECV_ASYNC TRUE
#define DEV_STOP_RECV_SYNC FALSE
#define DEV_ENABLE_RECV_ASYNC TRUE
#define DEV_ENABLE_RECV_SYNC FALSE
A_STATUS DevStopRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
A_STATUS DevEnableRecv(AR6K_DEVICE *pDev, A_BOOL ASyncMode);
A_STATUS DevEnableInterrupts(AR6K_DEVICE *pDev);
A_STATUS DevDisableInterrupts(AR6K_DEVICE *pDev);
A_STATUS DevWaitForPendingRecv(AR6K_DEVICE *pDev,A_UINT32 TimeoutInMs,A_BOOL *pbIsRecvPending);
#define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
#define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
#define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
static INLINE A_STATUS DevSendPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 SendLength) {
A_UINT32 paddedLength;
A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
A_STATUS status;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, SendLength);
#if 0
if (paddedLength > pPacket->BufferLength) {
A_ASSERT(FALSE);
if (pPacket->Completion != NULL) {
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
return A_OK;
}
return A_EINVAL;
}
#endif
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
paddedLength,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
sync ? "SYNC" : "ASYNC"));
status = HIFReadWrite(pDev->HIFDevice,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
pPacket->pBuffer,
paddedLength, /* the padded length */
sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
} else {
if (status == A_PENDING) {
status = A_OK;
}
}
return status;
}
static INLINE A_STATUS DevRecvPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 RecvLength) {
A_UINT32 paddedLength;
A_STATUS status;
A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, RecvLength);
if (paddedLength > pPacket->BufferLength) {
A_ASSERT(FALSE);
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
paddedLength,RecvLength,pPacket->BufferLength));
if (pPacket->Completion != NULL) {
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
return A_OK;
}
return A_EINVAL;
}
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
paddedLength,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
sync ? "SYNC" : "ASYNC"));
status = HIFReadWrite(pDev->HIFDevice,
pDev->MailBoxInfo.MboxAddresses[HTC_MAILBOX],
pPacket->pBuffer,
paddedLength,
sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
}
return status;
}
#define DEV_CHECK_RECV_YIELD(pDev) \
((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
#define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
#define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
/**************************************************/
/****** Scatter Function and Definitions
*
*
*/
A_STATUS DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ *pReq, A_BOOL FromDMA);
/* copy any READ data back into scatter list */
#define DEV_FINISH_SCATTER_OPERATION(pR) \
if (A_SUCCESS((pR)->CompletionStatus) && \
!((pR)->Request & HIF_WRITE) && \
((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
(pR)->CompletionStatus = DevCopyScatterListToFromDMABuffer((pR),FROM_DMA_BUFFER); \
}
/* copy any WRITE data to bounce buffer */
static INLINE A_STATUS DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ *pReq) {
if ((pReq->Request & HIF_WRITE) && (pReq->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) {
return DevCopyScatterListToFromDMABuffer(pReq,TO_DMA_BUFFER);
} else {
return A_OK;
}
}
A_STATUS DevSetupMsgBundling(AR6K_DEVICE *pDev, int MaxMsgsPerTransfer);
#define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
#define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
#define DEV_ALLOC_SCATTER_REQ(pDev) \
(pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
#define DEV_FREE_SCATTER_REQ(pDev,pR) \
(pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
#define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
#define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
#define DEV_SCATTER_READ TRUE
#define DEV_SCATTER_WRITE FALSE
#define DEV_SCATTER_ASYNC TRUE
#define DEV_SCATTER_SYNC FALSE
A_STATUS DevSubmitScatterRequest(AR6K_DEVICE *pDev, HIF_SCATTER_REQ *pScatterReq, A_BOOL Read, A_BOOL Async);
#ifdef MBOXHW_UNIT_TEST
A_STATUS DoMboxHWTest(AR6K_DEVICE *pDev);
#endif
/* completely virtual */
typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO {
A_UINT8 *pVirtDmaBuffer; /* dma-able buffer - CPU accessible address */
A_UINT8 DataArea[1]; /* start of data area */
} DEV_SCATTER_DMA_VIRTUAL_INFO;
void DumpAR6KDevState(AR6K_DEVICE *pDev);
/**************************************************/
/****** GMBOX functions and definitions
*
*
*/
#ifdef ATH_AR6K_ENABLE_GMBOX
void DevCleanupGMbox(AR6K_DEVICE *pDev);
A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev);
A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev);
void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev);
#else
/* compiled out */
#define DevCleanupGMbox(p)
#define DevCheckGMboxInterrupts(p) A_OK
#define DevNotifyGMboxTargetFailure(p)
static INLINE A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev) {
pDev->GMboxEnabled = FALSE;
return A_OK;
}
#endif
#ifdef ATH_AR6K_ENABLE_GMBOX
/* GMBOX protocol modules must expose each of these internal APIs */
HCI_TRANSPORT_HANDLE GMboxAttachProtocol(AR6K_DEVICE *pDev, HCI_TRANSPORT_CONFIG_INFO *pInfo);
A_STATUS GMboxProtocolInstall(AR6K_DEVICE *pDev);
void GMboxProtocolUninstall(AR6K_DEVICE *pDev);
/* API used by GMBOX protocol modules */
AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle);
#define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
{ \
(pDev)->GMboxInfo.pProtocolContext = (context); \
(pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
(pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
(pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
(pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
}
#define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength);
A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength);
#define PROC_IO_ASYNC TRUE
#define PROC_IO_SYNC FALSE
typedef enum GMBOX_IRQ_ACTION_TYPE {
GMBOX_ACTION_NONE = 0,
GMBOX_DISABLE_ALL,
GMBOX_ERRORS_IRQ_ENABLE,
GMBOX_RECV_IRQ_ENABLE,
GMBOX_RECV_IRQ_DISABLE,
GMBOX_CREDIT_IRQ_ENABLE,
GMBOX_CREDIT_IRQ_DISABLE,
} GMBOX_IRQ_ACTION_TYPE;
A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE, A_BOOL AsyncMode);
A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits);
A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize);
A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes);
A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int SignalNumber, int AckTimeoutMS);
#endif
#endif /*AR6K_H_*/

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//------------------------------------------------------------------------------
// <copyright file="ar6k_events.c" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// AR6K Driver layer event handling (i.e. interrupts, message polling)
//
// Author(s): ="Atheros"
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "AR6002/hw2.0/hw/mbox_host_reg.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
#include "htc_packet.h"
#include "ar6k.h"
extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev);
#define DELAY_PER_INTERVAL_MS 10 /* 10 MS delay per polling interval */
/* completion routine for ALL HIF layer async I/O */
A_STATUS DevRWCompletionHandler(void *context, A_STATUS status)
{
HTC_PACKET *pPacket = (HTC_PACKET *)context;
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
("+DevRWCompletionHandler (Pkt:0x%lX) , Status: %d \n",
(unsigned long)pPacket,
status));
COMPLETE_HTC_PACKET(pPacket,status);
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
("-DevRWCompletionHandler\n"));
return A_OK;
}
/* mailbox recv message polling */
A_STATUS DevPollMboxMsgRecv(AR6K_DEVICE *pDev,
A_UINT32 *pLookAhead,
int TimeoutMS)
{
A_STATUS status = A_OK;
int timeout = TimeoutMS/DELAY_PER_INTERVAL_MS;
A_ASSERT(timeout > 0);
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("+DevPollMboxMsgRecv \n"));
while (TRUE) {
if (pDev->GetPendingEventsFunc != NULL) {
HIF_PENDING_EVENTS_INFO events;
#ifdef THREAD_X
events.Polling =1;
#endif
/* the HIF layer uses a special mechanism to get events, do this
* synchronously */
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
&events,
NULL);
if (A_FAILED(status))
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get pending events \n"));
break;
}
if (events.Events & HIF_RECV_MSG_AVAIL)
{
/* there is a message available, the lookahead should be valid now */
*pLookAhead = events.LookAhead;
break;
}
} else {
/* this is the standard HIF way.... */
/* load the register table */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
(A_UINT8 *)&pDev->IrqProcRegisters,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (A_FAILED(status)){
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to read register table \n"));
break;
}
/* check for MBOX data and valid lookahead */
if (pDev->IrqProcRegisters.host_int_status & (1 << HTC_MAILBOX)) {
if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX))
{
/* mailbox has a message and the look ahead is valid */
*pLookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
break;
}
}
}
timeout--;
if (timeout <= 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Timeout waiting for recv message \n"));
status = A_ERROR;
/* check if the target asserted */
if ( pDev->IrqProcRegisters.counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
/* target signaled an assert, process this pending interrupt
* this will call the target failure handler */
DevServiceDebugInterrupt(pDev);
}
break;
}
/* delay a little */
A_MDELAY(DELAY_PER_INTERVAL_MS);
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,(" Retry Mbox Poll : %d \n",timeout));
}
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,("-DevPollMboxMsgRecv \n"));
return status;
}
static A_STATUS DevServiceCPUInterrupt(AR6K_DEVICE *pDev)
{
A_STATUS status;
A_UINT8 cpu_int_status;
A_UINT8 regBuffer[4];
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("CPU Interrupt\n"));
cpu_int_status = pDev->IrqProcRegisters.cpu_int_status &
pDev->IrqEnableRegisters.cpu_int_status_enable;
A_ASSERT(cpu_int_status);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
("Valid interrupt source(s) in CPU_INT_STATUS: 0x%x\n",
cpu_int_status));
/* Clear the interrupt */
pDev->IrqProcRegisters.cpu_int_status &= ~cpu_int_status; /* W1C */
/* set up the register transfer buffer to hit the register 4 times , this is done
* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
* restrict bus transfer lengths to be a multiple of 4-bytes */
/* set W1C value to clear the interrupt, this hits the register first */
regBuffer[0] = cpu_int_status;
/* the remaining 4 values are set to zero which have no-effect */
regBuffer[1] = 0;
regBuffer[2] = 0;
regBuffer[3] = 0;
status = HIFReadWrite(pDev->HIFDevice,
CPU_INT_STATUS_ADDRESS,
regBuffer,
4,
HIF_WR_SYNC_BYTE_FIX,
NULL);
A_ASSERT(status == A_OK);
return status;
}
static A_STATUS DevServiceErrorInterrupt(AR6K_DEVICE *pDev)
{
A_STATUS status;
A_UINT8 error_int_status;
A_UINT8 regBuffer[4];
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error Interrupt\n"));
error_int_status = pDev->IrqProcRegisters.error_int_status & 0x0F;
A_ASSERT(error_int_status);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
("Valid interrupt source(s) in ERROR_INT_STATUS: 0x%x\n",
error_int_status));
if (ERROR_INT_STATUS_WAKEUP_GET(error_int_status)) {
/* Wakeup */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Error : Wakeup\n"));
}
if (ERROR_INT_STATUS_RX_UNDERFLOW_GET(error_int_status)) {
/* Rx Underflow */
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Rx Underflow\n"));
}
if (ERROR_INT_STATUS_TX_OVERFLOW_GET(error_int_status)) {
/* Tx Overflow */
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Error : Tx Overflow\n"));
}
/* Clear the interrupt */
pDev->IrqProcRegisters.error_int_status &= ~error_int_status; /* W1C */
/* set up the register transfer buffer to hit the register 4 times , this is done
* to make the access 4-byte aligned to mitigate issues with host bus interconnects that
* restrict bus transfer lengths to be a multiple of 4-bytes */
/* set W1C value to clear the interrupt, this hits the register first */
regBuffer[0] = error_int_status;
/* the remaining 4 values are set to zero which have no-effect */
regBuffer[1] = 0;
regBuffer[2] = 0;
regBuffer[3] = 0;
status = HIFReadWrite(pDev->HIFDevice,
ERROR_INT_STATUS_ADDRESS,
regBuffer,
4,
HIF_WR_SYNC_BYTE_FIX,
NULL);
A_ASSERT(status == A_OK);
return status;
}
static A_STATUS DevServiceDebugInterrupt(AR6K_DEVICE *pDev)
{
A_UINT32 dummy;
A_STATUS status;
/* Send a target failure event to the application */
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Target debug interrupt\n"));
if (pDev->TargetFailureCallback != NULL) {
pDev->TargetFailureCallback(pDev->HTCContext);
}
if (pDev->GMboxEnabled) {
DevNotifyGMboxTargetFailure(pDev);
}
/* clear the interrupt , the debug error interrupt is
* counter 0 */
/* read counter to clear interrupt */
status = HIFReadWrite(pDev->HIFDevice,
COUNT_DEC_ADDRESS,
(A_UINT8 *)&dummy,
4,
HIF_RD_SYNC_BYTE_INC,
NULL);
A_ASSERT(status == A_OK);
return status;
}
static A_STATUS DevServiceCounterInterrupt(AR6K_DEVICE *pDev)
{
A_UINT8 counter_int_status;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("Counter Interrupt\n"));
counter_int_status = pDev->IrqProcRegisters.counter_int_status &
pDev->IrqEnableRegisters.counter_int_status_enable;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
("Valid interrupt source(s) in COUNTER_INT_STATUS: 0x%x\n",
counter_int_status));
/* Check if the debug interrupt is pending
* NOTE: other modules like GMBOX may use the counter interrupt for
* credit flow control on other counters, we only need to check for the debug assertion
* counter interrupt */
if (counter_int_status & AR6K_TARGET_DEBUG_INTR_MASK) {
return DevServiceDebugInterrupt(pDev);
}
return A_OK;
}
/* callback when our fetch to get interrupt status registers completes */
static void DevGetEventAsyncHandler(void *Context, HTC_PACKET *pPacket)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
A_UINT32 lookAhead = 0;
A_BOOL otherInts = FALSE;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGetEventAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
do {
if (A_FAILED(pPacket->Status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
(" GetEvents I/O request failed, status:%d \n", pPacket->Status));
/* bail out, don't unmask HIF interrupt */
break;
}
if (pDev->GetPendingEventsFunc != NULL) {
/* the HIF layer collected the information for us */
HIF_PENDING_EVENTS_INFO *pEvents = (HIF_PENDING_EVENTS_INFO *)pPacket->pBuffer;
if (pEvents->Events & HIF_RECV_MSG_AVAIL) {
lookAhead = pEvents->LookAhead;
if (0 == lookAhead) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler1, lookAhead is zero! \n"));
}
}
if (pEvents->Events & HIF_OTHER_EVENTS) {
otherInts = TRUE;
}
} else {
/* standard interrupt table handling.... */
AR6K_IRQ_PROC_REGISTERS *pReg = (AR6K_IRQ_PROC_REGISTERS *)pPacket->pBuffer;
A_UINT8 host_int_status;
host_int_status = pReg->host_int_status & pDev->IrqEnableRegisters.int_status_enable;
if (host_int_status & (1 << HTC_MAILBOX)) {
host_int_status &= ~(1 << HTC_MAILBOX);
if (pReg->rx_lookahead_valid & (1 << HTC_MAILBOX)) {
/* mailbox has a message and the look ahead is valid */
lookAhead = pReg->rx_lookahead[HTC_MAILBOX];
if (0 == lookAhead) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" DevGetEventAsyncHandler2, lookAhead is zero! \n"));
}
}
}
if (host_int_status) {
/* there are other interrupts to handle */
otherInts = TRUE;
}
}
if (otherInts || (lookAhead == 0)) {
/* if there are other interrupts to process, we cannot do this in the async handler so
* ack the interrupt which will cause our sync handler to run again
* if however there are no more messages, we can now ack the interrupt */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
(" Acking interrupt from DevGetEventAsyncHandler (otherints:%d, lookahead:0x%X)\n",
otherInts, lookAhead));
HIFAckInterrupt(pDev->HIFDevice);
} else {
int fetched = 0;
A_STATUS status;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
(" DevGetEventAsyncHandler : detected another message, lookahead :0x%X \n",
lookAhead));
/* lookahead is non-zero and there are no other interrupts to service,
* go get the next message */
status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, NULL, &fetched);
if (A_SUCCESS(status) && !fetched) {
/* HTC layer could not pull out messages due to lack of resources, stop IRQ processing */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("MessagePendingCallback did not pull any messages, force-ack \n"));
DevAsyncIrqProcessComplete(pDev);
}
}
} while (FALSE);
/* free this IO packet */
AR6KFreeIOPacket(pDev,pPacket);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGetEventAsyncHandler \n"));
}
/* called by the HTC layer when it wants us to check if the device has any more pending
* recv messages, this starts off a series of async requests to read interrupt registers */
A_STATUS DevCheckPendingRecvMsgsAsync(void *context)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
A_STATUS status = A_OK;
HTC_PACKET *pIOPacket;
/* this is called in an ASYNC only context, we may NOT block, sleep or call any apis that can
* cause us to switch contexts */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevCheckPendingRecvMsgsAsync: (dev: 0x%lX)\n", (unsigned long)pDev));
do {
if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
/* break the async processing chain right here, no need to continue.
* The DevDsrHandler() will handle things in a loop when things are driven
* synchronously */
break;
}
/* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
* the target, if upper layers determine that we are in a low-throughput mode, we can
* rely on taking another interrupt rather than re-checking the status registers which can
* re-wake the target */
if (pDev->RecheckIRQStatusCnt == 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, re-acking HIF interrupts\n"));
/* ack interrupt */
HIFAckInterrupt(pDev->HIFDevice);
break;
}
/* first allocate one of our HTC packets we created for async I/O
* we reuse HTC packet definitions so that we can use the completion mechanism
* in DevRWCompletionHandler() */
pIOPacket = AR6KAllocIOPacket(pDev);
if (NULL == pIOPacket) {
/* there should be only 1 asynchronous request out at a time to read these registers
* so this should actually never happen */
status = A_NO_MEMORY;
A_ASSERT(FALSE);
break;
}
/* stick in our completion routine when the I/O operation completes */
pIOPacket->Completion = DevGetEventAsyncHandler;
pIOPacket->pContext = pDev;
if (pDev->GetPendingEventsFunc) {
/* HIF layer has it's own mechanism, pass the IO to it.. */
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
(HIF_PENDING_EVENTS_INFO *)pIOPacket->pBuffer,
pIOPacket);
} else {
/* standard way, read the interrupt register table asynchronously again */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
pIOPacket->pBuffer,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_ASYNC_BYTE_INC,
pIOPacket);
}
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Async IO issued to get interrupt status...\n"));
} while (FALSE);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevCheckPendingRecvMsgsAsync \n"));
return status;
}
void DevAsyncIrqProcessComplete(AR6K_DEVICE *pDev)
{
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("DevAsyncIrqProcessComplete - forcing HIF IRQ ACK \n"));
HIFAckInterrupt(pDev->HIFDevice);
}
/* process pending interrupts synchronously */
static A_STATUS ProcessPendingIRQs(AR6K_DEVICE *pDev, A_BOOL *pDone, A_BOOL *pASyncProcessing)
{
A_STATUS status = A_OK;
A_UINT8 host_int_status = 0;
A_UINT32 lookAhead = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+ProcessPendingIRQs: (dev: 0x%lX)\n", (unsigned long)pDev));
/*** NOTE: the HIF implementation guarantees that the context of this call allows
* us to perform SYNCHRONOUS I/O, that is we can block, sleep or call any API that
* can block or switch thread/task ontexts.
* This is a fully schedulable context.
* */
do {
if (pDev->IrqEnableRegisters.int_status_enable == 0) {
/* interrupt enables have been cleared, do not try to process any pending interrupts that
* may result in more bus transactions. The target may be unresponsive at this
* point. */
break;
}
if (pDev->GetPendingEventsFunc != NULL) {
HIF_PENDING_EVENTS_INFO events;
#ifdef THREAD_X
events.Polling= 0;
#endif
/* the HIF layer uses a special mechanism to get events
* get this synchronously */
status = pDev->GetPendingEventsFunc(pDev->HIFDevice,
&events,
NULL);
if (A_FAILED(status)) {
break;
}
if (events.Events & HIF_RECV_MSG_AVAIL) {
lookAhead = events.LookAhead;
if (0 == lookAhead) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs1 lookAhead is zero! \n"));
}
}
if (!(events.Events & HIF_OTHER_EVENTS) ||
!(pDev->IrqEnableRegisters.int_status_enable & OTHER_INTS_ENABLED)) {
/* no need to read the register table, no other interesting interrupts.
* Some interfaces (like SPI) can shadow interrupt sources without
* requiring the host to do a full table read */
break;
}
/* otherwise fall through and read the register table */
}
/*
* Read the first 28 bytes of the HTC register table. This will yield us
* the value of different int status registers and the lookahead
* registers.
* length = sizeof(int_status) + sizeof(cpu_int_status) +
* sizeof(error_int_status) + sizeof(counter_int_status) +
* sizeof(mbox_frame) + sizeof(rx_lookahead_valid) +
* sizeof(hole) + sizeof(rx_lookahead) +
* sizeof(int_status_enable) + sizeof(cpu_int_status_enable) +
* sizeof(error_status_enable) +
* sizeof(counter_int_status_enable);
*
*/
#ifdef CONFIG_MMC_SDHCI_S3C
pDev->IrqProcRegisters.host_int_status = 0;
pDev->IrqProcRegisters.rx_lookahead_valid = 0;
pDev->IrqProcRegisters.host_int_status2 = 0;
pDev->IrqProcRegisters.rx_lookahead[0] = 0;
pDev->IrqProcRegisters.rx_lookahead[1] = 0xaaa5555;
#endif /* CONFIG_MMC_SDHCI_S3C */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
(A_UINT8 *)&pDev->IrqProcRegisters,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (A_FAILED(status)) {
break;
}
#ifdef ATH_DEBUG_MODULE
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_IRQ)) {
DevDumpRegisters(pDev,
&pDev->IrqProcRegisters,
&pDev->IrqEnableRegisters);
}
#endif
/* Update only those registers that are enabled */
host_int_status = pDev->IrqProcRegisters.host_int_status &
pDev->IrqEnableRegisters.int_status_enable;
if (NULL == pDev->GetPendingEventsFunc) {
/* only look at mailbox status if the HIF layer did not provide this function,
* on some HIF interfaces reading the RX lookahead is not valid to do */
if (host_int_status & (1 << HTC_MAILBOX)) {
/* mask out pending mailbox value, we use "lookAhead" as the real flag for
* mailbox processing below */
host_int_status &= ~(1 << HTC_MAILBOX);
if (pDev->IrqProcRegisters.rx_lookahead_valid & (1 << HTC_MAILBOX)) {
/* mailbox has a message and the look ahead is valid */
lookAhead = pDev->IrqProcRegisters.rx_lookahead[HTC_MAILBOX];
if (0 == lookAhead) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,(" ProcessPendingIRQs2, lookAhead is zero! \n"));
}
}
}
} else {
/* not valid to check if the HIF has another mechanism for reading mailbox pending status*/
host_int_status &= ~(1 << HTC_MAILBOX);
}
if (pDev->GMboxEnabled) {
/*call GMBOX layer to process any interrupts of interest */
status = DevCheckGMboxInterrupts(pDev);
}
} while (FALSE);
do {
/* did the interrupt status fetches succeed? */
if (A_FAILED(status)) {
break;
}
if ((0 == host_int_status) && (0 == lookAhead)) {
/* nothing to process, the caller can use this to break out of a loop */
*pDone = TRUE;
break;
}
if (lookAhead != 0) {
int fetched = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Pending mailbox message, LookAhead: 0x%X\n",lookAhead));
/* Mailbox Interrupt, the HTC layer may issue async requests to empty the
* mailbox...
* When emptying the recv mailbox we use the async handler above called from the
* completion routine of the callers read request. This can improve performance
* by reducing context switching when we rapidly pull packets */
status = pDev->MessagePendingCallback(pDev->HTCContext, &lookAhead, 1, pASyncProcessing, &fetched);
if (A_FAILED(status)) {
break;
}
if (!fetched) {
/* HTC could not pull any messages out due to lack of resources */
/* force DSR handler to ack the interrupt */
*pASyncProcessing = FALSE;
pDev->RecheckIRQStatusCnt = 0;
}
}
/* now handle the rest of them */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
(" Valid interrupt source(s) for OTHER interrupts: 0x%x\n",
host_int_status));
if (HOST_INT_STATUS_CPU_GET(host_int_status)) {
/* CPU Interrupt */
status = DevServiceCPUInterrupt(pDev);
if (A_FAILED(status)){
break;
}
}
if (HOST_INT_STATUS_ERROR_GET(host_int_status)) {
/* Error Interrupt */
status = DevServiceErrorInterrupt(pDev);
if (A_FAILED(status)){
break;
}
}
if (HOST_INT_STATUS_COUNTER_GET(host_int_status)) {
/* Counter Interrupt */
status = DevServiceCounterInterrupt(pDev);
if (A_FAILED(status)){
break;
}
}
} while (FALSE);
/* an optimization to bypass reading the IRQ status registers unecessarily which can re-wake
* the target, if upper layers determine that we are in a low-throughput mode, we can
* rely on taking another interrupt rather than re-checking the status registers which can
* re-wake the target.
*
* NOTE : for host interfaces that use the special GetPendingEventsFunc, this optimization cannot
* be used due to possible side-effects. For example, SPI requires the host to drain all
* messages from the mailbox before exiting the ISR routine. */
if (!(*pASyncProcessing) && (pDev->RecheckIRQStatusCnt == 0) && (pDev->GetPendingEventsFunc == NULL)) {
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("Bypassing IRQ Status re-check, forcing done \n"));
*pDone = TRUE;
}
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-ProcessPendingIRQs: (done:%d, async:%d) status=%d \n",
*pDone, *pASyncProcessing, status));
return status;
}
/* Synchronousinterrupt handler, this handler kicks off all interrupt processing.*/
A_STATUS DevDsrHandler(void *context)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)context;
A_STATUS status = A_OK;
A_BOOL done = FALSE;
A_BOOL asyncProc = FALSE;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevDsrHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
/* reset the recv counter that tracks when we need to yield from the DSR */
pDev->CurrentDSRRecvCount = 0;
/* reset counter used to flag a re-scan of IRQ status registers on the target */
pDev->RecheckIRQStatusCnt = 0;
while (!done) {
status = ProcessPendingIRQs(pDev, &done, &asyncProc);
if (A_FAILED(status)) {
break;
}
if (HIF_DEVICE_IRQ_SYNC_ONLY == pDev->HifIRQProcessingMode) {
/* the HIF layer does not allow async IRQ processing, override the asyncProc flag */
asyncProc = FALSE;
/* this will cause us to re-enter ProcessPendingIRQ() and re-read interrupt status registers.
* this has a nice side effect of blocking us until all async read requests are completed.
* This behavior is required on some HIF implementations that do not allow ASYNC
* processing in interrupt handlers (like Windows CE) */
if (pDev->DSRCanYield && DEV_CHECK_RECV_YIELD(pDev)) {
/* ProcessPendingIRQs() pulled enough recv messages to satisfy the yield count, stop
* checking for more messages and return */
break;
}
}
if (asyncProc) {
/* the function performed some async I/O for performance, we
need to exit the ISR immediately, the check below will prevent the interrupt from being
Ack'd while we handle it asynchronously */
break;
}
}
if (A_SUCCESS(status) && !asyncProc) {
/* Ack the interrupt only if :
* 1. we did not get any errors in processing interrupts
* 2. there are no outstanding async processing requests */
if (pDev->DSRCanYield) {
/* if the DSR can yield do not ACK the interrupt, there could be more pending messages.
* The HIF layer must ACK the interrupt on behalf of HTC */
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Yield in effect (cur RX count: %d) \n", pDev->CurrentDSRRecvCount));
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,(" Acking interrupt from DevDsrHandler \n"));
HIFAckInterrupt(pDev->HIFDevice);
}
}
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevDsrHandler \n"));
return status;
}
#ifdef ATH_DEBUG_MODULE
void DumpAR6KDevState(AR6K_DEVICE *pDev)
{
A_STATUS status;
AR6K_IRQ_ENABLE_REGISTERS regs;
AR6K_IRQ_PROC_REGISTERS procRegs;
LOCK_AR6K(pDev);
/* copy into our temp area */
A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
UNLOCK_AR6K(pDev);
/* load the register table from the device */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
(A_UINT8 *)&procRegs,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DumpAR6KDevState : Failed to read register table (%d) \n",status));
return;
}
DevDumpRegisters(pDev,&procRegs,&regs);
if (pDev->GMboxInfo.pStateDumpCallback != NULL) {
pDev->GMboxInfo.pStateDumpCallback(pDev->GMboxInfo.pProtocolContext);
}
/* dump any bus state at the HIF layer */
HIFConfigureDevice(pDev->HIFDevice,HIF_DEVICE_DEBUG_BUS_STATE,NULL,0);
}
#endif

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drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c Normal file
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//------------------------------------------------------------------------------
// <copyright file="ar6k_gmbox.c" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Generic MBOX API implementation
//
// Author(s): ="Atheros"
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
#include "htc_packet.h"
#include "ar6k.h"
#include "hw/mbox_host_reg.h"
#include "gmboxif.h"
/*
* This file provides management functions and a toolbox for GMBOX protocol modules.
* Only one protocol module can be installed at a time. The determination of which protocol
* module is installed is determined at compile time.
*
*/
#ifdef ATH_AR6K_ENABLE_GMBOX
/* GMBOX definitions */
#define GMBOX_INT_STATUS_ENABLE_REG 0x488
#define GMBOX_INT_STATUS_RX_DATA (1 << 0)
#define GMBOX_INT_STATUS_TX_OVERFLOW (1 << 1)
#define GMBOX_INT_STATUS_RX_OVERFLOW (1 << 2)
#define GMBOX_LOOKAHEAD_MUX_REG 0x498
#define GMBOX_LA_MUX_OVERRIDE_2_3 (1 << 0)
#define AR6K_GMBOX_CREDIT_DEC_ADDRESS (COUNT_DEC_ADDRESS + 4 * AR6K_GMBOX_CREDIT_COUNTER)
#define AR6K_GMBOX_CREDIT_SIZE_ADDRESS (COUNT_ADDRESS + AR6K_GMBOX_CREDIT_SIZE_COUNTER)
/* external APIs for allocating and freeing internal I/O packets to handle ASYNC I/O */
extern void AR6KFreeIOPacket(AR6K_DEVICE *pDev, HTC_PACKET *pPacket);
extern HTC_PACKET *AR6KAllocIOPacket(AR6K_DEVICE *pDev);
/* callback when our fetch to enable/disable completes */
static void DevGMboxIRQActionAsyncHandler(void *Context, HTC_PACKET *pPacket)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxIRQActionAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
if (A_FAILED(pPacket->Status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("IRQAction Operation (%d) failed! status:%d \n", pPacket->PktInfo.AsRx.HTCRxFlags,pPacket->Status));
}
/* free this IO packet */
AR6KFreeIOPacket(pDev,pPacket);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxIRQActionAsyncHandler \n"));
}
static A_STATUS DevGMboxCounterEnableDisable(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
{
A_STATUS status = A_OK;
AR6K_IRQ_ENABLE_REGISTERS regs;
HTC_PACKET *pIOPacket = NULL;
LOCK_AR6K(pDev);
if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
pDev->GMboxInfo.CreditCountIRQEnabled = TRUE;
pDev->IrqEnableRegisters.counter_int_status_enable |=
COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER);
pDev->IrqEnableRegisters.int_status_enable |= INT_STATUS_ENABLE_COUNTER_SET(0x01);
} else {
pDev->GMboxInfo.CreditCountIRQEnabled = FALSE;
pDev->IrqEnableRegisters.counter_int_status_enable &=
~(COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER));
}
/* copy into our temp area */
A_MEMCPY(&regs,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
UNLOCK_AR6K(pDev);
do {
if (AsyncMode) {
pIOPacket = AR6KAllocIOPacket(pDev);
if (NULL == pIOPacket) {
status = A_NO_MEMORY;
A_ASSERT(FALSE);
break;
}
/* copy values to write to our async I/O buffer */
A_MEMCPY(pIOPacket->pBuffer,&pDev->IrqEnableRegisters,AR6K_IRQ_ENABLE_REGS_SIZE);
/* stick in our completion routine when the I/O operation completes */
pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
pIOPacket->pContext = pDev;
pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
/* write it out asynchronously */
HIFReadWrite(pDev->HIFDevice,
INT_STATUS_ENABLE_ADDRESS,
pIOPacket->pBuffer,
AR6K_IRQ_ENABLE_REGS_SIZE,
HIF_WR_ASYNC_BYTE_INC,
pIOPacket);
pIOPacket = NULL;
break;
}
/* if we get here we are doing it synchronously */
status = HIFReadWrite(pDev->HIFDevice,
INT_STATUS_ENABLE_ADDRESS,
&regs.int_status_enable,
AR6K_IRQ_ENABLE_REGS_SIZE,
HIF_WR_SYNC_BYTE_INC,
NULL);
} while (FALSE);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
(" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
} else {
if (!AsyncMode) {
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
(" IRQAction Operation (%d) success \n", IrqAction));
}
}
if (pIOPacket != NULL) {
AR6KFreeIOPacket(pDev,pIOPacket);
}
return status;
}
A_STATUS DevGMboxIRQAction(AR6K_DEVICE *pDev, GMBOX_IRQ_ACTION_TYPE IrqAction, A_BOOL AsyncMode)
{
A_STATUS status = A_OK;
HTC_PACKET *pIOPacket = NULL;
A_UINT8 GMboxIntControl[4];
if (GMBOX_CREDIT_IRQ_ENABLE == IrqAction) {
return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_ENABLE, AsyncMode);
} else if(GMBOX_CREDIT_IRQ_DISABLE == IrqAction) {
return DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
}
if (GMBOX_DISABLE_ALL == IrqAction) {
/* disable credit IRQ, those are on a different set of registers */
DevGMboxCounterEnableDisable(pDev, GMBOX_CREDIT_IRQ_DISABLE, AsyncMode);
}
/* take the lock to protect interrupt enable shadows */
LOCK_AR6K(pDev);
switch (IrqAction) {
case GMBOX_DISABLE_ALL:
pDev->GMboxControlRegisters.int_status_enable = 0;
break;
case GMBOX_ERRORS_IRQ_ENABLE:
pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_TX_OVERFLOW |
GMBOX_INT_STATUS_RX_OVERFLOW;
break;
case GMBOX_RECV_IRQ_ENABLE:
pDev->GMboxControlRegisters.int_status_enable |= GMBOX_INT_STATUS_RX_DATA;
break;
case GMBOX_RECV_IRQ_DISABLE:
pDev->GMboxControlRegisters.int_status_enable &= ~GMBOX_INT_STATUS_RX_DATA;
break;
case GMBOX_ACTION_NONE:
default:
A_ASSERT(FALSE);
break;
}
GMboxIntControl[0] = pDev->GMboxControlRegisters.int_status_enable;
GMboxIntControl[1] = GMboxIntControl[0];
GMboxIntControl[2] = GMboxIntControl[0];
GMboxIntControl[3] = GMboxIntControl[0];
UNLOCK_AR6K(pDev);
do {
if (AsyncMode) {
pIOPacket = AR6KAllocIOPacket(pDev);
if (NULL == pIOPacket) {
status = A_NO_MEMORY;
A_ASSERT(FALSE);
break;
}
/* copy values to write to our async I/O buffer */
A_MEMCPY(pIOPacket->pBuffer,GMboxIntControl,sizeof(GMboxIntControl));
/* stick in our completion routine when the I/O operation completes */
pIOPacket->Completion = DevGMboxIRQActionAsyncHandler;
pIOPacket->pContext = pDev;
pIOPacket->PktInfo.AsRx.HTCRxFlags = IrqAction;
/* write it out asynchronously */
HIFReadWrite(pDev->HIFDevice,
GMBOX_INT_STATUS_ENABLE_REG,
pIOPacket->pBuffer,
sizeof(GMboxIntControl),
HIF_WR_ASYNC_BYTE_FIX,
pIOPacket);
pIOPacket = NULL;
break;
}
/* if we get here we are doing it synchronously */
status = HIFReadWrite(pDev->HIFDevice,
GMBOX_INT_STATUS_ENABLE_REG,
GMboxIntControl,
sizeof(GMboxIntControl),
HIF_WR_SYNC_BYTE_FIX,
NULL);
} while (FALSE);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
(" IRQAction Operation (%d) failed! status:%d \n", IrqAction, status));
} else {
if (!AsyncMode) {
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,
(" IRQAction Operation (%d) success \n", IrqAction));
}
}
if (pIOPacket != NULL) {
AR6KFreeIOPacket(pDev,pIOPacket);
}
return status;
}
void DevCleanupGMbox(AR6K_DEVICE *pDev)
{
if (pDev->GMboxEnabled) {
pDev->GMboxEnabled = FALSE;
GMboxProtocolUninstall(pDev);
}
}
A_STATUS DevSetupGMbox(AR6K_DEVICE *pDev)
{
A_STATUS status = A_OK;
A_UINT8 muxControl[4];
do {
if (0 == pDev->MailBoxInfo.GMboxAddress) {
break;
}
AR_DEBUG_PRINTF(ATH_DEBUG_ANY,(" GMBOX Advertised: Address:0x%X , size:%d \n",
pDev->MailBoxInfo.GMboxAddress, pDev->MailBoxInfo.GMboxSize));
status = DevGMboxIRQAction(pDev, GMBOX_DISABLE_ALL, PROC_IO_SYNC);
if (A_FAILED(status)) {
break;
}
/* write to mailbox look ahead mux control register, we want the
* GMBOX lookaheads to appear on lookaheads 2 and 3
* the register is 1-byte wide so we need to hit it 4 times to align the operation
* to 4-bytes */
muxControl[0] = GMBOX_LA_MUX_OVERRIDE_2_3;
muxControl[1] = GMBOX_LA_MUX_OVERRIDE_2_3;
muxControl[2] = GMBOX_LA_MUX_OVERRIDE_2_3;
muxControl[3] = GMBOX_LA_MUX_OVERRIDE_2_3;
status = HIFReadWrite(pDev->HIFDevice,
GMBOX_LOOKAHEAD_MUX_REG,
muxControl,
sizeof(muxControl),
HIF_WR_SYNC_BYTE_FIX, /* hit this register 4 times */
NULL);
if (A_FAILED(status)) {
break;
}
status = GMboxProtocolInstall(pDev);
if (A_FAILED(status)) {
break;
}
pDev->GMboxEnabled = TRUE;
} while (FALSE);
return status;
}
A_STATUS DevCheckGMboxInterrupts(AR6K_DEVICE *pDev)
{
A_STATUS status = A_OK;
A_UINT8 counter_int_status;
int credits;
A_UINT8 host_int_status2;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("+DevCheckGMboxInterrupts \n"));
/* the caller guarantees that this is a context that allows for blocking I/O */
do {
host_int_status2 = pDev->IrqProcRegisters.host_int_status2 &
pDev->GMboxControlRegisters.int_status_enable;
if (host_int_status2 & GMBOX_INT_STATUS_TX_OVERFLOW) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : TX Overflow \n"));
status = A_ECOMM;
}
if (host_int_status2 & GMBOX_INT_STATUS_RX_OVERFLOW) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("GMBOX : RX Overflow \n"));
status = A_ECOMM;
}
if (A_FAILED(status)) {
if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, status);
}
break;
}
if (host_int_status2 & GMBOX_INT_STATUS_RX_DATA) {
if (pDev->IrqProcRegisters.gmbox_rx_avail > 0) {
A_ASSERT(pDev->GMboxInfo.pMessagePendingCallBack != NULL);
status = pDev->GMboxInfo.pMessagePendingCallBack(
pDev->GMboxInfo.pProtocolContext,
(A_UINT8 *)&pDev->IrqProcRegisters.rx_gmbox_lookahead_alias[0],
pDev->IrqProcRegisters.gmbox_rx_avail);
}
}
if (A_FAILED(status)) {
break;
}
counter_int_status = pDev->IrqProcRegisters.counter_int_status &
pDev->IrqEnableRegisters.counter_int_status_enable;
/* check if credit interrupt is pending */
if (counter_int_status & (COUNTER_INT_STATUS_ENABLE_BIT_SET(1 << AR6K_GMBOX_CREDIT_COUNTER))) {
/* do synchronous read */
status = DevGMboxReadCreditCounter(pDev, PROC_IO_SYNC, &credits);
if (A_FAILED(status)) {
break;
}
A_ASSERT(pDev->GMboxInfo.pCreditsPendingCallback != NULL);
status = pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
credits,
pDev->GMboxInfo.CreditCountIRQEnabled);
}
} while (FALSE);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ, ("-DevCheckGMboxInterrupts (%d) \n",status));
return status;
}
A_STATUS DevGMboxWrite(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 WriteLength)
{
A_UINT32 paddedLength;
A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
A_STATUS status;
A_UINT32 address;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_SEND_PADDED_LEN(pDev, WriteLength);
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,
("DevGMboxWrite, Padded Length: %d Mbox:0x%X (mode:%s)\n",
WriteLength,
pDev->MailBoxInfo.GMboxAddress,
sync ? "SYNC" : "ASYNC"));
/* last byte of packet has to hit the EOM marker */
address = pDev->MailBoxInfo.GMboxAddress + pDev->MailBoxInfo.GMboxSize - paddedLength;
status = HIFReadWrite(pDev->HIFDevice,
address,
pPacket->pBuffer,
paddedLength, /* the padded length */
sync ? HIF_WR_SYNC_BLOCK_INC : HIF_WR_ASYNC_BLOCK_INC,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
} else {
if (status == A_PENDING) {
status = A_OK;
}
}
return status;
}
A_STATUS DevGMboxRead(AR6K_DEVICE *pDev, HTC_PACKET *pPacket, A_UINT32 ReadLength)
{
A_UINT32 paddedLength;
A_STATUS status;
A_BOOL sync = (pPacket->Completion == NULL) ? TRUE : FALSE;
/* adjust the length to be a multiple of block size if appropriate */
paddedLength = DEV_CALC_RECV_PADDED_LEN(pDev, ReadLength);
if (paddedLength > pPacket->BufferLength) {
A_ASSERT(FALSE);
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DevGMboxRead, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
paddedLength,ReadLength,pPacket->BufferLength));
if (pPacket->Completion != NULL) {
COMPLETE_HTC_PACKET(pPacket,A_EINVAL);
return A_OK;
}
return A_EINVAL;
}
AR_DEBUG_PRINTF(ATH_DEBUG_RECV,
("DevGMboxRead (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
(unsigned long)pPacket, pPacket->PktInfo.AsRx.ExpectedHdr,
paddedLength,
pDev->MailBoxInfo.GMboxAddress,
sync ? "SYNC" : "ASYNC"));
status = HIFReadWrite(pDev->HIFDevice,
pDev->MailBoxInfo.GMboxAddress,
pPacket->pBuffer,
paddedLength,
sync ? HIF_RD_SYNC_BLOCK_FIX : HIF_RD_ASYNC_BLOCK_FIX,
sync ? NULL : pPacket); /* pass the packet as the context to the HIF request */
if (sync) {
pPacket->Status = status;
}
return status;
}
static int ProcessCreditCounterReadBuffer(A_UINT8 *pBuffer, int Length)
{
int credits = 0;
/* theory of how this works:
* We read the credit decrement register multiple times on a byte-wide basis.
* The number of times (32) aligns the I/O operation to be a multiple of 4 bytes and provides a
* reasonable chance to acquire "all" pending credits in a single I/O operation.
*
* Once we obtain the filled buffer, we can walk through it looking for credit decrement transitions.
* Each non-zero byte represents a single credit decrement (which is a credit given back to the host)
* For example if the target provides 3 credits and added 4 more during the 32-byte read operation the following
* pattern "could" appear:
*
* 0x3 0x2 0x1 0x0 0x0 0x0 0x0 0x0 0x1 0x0 0x1 0x0 0x1 0x0 0x1 0x0 ......rest zeros
* <---------> <----------------------------->
* \_ credits aleady there \_ target adding 4 more credits
*
* The total available credits would be 7, since there are 7 non-zero bytes in the buffer.
*
* */
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_RECV)) {
DebugDumpBytes(pBuffer, Length, "GMBOX Credit read buffer");
}
while (Length) {
if (*pBuffer != 0) {
credits++;
}
Length--;
pBuffer++;
}
return credits;
}
/* callback when our fetch to enable/disable completes */
static void DevGMboxReadCreditsAsyncHandler(void *Context, HTC_PACKET *pPacket)
{
AR6K_DEVICE *pDev = (AR6K_DEVICE *)Context;
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("+DevGMboxReadCreditsAsyncHandler: (dev: 0x%lX)\n", (unsigned long)pDev));
if (A_FAILED(pPacket->Status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("Read Credit Operation failed! status:%d \n", pPacket->Status));
} else {
int credits = 0;
credits = ProcessCreditCounterReadBuffer(pPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
pDev->GMboxInfo.pCreditsPendingCallback(pDev->GMboxInfo.pProtocolContext,
credits,
pDev->GMboxInfo.CreditCountIRQEnabled);
}
/* free this IO packet */
AR6KFreeIOPacket(pDev,pPacket);
AR_DEBUG_PRINTF(ATH_DEBUG_IRQ,("-DevGMboxReadCreditsAsyncHandler \n"));
}
A_STATUS DevGMboxReadCreditCounter(AR6K_DEVICE *pDev, A_BOOL AsyncMode, int *pCredits)
{
A_STATUS status = A_OK;
HTC_PACKET *pIOPacket = NULL;
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("+DevGMboxReadCreditCounter (%s) \n", AsyncMode ? "ASYNC" : "SYNC"));
do {
pIOPacket = AR6KAllocIOPacket(pDev);
if (NULL == pIOPacket) {
status = A_NO_MEMORY;
A_ASSERT(FALSE);
break;
}
A_MEMZERO(pIOPacket->pBuffer,AR6K_REG_IO_BUFFER_SIZE);
if (AsyncMode) {
/* stick in our completion routine when the I/O operation completes */
pIOPacket->Completion = DevGMboxReadCreditsAsyncHandler;
pIOPacket->pContext = pDev;
/* read registers asynchronously */
HIFReadWrite(pDev->HIFDevice,
AR6K_GMBOX_CREDIT_DEC_ADDRESS,
pIOPacket->pBuffer,
AR6K_REG_IO_BUFFER_SIZE, /* hit the register multiple times */
HIF_RD_ASYNC_BYTE_FIX,
pIOPacket);
pIOPacket = NULL;
break;
}
pIOPacket->Completion = NULL;
/* if we get here we are doing it synchronously */
status = HIFReadWrite(pDev->HIFDevice,
AR6K_GMBOX_CREDIT_DEC_ADDRESS,
pIOPacket->pBuffer,
AR6K_REG_IO_BUFFER_SIZE,
HIF_RD_SYNC_BYTE_FIX,
NULL);
} while (FALSE);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
(" DevGMboxReadCreditCounter failed! status:%d \n", status));
}
if (pIOPacket != NULL) {
if (A_SUCCESS(status)) {
/* sync mode processing */
*pCredits = ProcessCreditCounterReadBuffer(pIOPacket->pBuffer, AR6K_REG_IO_BUFFER_SIZE);
}
AR6KFreeIOPacket(pDev,pIOPacket);
}
AR_DEBUG_PRINTF(ATH_DEBUG_SEND,("-DevGMboxReadCreditCounter (%s) (%d) \n",
AsyncMode ? "ASYNC" : "SYNC", status));
return status;
}
A_STATUS DevGMboxReadCreditSize(AR6K_DEVICE *pDev, int *pCreditSize)
{
A_STATUS status;
A_UINT8 buffer[4];
status = HIFReadWrite(pDev->HIFDevice,
AR6K_GMBOX_CREDIT_SIZE_ADDRESS,
buffer,
sizeof(buffer),
HIF_RD_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
NULL);
if (A_SUCCESS(status)) {
if (buffer[0] == 0) {
*pCreditSize = 256;
} else {
*pCreditSize = buffer[0];
}
}
return status;
}
void DevNotifyGMboxTargetFailure(AR6K_DEVICE *pDev)
{
/* Target ASSERTED!!! */
if (pDev->GMboxInfo.pTargetFailureCallback != NULL) {
pDev->GMboxInfo.pTargetFailureCallback(pDev->GMboxInfo.pProtocolContext, A_HARDWARE);
}
}
A_STATUS DevGMboxRecvLookAheadPeek(AR6K_DEVICE *pDev, A_UINT8 *pLookAheadBuffer, int *pLookAheadBytes)
{
A_STATUS status = A_OK;
AR6K_IRQ_PROC_REGISTERS procRegs;
int maxCopy;
do {
/* on entry the caller provides the length of the lookahead buffer */
if (*pLookAheadBytes > sizeof(procRegs.rx_gmbox_lookahead_alias)) {
A_ASSERT(FALSE);
status = A_EINVAL;
break;
}
maxCopy = *pLookAheadBytes;
*pLookAheadBytes = 0;
/* load the register table from the device */
status = HIFReadWrite(pDev->HIFDevice,
HOST_INT_STATUS_ADDRESS,
(A_UINT8 *)&procRegs,
AR6K_IRQ_PROC_REGS_SIZE,
HIF_RD_SYNC_BYTE_INC,
NULL);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DevGMboxRecvLookAheadPeek : Failed to read register table (%d) \n",status));
break;
}
if (procRegs.gmbox_rx_avail > 0) {
int bytes = procRegs.gmbox_rx_avail > maxCopy ? maxCopy : procRegs.gmbox_rx_avail;
A_MEMCPY(pLookAheadBuffer,&procRegs.rx_gmbox_lookahead_alias[0],bytes);
*pLookAheadBytes = bytes;
}
} while (FALSE);
return status;
}
A_STATUS DevGMboxSetTargetInterrupt(AR6K_DEVICE *pDev, int Signal, int AckTimeoutMS)
{
A_STATUS status = A_OK;
int i;
A_UINT8 buffer[4];
A_MEMZERO(buffer, sizeof(buffer));
do {
if (Signal >= MBOX_SIG_HCI_BRIDGE_MAX) {
status = A_EINVAL;
break;
}
/* set the last buffer to do the actual signal trigger */
buffer[3] = (1 << Signal);
status = HIFReadWrite(pDev->HIFDevice,
INT_WLAN_ADDRESS,
buffer,
sizeof(buffer),
HIF_WR_SYNC_BYTE_FIX, /* hit the register 4 times to align the I/O */
NULL);
if (A_FAILED(status)) {
break;
}
} while (FALSE);
if (A_SUCCESS(status)) {
/* now read back the register to see if the bit cleared */
while (AckTimeoutMS) {
status = HIFReadWrite(pDev->HIFDevice,
INT_WLAN_ADDRESS,
buffer,
sizeof(buffer),
HIF_RD_SYNC_BYTE_FIX,
NULL);
if (A_FAILED(status)) {
break;
}
for (i = 0; i < sizeof(buffer); i++) {
if (buffer[i] & (1 << Signal)) {
/* bit is still set */
break;
}
}
if (i >= sizeof(buffer)) {
/* done */
break;
}
AckTimeoutMS--;
A_MDELAY(1);
}
if (0 == AckTimeoutMS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("DevGMboxSetTargetInterrupt : Ack Timed-out (sig:%d) \n",Signal));
status = A_ERROR;
}
}
return status;
}
#endif //ATH_AR6K_ENABLE_GMBOX

1280
drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c Normal file
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//------------------------------------------------------------------------------
// <copyright file="htc.c" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#include "htc_internal.h"
#ifdef ATH_DEBUG_MODULE
static ATH_DEBUG_MASK_DESCRIPTION g_HTCDebugDescription[] = {
{ ATH_DEBUG_SEND , "Send"},
{ ATH_DEBUG_RECV , "Recv"},
{ ATH_DEBUG_SYNC , "Sync"},
{ ATH_DEBUG_DUMP , "Dump Data (RX or TX)"},
{ ATH_DEBUG_IRQ , "Interrupt Processing"}
};
ATH_DEBUG_INSTANTIATE_MODULE_VAR(htc,
"htc",
"Host Target Communications",
ATH_DEBUG_MASK_DEFAULTS,
ATH_DEBUG_DESCRIPTION_COUNT(g_HTCDebugDescription),
g_HTCDebugDescription);
#endif
static void HTCReportFailure(void *Context);
static void ResetEndpointStates(HTC_TARGET *target);
void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList)
{
LOCK_HTC(target);
HTC_PACKET_ENQUEUE(pList,pPacket);
UNLOCK_HTC(target);
}
HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList)
{
HTC_PACKET *pPacket;
LOCK_HTC(target);
pPacket = HTC_PACKET_DEQUEUE(pList);
UNLOCK_HTC(target);
return pPacket;
}
/* cleanup the HTC instance */
static void HTCCleanup(HTC_TARGET *target)
{
A_INT32 i;
DevCleanup(&target->Device);
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
if (target->HTCControlBuffers[i].Buffer) {
A_FREE(target->HTCControlBuffers[i].Buffer);
}
}
if (A_IS_MUTEX_VALID(&target->HTCLock)) {
A_MUTEX_DELETE(&target->HTCLock);
}
if (A_IS_MUTEX_VALID(&target->HTCRxLock)) {
A_MUTEX_DELETE(&target->HTCRxLock);
}
if (A_IS_MUTEX_VALID(&target->HTCTxLock)) {
A_MUTEX_DELETE(&target->HTCTxLock);
}
/* free our instance */
A_FREE(target);
}
/* registered target arrival callback from the HIF layer */
HTC_HANDLE HTCCreate(void *hif_handle, HTC_INIT_INFO *pInfo)
{
HTC_TARGET *target = NULL;
A_STATUS status = A_OK;
int i;
A_UINT32 ctrl_bufsz;
A_UINT32 blocksizes[HTC_MAILBOX_NUM_MAX];
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Enter\n"));
A_REGISTER_MODULE_DEBUG_INFO(htc);
do {
/* allocate target memory */
if ((target = (HTC_TARGET *)A_MALLOC(sizeof(HTC_TARGET))) == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
status = A_ERROR;
break;
}
A_MEMZERO(target, sizeof(HTC_TARGET));
A_MUTEX_INIT(&target->HTCLock);
A_MUTEX_INIT(&target->HTCRxLock);
A_MUTEX_INIT(&target->HTCTxLock);
INIT_HTC_PACKET_QUEUE(&target->ControlBufferTXFreeList);
INIT_HTC_PACKET_QUEUE(&target->ControlBufferRXFreeList);
/* give device layer the hif device handle */
target->Device.HIFDevice = hif_handle;
/* give the device layer our context (for event processing)
* the device layer will register it's own context with HIF
* so we need to set this so we can fetch it in the target remove handler */
target->Device.HTCContext = target;
/* set device layer target failure callback */
target->Device.TargetFailureCallback = HTCReportFailure;
/* set device layer recv message pending callback */
target->Device.MessagePendingCallback = HTCRecvMessagePendingHandler;
target->EpWaitingForBuffers = ENDPOINT_MAX;
A_MEMCPY(&target->HTCInitInfo,pInfo,sizeof(HTC_INIT_INFO));
ResetEndpointStates(target);
/* setup device layer */
status = DevSetup(&target->Device);
if (A_FAILED(status)) {
break;
}
/* get the block sizes */
status = HIFConfigureDevice(hif_handle, HIF_DEVICE_GET_MBOX_BLOCK_SIZE,
blocksizes, sizeof(blocksizes));
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Failed to get block size info from HIF layer...\n"));
break;
}
/* Set the control buffer size based on the block size */
if (blocksizes[1] > HTC_MAX_CONTROL_MESSAGE_LENGTH) {
ctrl_bufsz = blocksizes[1] + HTC_HDR_LENGTH;
} else {
ctrl_bufsz = HTC_MAX_CONTROL_MESSAGE_LENGTH + HTC_HDR_LENGTH;
}
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
target->HTCControlBuffers[i].Buffer = A_MALLOC(ctrl_bufsz);
if (target->HTCControlBuffers[i].Buffer == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unable to allocate memory\n"));
status = A_ERROR;
break;
}
}
if (A_FAILED(status)) {
break;
}
/* carve up buffers/packets for control messages */
for (i = 0; i < NUM_CONTROL_RX_BUFFERS; i++) {
HTC_PACKET *pControlPacket;
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
SET_HTC_PACKET_INFO_RX_REFILL(pControlPacket,
target,
target->HTCControlBuffers[i].Buffer,
ctrl_bufsz,
ENDPOINT_0);
HTC_FREE_CONTROL_RX(target,pControlPacket);
}
for (;i < NUM_CONTROL_BUFFERS;i++) {
HTC_PACKET *pControlPacket;
pControlPacket = &target->HTCControlBuffers[i].HtcPacket;
INIT_HTC_PACKET_INFO(pControlPacket,
target->HTCControlBuffers[i].Buffer,
ctrl_bufsz);
HTC_FREE_CONTROL_TX(target,pControlPacket);
}
} while (FALSE);
if (A_FAILED(status)) {
if (target != NULL) {
HTCCleanup(target);
target = NULL;
}
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCCreate - Exit\n"));
return target;
}
void HTCDestroy(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCDestroy .. Destroying :0x%lX \n",(unsigned long)target));
HTCCleanup(target);
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCDestroy \n"));
}
/* get the low level HIF device for the caller , the caller may wish to do low level
* HIF requests */
void *HTCGetHifDevice(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
return target->Device.HIFDevice;
}
/* wait for the target to arrive (sends HTC Ready message)
* this operation is fully synchronous and the message is polled for */
A_STATUS HTCWaitTarget(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
A_STATUS status;
HTC_PACKET *pPacket = NULL;
HTC_READY_EX_MSG *pRdyMsg;
HTC_SERVICE_CONNECT_REQ connect;
HTC_SERVICE_CONNECT_RESP resp;
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Enter (target:0x%lX) \n", (unsigned long)target));
do {
#ifdef MBOXHW_UNIT_TEST
status = DoMboxHWTest(&target->Device);
if (status != A_OK) {
break;
}
#endif
/* we should be getting 1 control message that the target is ready */
status = HTCWaitforControlMessage(target, &pPacket);
if (A_FAILED(status)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, (" Target Not Available!!\n"));
break;
}
/* we controlled the buffer creation so it has to be properly aligned */
pRdyMsg = (HTC_READY_EX_MSG *)pPacket->pBuffer;
if ((pRdyMsg->Version2_0_Info.MessageID != HTC_MSG_READY_ID) ||
(pPacket->ActualLength < sizeof(HTC_READY_MSG))) {
/* this message is not valid */
AR_DEBUG_ASSERT(FALSE);
status = A_EPROTO;
break;
}
if (pRdyMsg->Version2_0_Info.CreditCount == 0 || pRdyMsg->Version2_0_Info.CreditSize == 0) {
/* this message is not valid */
AR_DEBUG_ASSERT(FALSE);
status = A_EPROTO;
break;
}
target->TargetCredits = pRdyMsg->Version2_0_Info.CreditCount;
target->TargetCreditSize = pRdyMsg->Version2_0_Info.CreditSize;
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, (" Target Ready: credits: %d credit size: %d\n",
target->TargetCredits, target->TargetCreditSize));
/* check if this is an extended ready message */
if (pPacket->ActualLength >= sizeof(HTC_READY_EX_MSG)) {
/* this is an extended message */
target->HTCTargetVersion = pRdyMsg->HTCVersion;
target->MaxMsgPerBundle = pRdyMsg->MaxMsgsPerHTCBundle;
} else {
/* legacy */
target->HTCTargetVersion = HTC_VERSION_2P0;
target->MaxMsgPerBundle = 0;
}
#ifdef HTC_FORCE_LEGACY_2P0
/* for testing and comparison...*/
target->HTCTargetVersion = HTC_VERSION_2P0;
target->MaxMsgPerBundle = 0;
#endif
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
("Using HTC Protocol Version : %s (%d)\n ",
(target->HTCTargetVersion == HTC_VERSION_2P0) ? "2.0" : ">= 2.1",
target->HTCTargetVersion));
if (target->MaxMsgPerBundle > 0) {
/* limit what HTC can handle */
target->MaxMsgPerBundle = min(HTC_HOST_MAX_MSG_PER_BUNDLE, target->MaxMsgPerBundle);
/* target supports message bundling, setup device layer */
if (A_FAILED(DevSetupMsgBundling(&target->Device,target->MaxMsgPerBundle))) {
/* device layer can't handle bundling */
target->MaxMsgPerBundle = 0;
} else {
/* limit bundle what the device layer can handle */
target->MaxMsgPerBundle = min(DEV_GET_MAX_MSG_PER_BUNDLE(&target->Device),
target->MaxMsgPerBundle);
}
}
if (target->MaxMsgPerBundle > 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_TRC,
(" HTC bundling allowed. Max Msg Per HTC Bundle: %d\n", target->MaxMsgPerBundle));
if (DEV_GET_MAX_BUNDLE_SEND_LENGTH(&target->Device) != 0) {
target->SendBundlingEnabled = TRUE;
}
if (DEV_GET_MAX_BUNDLE_RECV_LENGTH(&target->Device) != 0) {
target->RecvBundlingEnabled = TRUE;
}
if (!DEV_IS_LEN_BLOCK_ALIGNED(&target->Device,target->TargetCreditSize)) {
AR_DEBUG_PRINTF(ATH_DEBUG_WARN, ("*** Credit size: %d is not block aligned! Disabling send bundling \n",
target->TargetCreditSize));
/* disallow send bundling since the credit size is not aligned to a block size
* the I/O block padding will spill into the next credit buffer which is fatal */
target->SendBundlingEnabled = FALSE;
}
}
/* setup our pseudo HTC control endpoint connection */
A_MEMZERO(&connect,sizeof(connect));
A_MEMZERO(&resp,sizeof(resp));
connect.EpCallbacks.pContext = target;
connect.EpCallbacks.EpTxComplete = HTCControlTxComplete;
connect.EpCallbacks.EpRecv = HTCControlRecv;
connect.EpCallbacks.EpRecvRefill = NULL; /* not needed */
connect.EpCallbacks.EpSendFull = NULL; /* not nedded */
connect.MaxSendQueueDepth = NUM_CONTROL_BUFFERS;
connect.ServiceID = HTC_CTRL_RSVD_SVC;
/* connect fake service */
status = HTCConnectService((HTC_HANDLE)target,
&connect,
&resp);
if (!A_FAILED(status)) {
break;
}
} while (FALSE);
if (pPacket != NULL) {
HTC_FREE_CONTROL_RX(target,pPacket);
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCWaitTarget - Exit\n"));
return status;
}
/* Start HTC, enable interrupts and let the target know host has finished setup */
A_STATUS HTCStart(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
HTC_PACKET *pPacket;
A_STATUS status;
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Enter\n"));
/* make sure interrupts are disabled at the chip level,
* this function can be called again from a reboot of the target without shutting down HTC */
DevDisableInterrupts(&target->Device);
/* make sure state is cleared again */
target->OpStateFlags = 0;
target->RecvStateFlags = 0;
/* now that we are starting, push control receive buffers into the
* HTC control endpoint */
while (1) {
pPacket = HTC_ALLOC_CONTROL_RX(target);
if (NULL == pPacket) {
break;
}
HTCAddReceivePkt((HTC_HANDLE)target,pPacket);
}
do {
AR_DEBUG_ASSERT(target->InitCredits != NULL);
AR_DEBUG_ASSERT(target->EpCreditDistributionListHead != NULL);
AR_DEBUG_ASSERT(target->EpCreditDistributionListHead->pNext != NULL);
/* call init credits callback to do the distribution ,
* NOTE: the first entry in the distribution list is ENDPOINT_0, so
* we pass the start of the list after this one. */
target->InitCredits(target->pCredDistContext,
target->EpCreditDistributionListHead->pNext,
target->TargetCredits);
#ifdef ATH_DEBUG_MODULE
if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_TRC)) {
DumpCreditDistStates(target);
}
#endif
/* the caller is done connecting to services, so we can indicate to the
* target that the setup phase is complete */
status = HTCSendSetupComplete(target);
if (A_FAILED(status)) {
break;
}
/* unmask interrupts */
status = DevUnmaskInterrupts(&target->Device);
if (A_FAILED(status)) {
HTCStop(target);
}
} while (FALSE);
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("HTCStart Exit\n"));
return status;
}
static void ResetEndpointStates(HTC_TARGET *target)
{
HTC_ENDPOINT *pEndpoint;
int i;
for (i = ENDPOINT_0; i < ENDPOINT_MAX; i++) {
pEndpoint = &target->EndPoint[i];
A_MEMZERO(&pEndpoint->CreditDist, sizeof(pEndpoint->CreditDist));
pEndpoint->ServiceID = 0;
pEndpoint->MaxMsgLength = 0;
pEndpoint->MaxTxQueueDepth = 0;
#ifdef HTC_EP_STAT_PROFILING
A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
#endif
INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
pEndpoint->target = target;
}
/* reset distribution list */
target->EpCreditDistributionListHead = NULL;
}
/* stop HTC communications, i.e. stop interrupt reception, and flush all queued buffers */
void HTCStop(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCStop \n"));
LOCK_HTC(target);
/* mark that we are shutting down .. */
target->OpStateFlags |= HTC_OP_STATE_STOPPING;
UNLOCK_HTC(target);
/* Masking interrupts is a synchronous operation, when this function returns
* all pending HIF I/O has completed, we can safely flush the queues */
DevMaskInterrupts(&target->Device);
#ifdef THREAD_X
//
// Is this delay required
//
A_MDELAY(200); // wait for IRQ process done
#endif
/* flush all send packets */
HTCFlushSendPkts(target);
/* flush all recv buffers */
HTCFlushRecvBuffers(target);
ResetEndpointStates(target);
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCStop \n"));
}
#ifdef ATH_DEBUG_MODULE
void HTCDumpCreditStates(HTC_HANDLE HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
LOCK_HTC_TX(target);
DumpCreditDistStates(target);
UNLOCK_HTC_TX(target);
DumpAR6KDevState(&target->Device);
}
#endif
/* report a target failure from the device, this is a callback from the device layer
* which uses a mechanism to report errors from the target (i.e. special interrupts) */
static void HTCReportFailure(void *Context)
{
HTC_TARGET *target = (HTC_TARGET *)Context;
target->TargetFailure = TRUE;
if (target->HTCInitInfo.TargetFailure != NULL) {
/* let upper layer know, it needs to call HTCStop() */
target->HTCInitInfo.TargetFailure(target->HTCInitInfo.pContext, A_ERROR);
}
}
A_BOOL HTCGetEndpointStatistics(HTC_HANDLE HTCHandle,
HTC_ENDPOINT_ID Endpoint,
HTC_ENDPOINT_STAT_ACTION Action,
HTC_ENDPOINT_STATS *pStats)
{
#ifdef HTC_EP_STAT_PROFILING
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
A_BOOL clearStats = FALSE;
A_BOOL sample = FALSE;
switch (Action) {
case HTC_EP_STAT_SAMPLE :
sample = TRUE;
break;
case HTC_EP_STAT_SAMPLE_AND_CLEAR :
sample = TRUE;
clearStats = TRUE;
break;
case HTC_EP_STAT_CLEAR :
clearStats = TRUE;
break;
default:
break;
}
A_ASSERT(Endpoint < ENDPOINT_MAX);
/* lock out TX and RX while we sample and/or clear */
LOCK_HTC_TX(target);
LOCK_HTC_RX(target);
if (sample) {
A_ASSERT(pStats != NULL);
/* return the stats to the caller */
A_MEMCPY(pStats, &target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
}
if (clearStats) {
/* reset stats */
A_MEMZERO(&target->EndPoint[Endpoint].EndPointStats, sizeof(HTC_ENDPOINT_STATS));
}
UNLOCK_HTC_RX(target);
UNLOCK_HTC_TX(target);
return TRUE;
#else
return FALSE;
#endif
}
AR6K_DEVICE *HTCGetAR6KDevice(void *HTCHandle)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
return &target->Device;
}

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//------------------------------------------------------------------------------
// <copyright file="htc_debug.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef HTC_DEBUG_H_
#define HTC_DEBUG_H_
#define ATH_MODULE_NAME htc
#include "a_debug.h"
/* ------- Debug related stuff ------- */
#define ATH_DEBUG_SEND ATH_DEBUG_MAKE_MODULE_MASK(0)
#define ATH_DEBUG_RECV ATH_DEBUG_MAKE_MODULE_MASK(1)
#define ATH_DEBUG_SYNC ATH_DEBUG_MAKE_MODULE_MASK(2)
#define ATH_DEBUG_DUMP ATH_DEBUG_MAKE_MODULE_MASK(3)
#define ATH_DEBUG_IRQ ATH_DEBUG_MAKE_MODULE_MASK(4)
#endif /*HTC_DEBUG_H_*/

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//------------------------------------------------------------------------------
// <copyright file="htc_internal.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _HTC_INTERNAL_H_
#define _HTC_INTERNAL_H_
/* for debugging, uncomment this to capture the last frame header, on frame header
* processing errors, the last frame header is dump for comparison */
//#define HTC_CAPTURE_LAST_FRAME
//#define HTC_EP_STAT_PROFILING
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Header files */
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "a_osapi.h"
#include "htc_debug.h"
#include "htc.h"
#include "htc_api.h"
#include "bmi_msg.h"
#include "hif.h"
#include "AR6000/ar6k.h"
/* HTC operational parameters */
#define HTC_TARGET_RESPONSE_TIMEOUT 2000 /* in ms */
#define HTC_TARGET_DEBUG_INTR_MASK 0x01
#define HTC_TARGET_CREDIT_INTR_MASK 0xF0
#define HTC_HOST_MAX_MSG_PER_BUNDLE 8
#define HTC_MIN_HTC_MSGS_TO_BUNDLE 2
/* packet flags */
#define HTC_RX_PKT_IGNORE_LOOKAHEAD (1 << 0)
#define HTC_RX_PKT_REFRESH_HDR (1 << 1)
#define HTC_RX_PKT_PART_OF_BUNDLE (1 << 2)
#define HTC_RX_PKT_NO_RECYCLE (1 << 3)
/* scatter request flags */
#define HTC_SCATTER_REQ_FLAGS_PARTIAL_BUNDLE (1 << 0)
typedef struct _HTC_ENDPOINT {
HTC_ENDPOINT_ID Id;
HTC_SERVICE_ID ServiceID; /* service ID this endpoint is bound to
non-zero value means this endpoint is in use */
HTC_PACKET_QUEUE TxQueue; /* HTC frame buffer TX queue */
HTC_PACKET_QUEUE RxBuffers; /* HTC frame buffer RX list */
HTC_ENDPOINT_CREDIT_DIST CreditDist; /* credit distribution structure (exposed to driver layer) */
HTC_EP_CALLBACKS EpCallBacks; /* callbacks associated with this endpoint */
int MaxTxQueueDepth; /* max depth of the TX queue before we need to
call driver's full handler */
int MaxMsgLength; /* max length of endpoint message */
int TxProcessCount; /* reference count to continue tx processing */
HTC_PACKET_QUEUE RecvIndicationQueue; /* recv packets ready to be indicated */
int RxProcessCount; /* reference count to allow single processing context */
struct _HTC_TARGET *target; /* back pointer to target */
A_UINT8 SeqNo; /* TX seq no (helpful) for debugging */
A_UINT32 LocalConnectionFlags; /* local connection flags */
#ifdef HTC_EP_STAT_PROFILING
HTC_ENDPOINT_STATS EndPointStats; /* endpoint statistics */
#endif
} HTC_ENDPOINT;
#ifdef HTC_EP_STAT_PROFILING
#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
#else
#define INC_HTC_EP_STAT(p,stat,count)
#endif
#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
#define NUM_CONTROL_BUFFERS 8
#define NUM_CONTROL_TX_BUFFERS 2
#define NUM_CONTROL_RX_BUFFERS (NUM_CONTROL_BUFFERS - NUM_CONTROL_TX_BUFFERS)
typedef struct HTC_CONTROL_BUFFER {
HTC_PACKET HtcPacket;
A_UINT8 *Buffer;
} HTC_CONTROL_BUFFER;
#define HTC_RECV_WAIT_BUFFERS (1 << 0)
#define HTC_OP_STATE_STOPPING (1 << 0)
/* our HTC target state */
typedef struct _HTC_TARGET {
HTC_ENDPOINT EndPoint[ENDPOINT_MAX];
HTC_CONTROL_BUFFER HTCControlBuffers[NUM_CONTROL_BUFFERS];
HTC_ENDPOINT_CREDIT_DIST *EpCreditDistributionListHead;
HTC_PACKET_QUEUE ControlBufferTXFreeList;
HTC_PACKET_QUEUE ControlBufferRXFreeList;
HTC_CREDIT_DIST_CALLBACK DistributeCredits;
HTC_CREDIT_INIT_CALLBACK InitCredits;
void *pCredDistContext;
int TargetCredits;
unsigned int TargetCreditSize;
A_MUTEX_T HTCLock;
A_MUTEX_T HTCRxLock;
A_MUTEX_T HTCTxLock;
AR6K_DEVICE Device; /* AR6K - specific state */
A_UINT32 OpStateFlags;
A_UINT32 RecvStateFlags;
HTC_ENDPOINT_ID EpWaitingForBuffers;
A_BOOL TargetFailure;
#ifdef HTC_CAPTURE_LAST_FRAME
HTC_FRAME_HDR LastFrameHdr; /* useful for debugging */
A_UINT8 LastTrailer[256];
A_UINT8 LastTrailerLength;
#endif
HTC_INIT_INFO HTCInitInfo;
A_UINT8 HTCTargetVersion;
int MaxMsgPerBundle; /* max messages per bundle for HTC */
A_BOOL SendBundlingEnabled; /* run time enable for send bundling (dynamic) */
int RecvBundlingEnabled; /* run time enable for recv bundling (dynamic) */
} HTC_TARGET;
#define HTC_STOPPING(t) ((t)->OpStateFlags & HTC_OP_STATE_STOPPING)
#define LOCK_HTC(t) A_MUTEX_LOCK(&(t)->HTCLock);
#define UNLOCK_HTC(t) A_MUTEX_UNLOCK(&(t)->HTCLock);
#define LOCK_HTC_RX(t) A_MUTEX_LOCK(&(t)->HTCRxLock);
#define UNLOCK_HTC_RX(t) A_MUTEX_UNLOCK(&(t)->HTCRxLock);
#define LOCK_HTC_TX(t) A_MUTEX_LOCK(&(t)->HTCTxLock);
#define UNLOCK_HTC_TX(t) A_MUTEX_UNLOCK(&(t)->HTCTxLock);
#define GET_HTC_TARGET_FROM_HANDLE(hnd) ((HTC_TARGET *)(hnd))
#define HTC_RECYCLE_RX_PKT(target,p,e) \
{ \
if ((p)->PktInfo.AsRx.HTCRxFlags & HTC_RX_PKT_NO_RECYCLE) { \
HTC_PACKET_RESET_RX(pPacket); \
pPacket->Status = A_ECANCELED; \
(e)->EpCallBacks.EpRecv((e)->EpCallBacks.pContext, \
(p)); \
} else { \
HTC_PACKET_RESET_RX(pPacket); \
HTCAddReceivePkt((HTC_HANDLE)(target),(p)); \
} \
}
/* internal HTC functions */
void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket);
void HTCControlRecv(void *Context, HTC_PACKET *pPacket);
A_STATUS HTCWaitforControlMessage(HTC_TARGET *target, HTC_PACKET **ppControlPacket);
HTC_PACKET *HTCAllocControlBuffer(HTC_TARGET *target, HTC_PACKET_QUEUE *pList);
void HTCFreeControlBuffer(HTC_TARGET *target, HTC_PACKET *pPacket, HTC_PACKET_QUEUE *pList);
A_STATUS HTCIssueSend(HTC_TARGET *target, HTC_PACKET *pPacket);
void HTCRecvCompleteHandler(void *Context, HTC_PACKET *pPacket);
A_STATUS HTCRecvMessagePendingHandler(void *Context, A_UINT32 MsgLookAheads[], int NumLookAheads, A_BOOL *pAsyncProc, int *pNumPktsFetched);
void HTCProcessCreditRpt(HTC_TARGET *target, HTC_CREDIT_REPORT *pRpt, int NumEntries, HTC_ENDPOINT_ID FromEndpoint);
A_STATUS HTCSendSetupComplete(HTC_TARGET *target);
void HTCFlushRecvBuffers(HTC_TARGET *target);
void HTCFlushSendPkts(HTC_TARGET *target);
#ifdef ATH_DEBUG_MODULE
void DumpCreditDist(HTC_ENDPOINT_CREDIT_DIST *pEPDist);
void DumpCreditDistStates(HTC_TARGET *target);
void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
#endif
static INLINE HTC_PACKET *HTC_ALLOC_CONTROL_TX(HTC_TARGET *target) {
HTC_PACKET *pPacket = HTCAllocControlBuffer(target,&target->ControlBufferTXFreeList);
if (pPacket != NULL) {
/* set payload pointer area with some headroom */
pPacket->pBuffer = pPacket->pBufferStart + HTC_HDR_LENGTH;
}
return pPacket;
}
#define HTC_FREE_CONTROL_TX(t,p) HTCFreeControlBuffer((t),(p),&(t)->ControlBufferTXFreeList)
#define HTC_ALLOC_CONTROL_RX(t) HTCAllocControlBuffer((t),&(t)->ControlBufferRXFreeList)
#define HTC_FREE_CONTROL_RX(t,p) \
{ \
HTC_PACKET_RESET_RX(p); \
HTCFreeControlBuffer((t),(p),&(t)->ControlBufferRXFreeList); \
}
#define HTC_PREPARE_SEND_PKT(pP,sendflags,ctrl0,ctrl1) \
{ \
A_UINT8 *pHdrBuf; \
(pP)->pBuffer -= HTC_HDR_LENGTH; \
pHdrBuf = (pP)->pBuffer; \
A_SET_UINT16_FIELD(pHdrBuf,HTC_FRAME_HDR,PayloadLen,(A_UINT16)(pP)->ActualLength); \
A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,Flags,(sendflags)); \
A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,EndpointID, (A_UINT8)(pP)->Endpoint); \
A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[0], (A_UINT8)(ctrl0)); \
A_SET_UINT8_FIELD(pHdrBuf,HTC_FRAME_HDR,ControlBytes[1], (A_UINT8)(ctrl1)); \
}
#define HTC_UNPREPARE_SEND_PKT(pP) \
(pP)->pBuffer += HTC_HDR_LENGTH; \
#ifdef __cplusplus
}
#endif
#endif /* _HTC_INTERNAL_H_ */

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//------------------------------------------------------------------------------
// <copyright file="htc_services.c" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#include "htc_internal.h"
void HTCControlTxComplete(void *Context, HTC_PACKET *pPacket)
{
/* not implemented
* we do not send control TX frames during normal runtime, only during setup */
AR_DEBUG_ASSERT(FALSE);
}
/* callback when a control message arrives on this endpoint */
void HTCControlRecv(void *Context, HTC_PACKET *pPacket)
{
AR_DEBUG_ASSERT(pPacket->Endpoint == ENDPOINT_0);
if (pPacket->Status == A_ECANCELED) {
/* this is a flush operation, return the control packet back to the pool */
HTC_FREE_CONTROL_RX((HTC_TARGET*)Context,pPacket);
return;
}
/* the only control messages we are expecting are NULL messages (credit resports) */
if (pPacket->ActualLength > 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("HTCControlRecv, got message with length:%d \n",
pPacket->ActualLength + (A_UINT32)HTC_HDR_LENGTH));
#ifdef ATH_DEBUG_MODULE
/* dump header and message */
DebugDumpBytes(pPacket->pBuffer - HTC_HDR_LENGTH,
pPacket->ActualLength + HTC_HDR_LENGTH,
"Unexpected ENDPOINT 0 Message");
#endif
}
HTC_RECYCLE_RX_PKT((HTC_TARGET*)Context,pPacket,&((HTC_TARGET*)Context)->EndPoint[0]);
}
A_STATUS HTCSendSetupComplete(HTC_TARGET *target)
{
HTC_PACKET *pSendPacket = NULL;
A_STATUS status;
do {
/* allocate a packet to send to the target */
pSendPacket = HTC_ALLOC_CONTROL_TX(target);
if (NULL == pSendPacket) {
status = A_NO_MEMORY;
break;
}
if (target->HTCTargetVersion >= HTC_VERSION_2P1) {
HTC_SETUP_COMPLETE_EX_MSG *pSetupCompleteEx;
A_UINT32 setupFlags = 0;
pSetupCompleteEx = (HTC_SETUP_COMPLETE_EX_MSG *)pSendPacket->pBuffer;
A_MEMZERO(pSetupCompleteEx, sizeof(HTC_SETUP_COMPLETE_EX_MSG));
pSetupCompleteEx->MessageID = HTC_MSG_SETUP_COMPLETE_EX_ID;
if (target->MaxMsgPerBundle > 0) {
/* host can do HTC bundling, indicate this to the target */
setupFlags |= HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV;
pSetupCompleteEx->MaxMsgsPerBundledRecv = target->MaxMsgPerBundle;
}
A_MEMCPY(&pSetupCompleteEx->SetupFlags, &setupFlags, sizeof(pSetupCompleteEx->SetupFlags));
SET_HTC_PACKET_INFO_TX(pSendPacket,
NULL,
(A_UINT8 *)pSetupCompleteEx,
sizeof(HTC_SETUP_COMPLETE_EX_MSG),
ENDPOINT_0,
HTC_SERVICE_TX_PACKET_TAG);
} else {
HTC_SETUP_COMPLETE_MSG *pSetupComplete;
/* assemble setup complete message */
pSetupComplete = (HTC_SETUP_COMPLETE_MSG *)pSendPacket->pBuffer;
A_MEMZERO(pSetupComplete, sizeof(HTC_SETUP_COMPLETE_MSG));
pSetupComplete->MessageID = HTC_MSG_SETUP_COMPLETE_ID;
SET_HTC_PACKET_INFO_TX(pSendPacket,
NULL,
(A_UINT8 *)pSetupComplete,
sizeof(HTC_SETUP_COMPLETE_MSG),
ENDPOINT_0,
HTC_SERVICE_TX_PACKET_TAG);
}
/* we want synchronous operation */
pSendPacket->Completion = NULL;
HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
/* send the message */
status = HTCIssueSend(target,pSendPacket);
} while (FALSE);
if (pSendPacket != NULL) {
HTC_FREE_CONTROL_TX(target,pSendPacket);
}
return status;
}
A_STATUS HTCConnectService(HTC_HANDLE HTCHandle,
HTC_SERVICE_CONNECT_REQ *pConnectReq,
HTC_SERVICE_CONNECT_RESP *pConnectResp)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
A_STATUS status = A_OK;
HTC_PACKET *pRecvPacket = NULL;
HTC_PACKET *pSendPacket = NULL;
HTC_CONNECT_SERVICE_RESPONSE_MSG *pResponseMsg;
HTC_CONNECT_SERVICE_MSG *pConnectMsg;
HTC_ENDPOINT_ID assignedEndpoint = ENDPOINT_MAX;
HTC_ENDPOINT *pEndpoint;
unsigned int maxMsgSize = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("+HTCConnectService, target:0x%lX SvcID:0x%X \n",
(unsigned long)target, pConnectReq->ServiceID));
do {
AR_DEBUG_ASSERT(pConnectReq->ServiceID != 0);
if (HTC_CTRL_RSVD_SVC == pConnectReq->ServiceID) {
/* special case for pseudo control service */
assignedEndpoint = ENDPOINT_0;
maxMsgSize = HTC_MAX_CONTROL_MESSAGE_LENGTH;
} else {
/* allocate a packet to send to the target */
pSendPacket = HTC_ALLOC_CONTROL_TX(target);
if (NULL == pSendPacket) {
AR_DEBUG_ASSERT(FALSE);
status = A_NO_MEMORY;
break;
}
/* assemble connect service message */
pConnectMsg = (HTC_CONNECT_SERVICE_MSG *)pSendPacket->pBuffer;
AR_DEBUG_ASSERT(pConnectMsg != NULL);
A_MEMZERO(pConnectMsg,sizeof(HTC_CONNECT_SERVICE_MSG));
pConnectMsg->MessageID = HTC_MSG_CONNECT_SERVICE_ID;
pConnectMsg->ServiceID = pConnectReq->ServiceID;
pConnectMsg->ConnectionFlags = pConnectReq->ConnectionFlags;
/* check caller if it wants to transfer meta data */
if ((pConnectReq->pMetaData != NULL) &&
(pConnectReq->MetaDataLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
/* copy meta data into message buffer (after header ) */
A_MEMCPY((A_UINT8 *)pConnectMsg + sizeof(HTC_CONNECT_SERVICE_MSG),
pConnectReq->pMetaData,
pConnectReq->MetaDataLength);
pConnectMsg->ServiceMetaLength = pConnectReq->MetaDataLength;
}
SET_HTC_PACKET_INFO_TX(pSendPacket,
NULL,
(A_UINT8 *)pConnectMsg,
sizeof(HTC_CONNECT_SERVICE_MSG) + pConnectMsg->ServiceMetaLength,
ENDPOINT_0,
HTC_SERVICE_TX_PACKET_TAG);
/* we want synchronous operation */
pSendPacket->Completion = NULL;
HTC_PREPARE_SEND_PKT(pSendPacket,0,0,0);
status = HTCIssueSend(target,pSendPacket);
if (A_FAILED(status)) {
break;
}
/* wait for response */
status = HTCWaitforControlMessage(target, &pRecvPacket);
if (A_FAILED(status)) {
break;
}
/* we controlled the buffer creation so it has to be properly aligned */
pResponseMsg = (HTC_CONNECT_SERVICE_RESPONSE_MSG *)pRecvPacket->pBuffer;
if ((pResponseMsg->MessageID != HTC_MSG_CONNECT_SERVICE_RESPONSE_ID) ||
(pRecvPacket->ActualLength < sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG))) {
/* this message is not valid */
AR_DEBUG_ASSERT(FALSE);
status = A_EPROTO;
break;
}
pConnectResp->ConnectRespCode = pResponseMsg->Status;
/* check response status */
if (pResponseMsg->Status != HTC_SERVICE_SUCCESS) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
(" Target failed service 0x%X connect request (status:%d)\n",
pResponseMsg->ServiceID, pResponseMsg->Status));
status = A_EPROTO;
break;
}
assignedEndpoint = (HTC_ENDPOINT_ID) pResponseMsg->EndpointID;
maxMsgSize = pResponseMsg->MaxMsgSize;
if ((pConnectResp->pMetaData != NULL) &&
(pResponseMsg->ServiceMetaLength > 0) &&
(pResponseMsg->ServiceMetaLength <= HTC_SERVICE_META_DATA_MAX_LENGTH)) {
/* caller supplied a buffer and the target responded with data */
int copyLength = min((int)pConnectResp->BufferLength, (int)pResponseMsg->ServiceMetaLength);
/* copy the meta data */
A_MEMCPY(pConnectResp->pMetaData,
((A_UINT8 *)pResponseMsg) + sizeof(HTC_CONNECT_SERVICE_RESPONSE_MSG),
copyLength);
pConnectResp->ActualLength = copyLength;
}
}
/* the rest of these are parameter checks so set the error status */
status = A_EPROTO;
if (assignedEndpoint >= ENDPOINT_MAX) {
AR_DEBUG_ASSERT(FALSE);
break;
}
if (0 == maxMsgSize) {
AR_DEBUG_ASSERT(FALSE);
break;
}
pEndpoint = &target->EndPoint[assignedEndpoint];
pEndpoint->Id = assignedEndpoint;
if (pEndpoint->ServiceID != 0) {
/* endpoint already in use! */
AR_DEBUG_ASSERT(FALSE);
break;
}
/* return assigned endpoint to caller */
pConnectResp->Endpoint = assignedEndpoint;
pConnectResp->MaxMsgLength = maxMsgSize;
/* setup the endpoint */
pEndpoint->ServiceID = pConnectReq->ServiceID; /* this marks the endpoint in use */
pEndpoint->MaxTxQueueDepth = pConnectReq->MaxSendQueueDepth;
pEndpoint->MaxMsgLength = maxMsgSize;
/* copy all the callbacks */
pEndpoint->EpCallBacks = pConnectReq->EpCallbacks;
/* set the credit distribution info for this endpoint, this information is
* passed back to the credit distribution callback function */
pEndpoint->CreditDist.ServiceID = pConnectReq->ServiceID;
pEndpoint->CreditDist.pHTCReserved = pEndpoint;
pEndpoint->CreditDist.Endpoint = assignedEndpoint;
pEndpoint->CreditDist.TxCreditSize = target->TargetCreditSize;
if (pConnectReq->MaxSendMsgSize != 0) {
/* override TxCreditsPerMaxMsg calculation, this optimizes the credit-low indications
* since the host will actually issue smaller messages in the Send path */
if (pConnectReq->MaxSendMsgSize > maxMsgSize) {
/* can't be larger than the maximum the target can support */
AR_DEBUG_ASSERT(FALSE);
break;
}
pEndpoint->CreditDist.TxCreditsPerMaxMsg = pConnectReq->MaxSendMsgSize / target->TargetCreditSize;
} else {
pEndpoint->CreditDist.TxCreditsPerMaxMsg = maxMsgSize / target->TargetCreditSize;
}
if (0 == pEndpoint->CreditDist.TxCreditsPerMaxMsg) {
pEndpoint->CreditDist.TxCreditsPerMaxMsg = 1;
}
/* save local connection flags */
pEndpoint->LocalConnectionFlags = pConnectReq->LocalConnectionFlags;
status = A_OK;
} while (FALSE);
if (pSendPacket != NULL) {
HTC_FREE_CONTROL_TX(target,pSendPacket);
}
if (pRecvPacket != NULL) {
HTC_FREE_CONTROL_RX(target,pRecvPacket);
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRC, ("-HTCConnectService \n"));
return status;
}
static void AddToEndpointDistList(HTC_TARGET *target, HTC_ENDPOINT_CREDIT_DIST *pEpDist)
{
HTC_ENDPOINT_CREDIT_DIST *pCurEntry,*pLastEntry;
if (NULL == target->EpCreditDistributionListHead) {
target->EpCreditDistributionListHead = pEpDist;
pEpDist->pNext = NULL;
pEpDist->pPrev = NULL;
return;
}
/* queue to the end of the list, this does not have to be very
* fast since this list is built at startup time */
pCurEntry = target->EpCreditDistributionListHead;
while (pCurEntry) {
pLastEntry = pCurEntry;
pCurEntry = pCurEntry->pNext;
}
pLastEntry->pNext = pEpDist;
pEpDist->pPrev = pLastEntry;
pEpDist->pNext = NULL;
}
/* default credit init callback */
static void HTCDefaultCreditInit(void *Context,
HTC_ENDPOINT_CREDIT_DIST *pEPList,
int TotalCredits)
{
HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
int totalEps = 0;
int creditsPerEndpoint;
pCurEpDist = pEPList;
/* first run through the list and figure out how many endpoints we are dealing with */
while (pCurEpDist != NULL) {
pCurEpDist = pCurEpDist->pNext;
totalEps++;
}
/* even distribution */
creditsPerEndpoint = TotalCredits/totalEps;
pCurEpDist = pEPList;
/* run through the list and set minimum and normal credits and
* provide the endpoint with some credits to start */
while (pCurEpDist != NULL) {
if (creditsPerEndpoint < pCurEpDist->TxCreditsPerMaxMsg) {
/* too many endpoints and not enough credits */
AR_DEBUG_ASSERT(FALSE);
break;
}
/* our minimum is set for at least 1 max message */
pCurEpDist->TxCreditsMin = pCurEpDist->TxCreditsPerMaxMsg;
/* this value is ignored by our credit alg, since we do
* not dynamically adjust credits, this is the policy of
* the "default" credit distribution, something simple and easy */
pCurEpDist->TxCreditsNorm = 0xFFFF;
/* give the endpoint minimum credits */
pCurEpDist->TxCredits = creditsPerEndpoint;
pCurEpDist->TxCreditsAssigned = creditsPerEndpoint;
pCurEpDist = pCurEpDist->pNext;
}
}
/* default credit distribution callback, NOTE, this callback holds the TX lock */
void HTCDefaultCreditDist(void *Context,
HTC_ENDPOINT_CREDIT_DIST *pEPDistList,
HTC_CREDIT_DIST_REASON Reason)
{
HTC_ENDPOINT_CREDIT_DIST *pCurEpDist;
if (Reason == HTC_CREDIT_DIST_SEND_COMPLETE) {
pCurEpDist = pEPDistList;
/* simple distribution */
while (pCurEpDist != NULL) {
if (pCurEpDist->TxCreditsToDist > 0) {
/* just give the endpoint back the credits */
pCurEpDist->TxCredits += pCurEpDist->TxCreditsToDist;
pCurEpDist->TxCreditsToDist = 0;
}
pCurEpDist = pCurEpDist->pNext;
}
}
/* note we do not need to handle the other reason codes as this is a very
* simple distribution scheme, no need to seek for more credits or handle inactivity */
}
void HTCSetCreditDistribution(HTC_HANDLE HTCHandle,
void *pCreditDistContext,
HTC_CREDIT_DIST_CALLBACK CreditDistFunc,
HTC_CREDIT_INIT_CALLBACK CreditInitFunc,
HTC_SERVICE_ID ServicePriorityOrder[],
int ListLength)
{
HTC_TARGET *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
int i;
int ep;
if (CreditInitFunc != NULL) {
/* caller has supplied their own distribution functions */
target->InitCredits = CreditInitFunc;
AR_DEBUG_ASSERT(CreditDistFunc != NULL);
target->DistributeCredits = CreditDistFunc;
target->pCredDistContext = pCreditDistContext;
} else {
/* caller wants HTC to do distribution */
/* if caller wants service to handle distributions then
* it must set both of these to NULL! */
AR_DEBUG_ASSERT(CreditDistFunc == NULL);
target->InitCredits = HTCDefaultCreditInit;
target->DistributeCredits = HTCDefaultCreditDist;
target->pCredDistContext = target;
}
/* always add HTC control endpoint first, we only expose the list after the
* first one, this is added for TX queue checking */
AddToEndpointDistList(target, &target->EndPoint[ENDPOINT_0].CreditDist);
/* build the list of credit distribution structures in priority order
* supplied by the caller, these will follow endpoint 0 */
for (i = 0; i < ListLength; i++) {
/* match services with endpoints and add the endpoints to the distribution list
* in FIFO order */
for (ep = ENDPOINT_1; ep < ENDPOINT_MAX; ep++) {
if (target->EndPoint[ep].ServiceID == ServicePriorityOrder[i]) {
/* queue this one to the list */
AddToEndpointDistList(target, &target->EndPoint[ep].CreditDist);
break;
}
}
AR_DEBUG_ASSERT(ep < ENDPOINT_MAX);
}
}

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//------------------------------------------------------------------------------
// <copyright file="a_config.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains software configuration options that enables
// specific software "features"
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_CONFIG_H_
#define _A_CONFIG_H_
#ifdef UNDER_NWIFI
#include "../os/windows/include/config.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/config.h"
#endif
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/config_linux.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/config_rexos.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/win/config_win.h"
#endif
#ifdef THREADX
#include "../os/threadx/include/common/config_threadx.h"
#endif
#endif

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//------------------------------------------------------------------------------
// <copyright file="a_debug.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_DEBUG_H_
#define _A_DEBUG_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#include <a_types.h>
#include <a_osapi.h>
/* standard debug print masks bits 0..7 */
#define ATH_DEBUG_ERR (1 << 0) /* errors */
#define ATH_DEBUG_WARN (1 << 1) /* warnings */
#define ATH_DEBUG_INFO (1 << 2) /* informational (module startup info) */
#define ATH_DEBUG_TRC (1 << 3) /* generic function call tracing */
#define ATH_DEBUG_RSVD1 (1 << 4)
#define ATH_DEBUG_RSVD2 (1 << 5)
#define ATH_DEBUG_RSVD3 (1 << 6)
#define ATH_DEBUG_RSVD4 (1 << 7)
#define ATH_DEBUG_MASK_DEFAULTS (ATH_DEBUG_ERR | ATH_DEBUG_WARN)
#define ATH_DEBUG_ANY 0xFFFF
/* other aliases used throughout */
#define ATH_DEBUG_ERROR ATH_DEBUG_ERR
#define ATH_LOG_ERR ATH_DEBUG_ERR
#define ATH_LOG_INF ATH_DEBUG_INFO
#define ATH_LOG_TRC ATH_DEBUG_TRC
#define ATH_DEBUG_TRACE ATH_DEBUG_TRC
#define ATH_DEBUG_INIT ATH_DEBUG_INFO
/* bits 8..31 are module-specific masks */
#define ATH_DEBUG_MODULE_MASK_SHIFT 8
/* macro to make a module-specific masks */
#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
void DebugDumpBytes(A_UCHAR *buffer, A_UINT16 length, char *pDescription);
/* Debug support on a per-module basis
*
* Usage:
*
* Each module can utilize it's own debug mask variable. A set of commonly used
* masks are provided (ERRORS, WARNINGS, TRACE etc..). It is up to each module
* to define module-specific masks using the macros above.
*
* Each module defines a single debug mask variable debug_XXX where the "name" of the module is
* common to all C-files within that module. This requires every C-file that includes a_debug.h
* to define the module name in that file.
*
* Example:
*
* #define ATH_MODULE_NAME htc
* #include "a_debug.h"
*
* This will define a debug mask structure called debug_htc and all debug macros will reference this
* variable.
*
* A module can define module-specific bit masks using the ATH_DEBUG_MAKE_MODULE_MASK() macro:
*
* #define ATH_DEBUG_MY_MASK1 ATH_DEBUG_MAKE_MODULE_MASK(0)
* #define ATH_DEBUG_MY_MASK2 ATH_DEBUG_MAKE_MODULE_MASK(1)
*
* The instantiation of the debug structure should be made by the module. When a module is
* instantiated, the module can set a description string, a default mask and an array of description
* entries containing information on each module-defined debug mask.
* NOTE: The instantiation is statically allocated, only one instance can exist per module.
*
* Example:
*
*
* #define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
*
* #ifdef DEBUG
* static ATH_DEBUG_MASK_DESCRIPTION bmi_debug_desc[] = {
* { ATH_DEBUG_BMI , "BMI Tracing"}, <== description of the module specific mask
* };
*
* ATH_DEBUG_INSTANTIATE_MODULE_VAR(bmi,
* "bmi" <== module name
* "Boot Manager Interface", <== description of module
* ATH_DEBUG_MASK_DEFAULTS, <== defaults
* ATH_DEBUG_DESCRIPTION_COUNT(bmi_debug_desc),
* bmi_debug_desc);
*
* #endif
*
* A module can optionally register it's debug module information in order for other tools to change the
* bit mask at runtime. A module can call A_REGISTER_MODULE_DEBUG_INFO() in it's module
* init code. This macro can be called multiple times without consequence. The debug info maintains
* state to indicate whether the information was previously registered.
*
* */
#define ATH_DEBUG_MAX_MASK_DESC_LENGTH 32
#define ATH_DEBUG_MAX_MOD_DESC_LENGTH 64
typedef struct {
A_UINT32 Mask;
A_CHAR Description[ATH_DEBUG_MAX_MASK_DESC_LENGTH];
} ATH_DEBUG_MASK_DESCRIPTION;
#define ATH_DEBUG_INFO_FLAGS_REGISTERED (1 << 0)
typedef struct _ATH_DEBUG_MODULE_DBG_INFO{
struct _ATH_DEBUG_MODULE_DBG_INFO *pNext;
A_CHAR ModuleName[16];
A_CHAR ModuleDescription[ATH_DEBUG_MAX_MOD_DESC_LENGTH];
A_UINT32 Flags;
A_UINT32 CurrentMask;
int MaxDescriptions;
ATH_DEBUG_MASK_DESCRIPTION *pMaskDescriptions; /* pointer to array of descriptions */
} ATH_DEBUG_MODULE_DBG_INFO;
#define ATH_DEBUG_DESCRIPTION_COUNT(d) (int)((sizeof((d))) / (sizeof(ATH_DEBUG_MASK_DESCRIPTION)))
#define GET_ATH_MODULE_DEBUG_VAR_NAME(s) _XGET_ATH_MODULE_NAME_DEBUG_(s)
#define GET_ATH_MODULE_DEBUG_VAR_MASK(s) _XGET_ATH_MODULE_NAME_DEBUG_(s).CurrentMask
#define _XGET_ATH_MODULE_NAME_DEBUG_(s) debug_ ## s
#ifdef ATH_DEBUG_MODULE
/* for source files that will instantiate the debug variables */
#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions) \
ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s) = \
{NULL,(name),(moddesc),0,(initmask),count,(descriptions)}
#ifdef ATH_MODULE_NAME
extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(ATH_MODULE_NAME);
#define AR_DEBUG_LVL_CHECK(lvl) (GET_ATH_MODULE_DEBUG_VAR_MASK(ATH_MODULE_NAME) & (lvl))
#endif /* ATH_MODULE_NAME */
#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl) GET_ATH_MODULE_DEBUG_VAR_MASK(s) = (lvl)
#define ATH_DEBUG_DECLARE_EXTERN(s) \
extern ATH_DEBUG_MODULE_DBG_INFO GET_ATH_MODULE_DEBUG_VAR_NAME(s)
#define AR_DEBUG_PRINTBUF(buffer, length, desc) DebugDumpBytes(buffer,length,desc)
#define AR_DEBUG_ASSERT A_ASSERT
void a_dump_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
void a_register_module_debug_info(ATH_DEBUG_MODULE_DBG_INFO *pInfo);
#define A_DUMP_MODULE_DEBUG_INFO(s) a_dump_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
#define A_REGISTER_MODULE_DEBUG_INFO(s) a_register_module_debug_info(&(GET_ATH_MODULE_DEBUG_VAR_NAME(s)))
#else /* !ATH_DEBUG_MODULE */
/* NON ATH_DEBUG_MODULE */
#define ATH_DEBUG_INSTANTIATE_MODULE_VAR(s,name,moddesc,initmask,count,descriptions)
#define AR_DEBUG_LVL_CHECK(lvl) 0
#define AR_DEBUG_PRINTBUF(buffer, length, desc)
#define AR_DEBUG_ASSERT(test)
#define ATH_DEBUG_DECLARE_EXTERN(s)
#define ATH_DEBUG_SET_DEBUG_MASK(s,lvl)
#define A_DUMP_MODULE_DEBUG_INFO(s)
#define A_REGISTER_MODULE_DEBUG_INFO(s)
#endif
A_STATUS a_get_module_mask(A_CHAR *module_name, A_UINT32 *pMask);
A_STATUS a_set_module_mask(A_CHAR *module_name, A_UINT32 Mask);
void a_dump_module_debug_info_by_name(A_CHAR *module_name);
void a_module_debug_support_init(void);
void a_module_debug_support_cleanup(void);
#ifdef UNDER_NWIFI
#include "../os/windows/include/debug.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/debug.h"
#endif
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/debug_linux.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/debug_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/debug_win.h"
#endif
#ifdef WIN_NWF
#include <debug_win.h>
#endif
#ifdef THREADX
#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
#include "../os/threadx/include/common/debug_threadx.h"
#endif
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif

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//------------------------------------------------------------------------------
// <copyright file="a_drv.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of the basic atheros data types.
// It is used to map the data types in atheros files to a platform specific
// type.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_DRV_H_
#define _A_DRV_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/athdrv_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/athdrv.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athdrv.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/athdrv_rexos.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/athdrv.h"
#endif
#ifdef THREADX
#include "../os/threadx/include/common/athdrv_threadx.h"
#endif
#endif /* _ADRV_H_ */

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//------------------------------------------------------------------------------
// <copyright file="a_drv_api.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_DRV_API_H_
#define _A_DRV_API_H_
#ifdef __cplusplus
extern "C" {
#endif
/****************************************************************************/
/****************************************************************************/
/** **/
/** WMI related hooks **/
/** **/
/****************************************************************************/
/****************************************************************************/
#include <ar6000_api.h>
#define A_WMI_CHANNELLIST_RX(devt, numChan, chanList) \
ar6000_channelList_rx((devt), (numChan), (chanList))
#define A_WMI_SET_NUMDATAENDPTS(devt, num) \
ar6000_set_numdataendpts((devt), (num))
#define A_WMI_CONTROL_TX(devt, osbuf, streamID) \
ar6000_control_tx((devt), (osbuf), (streamID))
#define A_WMI_TARGETSTATS_EVENT(devt, pStats, len) \
ar6000_targetStats_event((devt), (pStats), (len))
#define A_WMI_SCANCOMPLETE_EVENT(devt, status) \
ar6000_scanComplete_event((devt), (status))
#ifdef CONFIG_HOST_DSET_SUPPORT
#define A_WMI_DSET_DATA_REQ(devt, access_cookie, offset, length, targ_buf, targ_reply_fn, targ_reply_arg) \
ar6000_dset_data_req((devt), (access_cookie), (offset), (length), (targ_buf), (targ_reply_fn), (targ_reply_arg))
#define A_WMI_DSET_CLOSE(devt, access_cookie) \
ar6000_dset_close((devt), (access_cookie))
#endif
#define A_WMI_DSET_OPEN_REQ(devt, id, targ_handle, targ_reply_fn, targ_reply_arg) \
ar6000_dset_open_req((devt), (id), (targ_handle), (targ_reply_fn), (targ_reply_arg))
#define A_WMI_CONNECT_EVENT(devt, channel, bssid, listenInterval, beaconInterval, networkType, beaconIeLen, assocReqLen, assocRespLen, assocInfo) \
ar6000_connect_event((devt), (channel), (bssid), (listenInterval), (beaconInterval), (networkType), (beaconIeLen), (assocReqLen), (assocRespLen), (assocInfo))
#define A_WMI_PSPOLL_EVENT(devt, aid)\
ar6000_pspoll_event((devt),(aid))
#define A_WMI_DTIMEXPIRY_EVENT(devt)\
ar6000_dtimexpiry_event((devt))
#ifdef WAPI_ENABLE
#define A_WMI_WAPI_REKEY_EVENT(devt, type, mac)\
ap_wapi_rekey_event((devt),(type),(mac))
#endif
#define A_WMI_REGDOMAIN_EVENT(devt, regCode) \
ar6000_regDomain_event((devt), (regCode))
#define A_WMI_NEIGHBORREPORT_EVENT(devt, numAps, info) \
ar6000_neighborReport_event((devt), (numAps), (info))
#define A_WMI_DISCONNECT_EVENT(devt, reason, bssid, assocRespLen, assocInfo, protocolReasonStatus) \
ar6000_disconnect_event((devt), (reason), (bssid), (assocRespLen), (assocInfo), (protocolReasonStatus))
#define A_WMI_TKIP_MICERR_EVENT(devt, keyid, ismcast) \
ar6000_tkip_micerr_event((devt), (keyid), (ismcast))
#define A_WMI_BITRATE_RX(devt, rateKbps) \
ar6000_bitrate_rx((devt), (rateKbps))
#define A_WMI_TXPWR_RX(devt, txPwr) \
ar6000_txPwr_rx((devt), (txPwr))
#define A_WMI_READY_EVENT(devt, datap, phyCap, sw_ver, abi_ver) \
ar6000_ready_event((devt), (datap), (phyCap), (sw_ver), (abi_ver))
#define A_WMI_DBGLOG_INIT_DONE(ar) \
ar6000_dbglog_init_done(ar);
#define A_WMI_RSSI_THRESHOLD_EVENT(devt, newThreshold, rssi) \
ar6000_rssiThreshold_event((devt), (newThreshold), (rssi))
#define A_WMI_REPORT_ERROR_EVENT(devt, errorVal) \
ar6000_reportError_event((devt), (errorVal))
#define A_WMI_ROAM_TABLE_EVENT(devt, pTbl) \
ar6000_roam_tbl_event((devt), (pTbl))
#define A_WMI_ROAM_DATA_EVENT(devt, p) \
ar6000_roam_data_event((devt), (p))
#define A_WMI_WOW_LIST_EVENT(devt, num_filters, wow_filters) \
ar6000_wow_list_event((devt), (num_filters), (wow_filters))
#define A_WMI_CAC_EVENT(devt, ac, cac_indication, statusCode, tspecSuggestion) \
ar6000_cac_event((devt), (ac), (cac_indication), (statusCode), (tspecSuggestion))
#define A_WMI_CHANNEL_CHANGE_EVENT(devt, oldChannel, newChannel) \
ar6000_channel_change_event((devt), (oldChannel), (newChannel))
#define A_WMI_PMKID_LIST_EVENT(devt, num_pmkid, pmkid_list, bssid_list) \
ar6000_pmkid_list_event((devt), (num_pmkid), (pmkid_list), (bssid_list))
#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \
ar6000_peer_event ((devt), (eventCode), (bssid))
#ifdef CONFIG_HOST_GPIO_SUPPORT
#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
ar6000_gpio_intr_rx((intr_mask), (input_values))
#define A_WMI_GPIO_DATA_RX(reg_id, value) \
ar6000_gpio_data_rx((reg_id), (value))
#define A_WMI_GPIO_ACK_RX() \
ar6000_gpio_ack_rx()
#endif
#ifdef SEND_EVENT_TO_APP
#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
ar6000_send_event_to_app((ar), (eventId), (datap), (len))
#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
#else
#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
#endif
#ifdef CONFIG_HOST_TCMD_SUPPORT
#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
ar6000_tcmd_rx_report_event((devt), (results), (len))
#endif
#define A_WMI_HBCHALLENGERESP_EVENT(devt, cookie, source) \
ar6000_hbChallengeResp_event((devt), (cookie), (source))
#define A_WMI_TX_RETRY_ERR_EVENT(devt) \
ar6000_tx_retry_err_event((devt))
#define A_WMI_SNR_THRESHOLD_EVENT_RX(devt, newThreshold, snr) \
ar6000_snrThresholdEvent_rx((devt), (newThreshold), (snr))
#define A_WMI_LQ_THRESHOLD_EVENT_RX(devt, range, lqVal) \
ar6000_lqThresholdEvent_rx((devt), (range), (lqVal))
#define A_WMI_RATEMASK_RX(devt, ratemask) \
ar6000_ratemask_rx((devt), (ratemask))
#define A_WMI_KEEPALIVE_RX(devt, configured) \
ar6000_keepalive_rx((devt), (configured))
#define A_WMI_BSSINFO_EVENT_RX(ar, datp, len) \
ar6000_bssInfo_event_rx((ar), (datap), (len))
#define A_WMI_DBGLOG_EVENT(ar, dropped, buffer, length) \
ar6000_dbglog_event((ar), (dropped), (buffer), (length));
#define A_WMI_STREAM_TX_ACTIVE(devt,trafficClass) \
ar6000_indicate_tx_activity((devt),(trafficClass), TRUE)
#define A_WMI_STREAM_TX_INACTIVE(devt,trafficClass) \
ar6000_indicate_tx_activity((devt),(trafficClass), FALSE)
#define A_WMI_Ac2EndpointID(devht, ac)\
ar6000_ac2_endpoint_id((devht), (ac))
#define A_WMI_AGGR_RECV_ADDBA_REQ_EVT(devt, cmd)\
ar6000_aggr_rcv_addba_req_evt((devt), (cmd))
#define A_WMI_AGGR_RECV_ADDBA_RESP_EVT(devt, cmd)\
ar6000_aggr_rcv_addba_resp_evt((devt), (cmd))
#define A_WMI_AGGR_RECV_DELBA_REQ_EVT(devt, cmd)\
ar6000_aggr_rcv_delba_req_evt((devt), (cmd))
#define A_WMI_HCI_EVENT_EVT(devt, cmd)\
ar6000_hci_event_rcv_evt((devt), (cmd))
#define A_WMI_Endpoint2Ac(devt, ep) \
ar6000_endpoint_id2_ac((devt), (ep))
#define A_WMI_BTCOEX_CONFIG_EVENT(devt, evt, len)\
ar6000_btcoex_config_event((devt), (evt), (len))
#define A_WMI_BTCOEX_STATS_EVENT(devt, datap, len)\
ar6000_btcoex_stats_event((devt), (datap), (len))
/****************************************************************************/
/****************************************************************************/
/** **/
/** HTC related hooks **/
/** **/
/****************************************************************************/
/****************************************************************************/
#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
#define A_WMI_PROF_COUNT_RX(addr, count) prof_count_rx((addr), (count))
#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
#ifdef __cplusplus
}
#endif
#endif

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//------------------------------------------------------------------------------
// <copyright file="a_osapi.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of the basic atheros data types.
// It is used to map the data types in atheros files to a platform specific
// type.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/osapi_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/osapi.h"
#include "../os/windows/include/netbuf.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/osapi.h"
#include "../os/windows/include/netbuf.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/osapi_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/osapi_win.h"
#include "../os/win_art/include/netbuf.h"
#endif
#ifdef WIN_NWF
#include <osapi_win.h>
#endif
#if defined(THREADX)
#include "../os/threadx/include/common/osapi_threadx.h"
#endif
#endif /* _OSAPI_H_ */

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//------------------------------------------------------------------------------
// <copyright file="a_types.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of the basic atheros data types.
// It is used to map the data types in atheros files to a platform specific
// type.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _A_TYPES_H_
#define _A_TYPES_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/athtypes_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/athtypes.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athtypes.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/athtypes_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/athtypes_win.h"
#endif
#ifdef WIN_NWF
#include <athtypes_win.h>
#endif
#ifdef THREADX
#include "../os/threadx/include/common/athtypes_threadx.h"
#endif
#endif /* _ATHTYPES_H_ */

140
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/*
*
* Copyright (c) 2004-2010 Atheros Communications Inc.
* All rights reserved.
*
*
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
*
*/
#ifndef __AGGR_RECV_API_H__
#define __AGGR_RECV_API_H__
#ifdef __cplusplus
extern "C" {
#endif
typedef void (* RX_CALLBACK)(void * dev, void *osbuf);
typedef void (* ALLOC_NETBUFS)(A_NETBUF_QUEUE_T *q, A_UINT16 num);
/*
* aggr_init:
* Initialises the data structures, allocates data queues and
* os buffers. Netbuf allocator is the input param, used by the
* aggr module for allocation of NETBUFs from driver context.
* These NETBUFs are used for AMSDU processing.
* Returns the context for the aggr module.
*/
void *
aggr_init(ALLOC_NETBUFS netbuf_allocator);
/*
* aggr_register_rx_dispatcher:
* Registers OS call back function to deliver the
* frames to OS. This is generally the topmost layer of
* the driver context, after which the frames go to
* IP stack via the call back function.
* This dispatcher is active only when aggregation is ON.
*/
void
aggr_register_rx_dispatcher(void *cntxt, void * dev, RX_CALLBACK fn);
/*
* aggr_process_bar:
* When target receives BAR, it communicates to host driver
* for modifying window parameters. Target indicates this via the
* event: WMI_ADDBA_REQ_EVENTID. Host will dequeue all frames
* up to the indicated sequence number.
*/
void
aggr_process_bar(void *cntxt, A_UINT8 tid, A_UINT16 seq_no);
/*
* aggr_recv_addba_req_evt:
* This event is to initiate/modify the receive side window.
* Target will send WMI_ADDBA_REQ_EVENTID event to host - to setup
* recv re-ordering queues. Target will negotiate ADDBA with peer,
* and indicate via this event after succesfully completing the
* negotiation. This happens in two situations:
* 1. Initial setup of aggregation
* 2. Renegotiation of current recv window.
* Window size for re-ordering is limited by target buffer
* space, which is reflected in win_sz.
* (Re)Start the periodic timer to deliver long standing frames,
* in hold_q to OS.
*/
void
aggr_recv_addba_req_evt(void * cntxt, A_UINT8 tid, A_UINT16 seq_no, A_UINT8 win_sz);
/*
* aggr_recv_delba_req_evt:
* Target indicates deletion of a BA window for a tid via the
* WMI_DELBA_EVENTID. Host would deliver all the frames in the
* hold_q, reset tid config and disable the periodic timer, if
* aggr is not enabled on any tid.
*/
void
aggr_recv_delba_req_evt(void * cntxt, A_UINT8 tid);
/*
* aggr_process_recv_frm:
* Called only for data frames. When aggr is ON for a tid, the buffer
* is always consumed, and osbuf would be NULL. For a non-aggr case,
* osbuf is not modified.
* AMSDU frames are consumed and are later freed. They are sliced and
* diced to individual frames and dispatched to stack.
* After consuming a osbuf(when aggr is ON), a previously registered
* callback may be called to deliver frames in order.
*/
void
aggr_process_recv_frm(void *cntxt, A_UINT8 tid, A_UINT16 seq_no, A_BOOL is_amsdu, void **osbuf);
/*
* aggr_module_destroy:
* Frees up all the queues and frames in them. Releases the cntxt to OS.
*/
void
aggr_module_destroy(void *cntxt);
/*
* Dumps the aggregation stats
*/
void
aggr_dump_stats(void *cntxt, PACKET_LOG **log_buf);
/*
* aggr_reset_state -- Called when it is deemed necessary to clear the aggregate
* hold Q state. Examples include when a Connect event or disconnect event is
* received.
*/
void
aggr_reset_state(void *cntxt);
#ifdef __cplusplus
}
#endif
#endif /*__AGGR_RECV_API_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
/* AR3K module configuration APIs for HCI-bridge operation */
#ifndef AR3KCONFIG_H_
#define AR3KCONFIG_H_
#include <net/bluetooth/bluetooth.h>
#include <net/bluetooth/hci_core.h>
#ifdef __cplusplus
extern "C" {
#endif
#define AR3K_CONFIG_FLAG_FORCE_MINBOOT_EXIT (1 << 0)
#define AR3K_CONFIG_FLAG_SET_AR3K_BAUD (1 << 1)
#define AR3K_CONFIG_FLAG_AR3K_BAUD_CHANGE_DELAY (1 << 2)
#define AR3K_CONFIG_FLAG_SET_AR6K_SCALE_STEP (1 << 3)
typedef struct {
A_UINT32 Flags; /* config flags */
void *pHCIDev; /* HCI bridge device */
HCI_TRANSPORT_PROPERTIES *pHCIProps; /* HCI bridge props */
HIF_DEVICE *pHIFDevice; /* HIF layer device */
A_UINT32 AR3KBaudRate; /* AR3K operational baud rate */
A_UINT16 AR6KScale; /* AR6K UART scale value */
A_UINT16 AR6KStep; /* AR6K UART step value */
struct hci_dev *pBtStackHCIDev; /* BT Stack HCI dev */
A_UINT32 PwrMgmtEnabled; /* TLPM enabled? */
A_UINT16 IdleTimeout; /* TLPM idle timeout */
A_UINT16 WakeupTimeout; /* TLPM wakeup timeout */
A_UINT8 bdaddr[6]; /* Bluetooth device address */
} AR3K_CONFIG_INFO;
A_STATUS AR3KConfigure(AR3K_CONFIG_INFO *pConfigInfo);
A_STATUS AR3KConfigureExit(void *config);
#ifdef __cplusplus
}
#endif
#endif /*AR3KCONFIG_H_*/

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//------------------------------------------------------------------------------
// <copyright file="ar6000_api.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the API to access the OS dependent atheros host driver
// by the WMI or WLAN generic modules.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _AR6000_API_H_
#define _AR6000_API_H_
#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/ar6xapi_linux.h"
#endif
#ifdef UNDER_NWIFI
#include "../os/windows/include/ar6xapi.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/ar6xapi.h"
#endif
#ifdef REXOS
#include "../os/rexos/include/common/ar6xapi_rexos.h"
#endif
#if defined ART_WIN
#include "../os/win_art/include/ar6xapi_win.h"
#endif
#ifdef WIN_NWF
#include "../os/windows/include/ar6xapi.h"
#endif
#endif /* _AR6000_API_H */

48
drivers/staging/ath6kl/include/ar6000_diag.h Normal file
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//------------------------------------------------------------------------------
// <copyright file="ar6000_diag.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef AR6000_DIAG_H_
#define AR6000_DIAG_H_
A_STATUS
ar6000_ReadRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
A_STATUS
ar6000_WriteRegDiag(HIF_DEVICE *hifDevice, A_UINT32 *address, A_UINT32 *data);
A_STATUS
ar6000_ReadDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
A_UCHAR *data, A_UINT32 length);
A_STATUS
ar6000_WriteDataDiag(HIF_DEVICE *hifDevice, A_UINT32 address,
A_UCHAR *data, A_UINT32 length);
A_STATUS
ar6k_ReadTargetRegister(HIF_DEVICE *hifDevice, int regsel, A_UINT32 *regval);
void
ar6k_FetchTargetRegs(HIF_DEVICE *hifDevice, A_UINT32 *targregs);
#endif /*AR6000_DIAG_H_*/

44
drivers/staging/ath6kl/include/ar6kap_common.h Normal file
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//------------------------------------------------------------------------------
// <copyright file="ar6kap_common.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// This file contains the definitions of common AP mode data structures.
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _AR6KAP_COMMON_H_
#define _AR6KAP_COMMON_H_
/*
* Used with AR6000_XIOCTL_AP_GET_STA_LIST
*/
typedef struct {
A_UINT8 mac[ATH_MAC_LEN];
A_UINT8 aid;
A_UINT8 keymgmt;
A_UINT8 ucipher;
A_UINT8 auth;
} station_t;
typedef struct {
station_t sta[AP_MAX_NUM_STA];
} ap_get_sta_t;
#endif /* _AR6KAP_COMMON_H_ */

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//------------------------------------------------------------------------------
// <copyright file="athbtfilter.h" company="Atheros">
// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Public Bluetooth filter APIs
// Author(s): ="Atheros"
//==============================================================================
#ifndef ATHBTFILTER_H_
#define ATHBTFILTER_H_
#define ATH_DEBUG_INFO (1 << 2)
#define ATH_DEBUG_INF ATH_DEBUG_INFO
typedef enum _ATHBT_HCI_CTRL_TYPE {
ATHBT_HCI_COMMAND = 0,
ATHBT_HCI_EVENT = 1,
} ATHBT_HCI_CTRL_TYPE;
typedef enum _ATHBT_STATE_INDICATION {
ATH_BT_NOOP = 0,
ATH_BT_INQUIRY = 1,
ATH_BT_CONNECT = 2,
ATH_BT_SCO = 3,
ATH_BT_ACL = 4,
ATH_BT_A2DP = 5,
ATH_BT_ESCO = 6,
/* new states go here.. */
ATH_BT_MAX_STATE_INDICATION
} ATHBT_STATE_INDICATION;
/* filter function for OUTGOING commands and INCOMMING events */
typedef void (*ATHBT_FILTER_CMD_EVENTS_FN)(void *pContext, ATHBT_HCI_CTRL_TYPE Type, unsigned char *pBuffer, int Length);
/* filter function for OUTGOING data HCI packets */
typedef void (*ATHBT_FILTER_DATA_FN)(void *pContext, unsigned char *pBuffer, int Length);
typedef enum _ATHBT_STATE {
STATE_OFF = 0,
STATE_ON = 1,
STATE_MAX
} ATHBT_STATE;
/* BT state indication (when filter functions are not used) */
typedef void (*ATHBT_INDICATE_STATE_FN)(void *pContext, ATHBT_STATE_INDICATION Indication, ATHBT_STATE State, unsigned char LMPVersion);
typedef struct _ATHBT_FILTER_INSTANCE {
#ifdef UNDER_CE
WCHAR *pWlanAdapterName; /* filled in by user */
#else
char *pWlanAdapterName; /* filled in by user */
#endif /* UNDER_CE */
int FilterEnabled; /* filtering is enabled */
int Attached; /* filter library is attached */
void *pContext; /* private context for filter library */
ATHBT_FILTER_CMD_EVENTS_FN pFilterCmdEvents; /* function ptr to filter a command or event */
ATHBT_FILTER_DATA_FN pFilterAclDataOut; /* function ptr to filter ACL data out (to radio) */
ATHBT_FILTER_DATA_FN pFilterAclDataIn; /* function ptr to filter ACL data in (from radio) */
ATHBT_INDICATE_STATE_FN pIndicateState; /* function ptr to indicate a state */
} ATH_BT_FILTER_INSTANCE;
/* API MACROS */
#define AthBtFilterHciCommand(instance,packet,length) \
if ((instance)->FilterEnabled) { \
(instance)->pFilterCmdEvents((instance)->pContext, \
ATHBT_HCI_COMMAND, \
(unsigned char *)(packet), \
(length)); \
}
#define AthBtFilterHciEvent(instance,packet,length) \
if ((instance)->FilterEnabled) { \
(instance)->pFilterCmdEvents((instance)->pContext, \
ATHBT_HCI_EVENT, \
(unsigned char *)(packet), \
(length)); \
}
#define AthBtFilterHciAclDataOut(instance,packet,length) \
if ((instance)->FilterEnabled) { \
(instance)->pFilterAclDataOut((instance)->pContext, \
(unsigned char *)(packet), \
(length)); \
}
#define AthBtFilterHciAclDataIn(instance,packet,length) \
if ((instance)->FilterEnabled) { \
(instance)->pFilterAclDataIn((instance)->pContext, \
(unsigned char *)(packet), \
(length)); \
}
/* if filtering is not desired, the application can indicate the state directly using this
* macro:
*/
#define AthBtIndicateState(instance,indication,state) \
if ((instance)->FilterEnabled) { \
(instance)->pIndicateState((instance)->pContext, \
(indication), \
(state), \
0); \
}
#ifdef __cplusplus
extern "C" {
#endif
/* API prototypes */
int AthBtFilter_Attach(ATH_BT_FILTER_INSTANCE *pInstance, unsigned int flags);
void AthBtFilter_Detach(ATH_BT_FILTER_INSTANCE *pInstance);
#ifdef __cplusplus
}
#endif
#endif /*ATHBTFILTER_H_*/

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drivers/staging/ath6kl/include/athendpack.h Normal file
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//------------------------------------------------------------------------------
// <copyright file="athendpack.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// end compiler-specific structure packing
//
// Author(s): ="Atheros"
//==============================================================================
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */
#ifdef INTEGRITY
#include "integrity/athendpack_integrity.h"
#endif /* INTEGRITY */
#ifdef NUCLEUS
#endif /* NUCLEUS */
#ifdef UNDER_NWIFI
#include "../os/windows/include/athendpack.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athendpack.h"
#endif /* WINCE */
#ifdef WIN_NWF
#include <athendpack_win.h>
#endif

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drivers/staging/ath6kl/include/athstartpack.h Normal file
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//------------------------------------------------------------------------------
// <copyright file="athstartpack.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// start compiler-specific structure packing
//
// Author(s): ="Atheros"
//==============================================================================
#ifdef VXWORKS
#endif /* VXWORKS */
#if defined(LINUX) || defined(__linux__)
#endif /* LINUX */
#ifdef QNX
#endif /* QNX */
#ifdef INTEGRITY
#include "integrity/athstartpack_integrity.h"
#endif /* INTEGRITY */
#ifdef NUCLEUS
#endif /* NUCLEUS */
#ifdef UNDER_NWIFI
#include "../os/windows/include/athstartpack.h"
#endif
#ifdef ATHR_CE_LEGACY
#include "../os/windows/include/athstartpack.h"
#endif /* WINCE */
#ifdef WIN_NWF
#include <athstartpack_win.h>
#endif
#ifdef THREADX
#include "../os/threadx/include/common/osapi_threadx.h"
#endif

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//------------------------------------------------------------------------------
// <copyright file="bmi.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// BMI declarations and prototypes
//
// Author(s): ="Atheros"
//==============================================================================
#ifndef _BMI_H_
#define _BMI_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Header files */
#include "a_config.h"
#include "athdefs.h"
#include "a_types.h"
#include "hif.h"
#include "a_osapi.h"
#include "bmi_msg.h"
void
BMIInit(void);
void
BMICleanup(void);
A_STATUS
BMIDone(HIF_DEVICE *device);
A_STATUS
BMIGetTargetInfo(HIF_DEVICE *device, struct bmi_target_info *targ_info);
A_STATUS
BMIReadMemory(HIF_DEVICE *device,
A_UINT32 address,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
BMIWriteMemory(HIF_DEVICE *device,
A_UINT32 address,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
BMIExecute(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 *param);
A_STATUS
BMISetAppStart(HIF_DEVICE *device,
A_UINT32 address);
A_STATUS
BMIReadSOCRegister(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 *param);
A_STATUS
BMIWriteSOCRegister(HIF_DEVICE *device,
A_UINT32 address,
A_UINT32 param);
A_STATUS
BMIrompatchInstall(HIF_DEVICE *device,
A_UINT32 ROM_addr,
A_UINT32 RAM_addr,
A_UINT32 nbytes,
A_UINT32 do_activate,
A_UINT32 *patch_id);
A_STATUS
BMIrompatchUninstall(HIF_DEVICE *device,
A_UINT32 rompatch_id);
A_STATUS
BMIrompatchActivate(HIF_DEVICE *device,
A_UINT32 rompatch_count,
A_UINT32 *rompatch_list);
A_STATUS
BMIrompatchDeactivate(HIF_DEVICE *device,
A_UINT32 rompatch_count,
A_UINT32 *rompatch_list);
A_STATUS
BMILZStreamStart(HIF_DEVICE *device,
A_UINT32 address);
A_STATUS
BMILZData(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
BMIFastDownload(HIF_DEVICE *device,
A_UINT32 address,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
BMIRawWrite(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length);
A_STATUS
BMIRawRead(HIF_DEVICE *device,
A_UCHAR *buffer,
A_UINT32 length,
A_BOOL want_timeout);
#ifdef __cplusplus
}
#endif
#endif /* _BMI_H_ */

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//------------------------------------------------------------------------------
// Copyright (c) 2006-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __AR6002_REGDUMP_H__
#define __AR6002_REGDUMP_H__
#if !defined(__ASSEMBLER__)
/*
* XTensa CPU state
* This must match the state saved by the target exception handler.
*/
struct XTensa_exception_frame_s {
A_UINT32 xt_pc;
A_UINT32 xt_ps;
A_UINT32 xt_sar;
A_UINT32 xt_vpri;
A_UINT32 xt_a2;
A_UINT32 xt_a3;
A_UINT32 xt_a4;
A_UINT32 xt_a5;
A_UINT32 xt_exccause;
A_UINT32 xt_lcount;
A_UINT32 xt_lbeg;
A_UINT32 xt_lend;
A_UINT32 epc1, epc2, epc3, epc4;
/* Extra info to simplify post-mortem stack walkback */
#define AR6002_REGDUMP_FRAMES 10
struct {
A_UINT32 a0; /* pc */
A_UINT32 a1; /* sp */
A_UINT32 a2;
A_UINT32 a3;
} wb[AR6002_REGDUMP_FRAMES];
};
typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
#define RD_SIZE sizeof(CPU_exception_frame_t)
#endif
#endif /* __AR6002_REGDUMP_H__ */

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drivers/staging/ath6kl/include/common/AR6002/AR6K_version.h Normal file
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//------------------------------------------------------------------------------
// <copyright file="AR6K_version.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#define __VER_MAJOR_ 3
#define __VER_MINOR_ 0
#define __VER_PATCH_ 0
/* The makear6ksdk script (used for release builds) modifies the following line. */
#define __BUILD_NUMBER_ 233
/* Format of the version number. */
#define VER_MAJOR_BIT_OFFSET 28
#define VER_MINOR_BIT_OFFSET 24
#define VER_PATCH_BIT_OFFSET 16
#define VER_BUILD_NUM_BIT_OFFSET 0
/*
* The version has the following format:
* Bits 28-31: Major version
* Bits 24-27: Minor version
* Bits 16-23: Patch version
* Bits 0-15: Build number (automatically generated during build process )
* E.g. Build 1.1.3.7 would be represented as 0x11030007.
*
* DO NOT split the following macro into multiple lines as this may confuse the build scripts.
*/
#define AR6K_SW_VERSION ( ( __VER_MAJOR_ << VER_MAJOR_BIT_OFFSET ) + ( __VER_MINOR_ << VER_MINOR_BIT_OFFSET ) + ( __VER_PATCH_ << VER_PATCH_BIT_OFFSET ) + ( __BUILD_NUMBER_ << VER_BUILD_NUM_BIT_OFFSET ) )
/* ABI Version. Reflects the version of binary interface exposed by AR6K target firmware. Needs to be incremented by 1 for any change in the firmware that requires upgrade of the driver on the host side for the change to work correctly */
#define AR6K_ABI_VERSION 1

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//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#ifndef __ADDRS_H__
#define __ADDRS_H__
/*
* Special AR6002 Addresses that may be needed by special
* applications (e.g. ART) on the Host as well as Target.
*/
#if defined(AR6002_REV2)
#define AR6K_RAM_START 0x00500000
#define TARG_RAM_OFFSET(vaddr) ((A_UINT32)(vaddr) & 0xfffff)
#define TARG_RAM_SZ (184*1024)
#define TARG_ROM_SZ (80*1024)
#endif
#if defined(AR6002_REV4) || defined(AR6003)
#define AR6K_RAM_START 0x00540000
#define TARG_RAM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0xfffff) - 0x40000)
#define TARG_RAM_SZ (256*1024)
#define TARG_ROM_SZ (256*1024)
#endif
#define AR6002_BOARD_DATA_SZ 768
#define AR6002_BOARD_EXT_DATA_SZ 0
#define AR6003_BOARD_DATA_SZ 1024
#define AR6003_BOARD_EXT_DATA_SZ 768
#define AR6K_RAM_ADDR(byte_offset) (AR6K_RAM_START+(byte_offset))
#define TARG_RAM_ADDRS(byte_offset) AR6K_RAM_ADDR(byte_offset)
#define AR6K_ROM_START 0x004e0000
#define TARG_ROM_OFFSET(vaddr) (((A_UINT32)(vaddr) & 0x1fffff) - 0xe0000)
#define AR6K_ROM_ADDR(byte_offset) (AR6K_ROM_START+(byte_offset))
#define TARG_ROM_ADDRS(byte_offset) AR6K_ROM_ADDR(byte_offset)
/*
* At this ROM address is a pointer to the start of the ROM DataSet Index.
* If there are no ROM DataSets, there's a 0 at this address.
*/
#define ROM_DATASET_INDEX_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-8)
#define ROM_MBIST_CKSUM_ADDR (TARG_ROM_ADDRS(TARG_ROM_SZ)-4)
/*
* The API A_BOARD_DATA_ADDR() is the proper way to get a read pointer to
* board data.
*/
/* Size of Board Data, in bytes */
#if defined(AR6002_REV4) || defined(AR6003)
#define BOARD_DATA_SZ AR6003_BOARD_DATA_SZ
#else
#define BOARD_DATA_SZ AR6002_BOARD_DATA_SZ
#endif
/*
* Constants used by ASM code to access fields of host_interest_s,
* which is at a fixed location in RAM.
*/
#if defined(AR6002_REV4) || defined(AR6003)
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x60c)
#else
#define HOST_INTEREST_FLASH_IS_PRESENT_ADDR (AR6K_RAM_START + 0x40c)
#endif
#define FLASH_IS_PRESENT_TARGADDR HOST_INTEREST_FLASH_IS_PRESENT_ADDR
#endif /* __ADDRS_H__ */

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drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_intf_reg.h Normal file
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#ifndef _ANALOG_INTF_REG_REG_H_
#define _ANALOG_INTF_REG_REG_H_
#define SW_OVERRIDE_ADDRESS 0x00000080
#define SW_OVERRIDE_OFFSET 0x00000080
#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
#define SW_OVERRIDE_ENABLE_MSB 0
#define SW_OVERRIDE_ENABLE_LSB 0
#define SW_OVERRIDE_ENABLE_MASK 0x00000001
#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
#define SIN_VAL_ADDRESS 0x00000084
#define SIN_VAL_OFFSET 0x00000084
#define SIN_VAL_SIN_MSB 0
#define SIN_VAL_SIN_LSB 0
#define SIN_VAL_SIN_MASK 0x00000001
#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
#define SW_SCLK_ADDRESS 0x00000088
#define SW_SCLK_OFFSET 0x00000088
#define SW_SCLK_SW_SCLK_MSB 0
#define SW_SCLK_SW_SCLK_LSB 0
#define SW_SCLK_SW_SCLK_MASK 0x00000001
#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
#define SW_CNTL_ADDRESS 0x0000008c
#define SW_CNTL_OFFSET 0x0000008c
#define SW_CNTL_SW_SCAPTURE_MSB 2
#define SW_CNTL_SW_SCAPTURE_LSB 2
#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
#define SW_CNTL_SW_SUPDATE_MSB 1
#define SW_CNTL_SW_SUPDATE_LSB 1
#define SW_CNTL_SW_SUPDATE_MASK 0x00000002
#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
#define SW_CNTL_SW_SOUT_MSB 0
#define SW_CNTL_SW_SOUT_LSB 0
#define SW_CNTL_SW_SOUT_MASK 0x00000001
#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
#ifndef __ASSEMBLER__
typedef struct analog_intf_reg_reg_s {
unsigned char pad0[128]; /* pad to 0x80 */
volatile unsigned int sw_override;
volatile unsigned int sin_val;
volatile unsigned int sw_sclk;
volatile unsigned int sw_cntl;
} analog_intf_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _ANALOG_INTF_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw.0/analog_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw.0/apb_map.h Normal file
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#ifndef _APB_MAP_H_
#define _APB_MAP_H_
#define RTC_BASE_ADDRESS 0x00004000
#define VMC_BASE_ADDRESS 0x00008000
#define UART_BASE_ADDRESS 0x0000c000
#define SI_BASE_ADDRESS 0x00010000
#define GPIO_BASE_ADDRESS 0x00014000
#define MBOX_BASE_ADDRESS 0x00018000
#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define MAC_BASE_ADDRESS 0x00020000
#endif /* _APB_MAP_REG_H_ */

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#ifndef _GPIO_REG_REG_H_
#define _GPIO_REG_REG_H_
#define GPIO_OUT_ADDRESS 0x00000000
#define GPIO_OUT_OFFSET 0x00000000
#define GPIO_OUT_DATA_MSB 17
#define GPIO_OUT_DATA_LSB 0
#define GPIO_OUT_DATA_MASK 0x0003ffff
#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
#define GPIO_OUT_W1TS_ADDRESS 0x00000004
#define GPIO_OUT_W1TS_OFFSET 0x00000004
#define GPIO_OUT_W1TS_DATA_MSB 17
#define GPIO_OUT_W1TS_DATA_LSB 0
#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff
#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
#define GPIO_OUT_W1TC_ADDRESS 0x00000008
#define GPIO_OUT_W1TC_OFFSET 0x00000008
#define GPIO_OUT_W1TC_DATA_MSB 17
#define GPIO_OUT_W1TC_DATA_LSB 0
#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff
#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
#define GPIO_ENABLE_ADDRESS 0x0000000c
#define GPIO_ENABLE_OFFSET 0x0000000c
#define GPIO_ENABLE_DATA_MSB 17
#define GPIO_ENABLE_DATA_LSB 0
#define GPIO_ENABLE_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010
#define GPIO_ENABLE_W1TS_OFFSET 0x00000010
#define GPIO_ENABLE_W1TS_DATA_MSB 17
#define GPIO_ENABLE_W1TS_DATA_LSB 0
#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014
#define GPIO_ENABLE_W1TC_OFFSET 0x00000014
#define GPIO_ENABLE_W1TC_DATA_MSB 17
#define GPIO_ENABLE_W1TC_DATA_LSB 0
#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff
#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
#define GPIO_IN_ADDRESS 0x00000018
#define GPIO_IN_OFFSET 0x00000018
#define GPIO_IN_DATA_MSB 17
#define GPIO_IN_DATA_LSB 0
#define GPIO_IN_DATA_MASK 0x0003ffff
#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
#define GPIO_STATUS_ADDRESS 0x0000001c
#define GPIO_STATUS_OFFSET 0x0000001c
#define GPIO_STATUS_INTERRUPT_MSB 17
#define GPIO_STATUS_INTERRUPT_LSB 0
#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
#define GPIO_STATUS_W1TS_ADDRESS 0x00000020
#define GPIO_STATUS_W1TS_OFFSET 0x00000020
#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17
#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0
#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
#define GPIO_STATUS_W1TC_ADDRESS 0x00000024
#define GPIO_STATUS_W1TC_OFFSET 0x00000024
#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17
#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0
#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff
#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
#define GPIO_PIN0_ADDRESS 0x00000028
#define GPIO_PIN0_OFFSET 0x00000028
#define GPIO_PIN0_CONFIG_MSB 12
#define GPIO_PIN0_CONFIG_LSB 11
#define GPIO_PIN0_CONFIG_MASK 0x00001800
#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
#define GPIO_PIN0_INT_TYPE_MSB 9
#define GPIO_PIN0_INT_TYPE_LSB 7
#define GPIO_PIN0_INT_TYPE_MASK 0x00000380
#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
#define GPIO_PIN0_PAD_DRIVER_MSB 2
#define GPIO_PIN0_PAD_DRIVER_LSB 2
#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
#define GPIO_PIN0_SOURCE_MSB 0
#define GPIO_PIN0_SOURCE_LSB 0
#define GPIO_PIN0_SOURCE_MASK 0x00000001
#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
#define GPIO_PIN1_ADDRESS 0x0000002c
#define GPIO_PIN1_OFFSET 0x0000002c
#define GPIO_PIN1_CONFIG_MSB 12
#define GPIO_PIN1_CONFIG_LSB 11
#define GPIO_PIN1_CONFIG_MASK 0x00001800
#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
#define GPIO_PIN1_INT_TYPE_MSB 9
#define GPIO_PIN1_INT_TYPE_LSB 7
#define GPIO_PIN1_INT_TYPE_MASK 0x00000380
#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
#define GPIO_PIN1_PAD_DRIVER_MSB 2
#define GPIO_PIN1_PAD_DRIVER_LSB 2
#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
#define GPIO_PIN1_SOURCE_MSB 0
#define GPIO_PIN1_SOURCE_LSB 0
#define GPIO_PIN1_SOURCE_MASK 0x00000001
#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
#define GPIO_PIN2_ADDRESS 0x00000030
#define GPIO_PIN2_OFFSET 0x00000030
#define GPIO_PIN2_CONFIG_MSB 12
#define GPIO_PIN2_CONFIG_LSB 11
#define GPIO_PIN2_CONFIG_MASK 0x00001800
#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
#define GPIO_PIN2_INT_TYPE_MSB 9
#define GPIO_PIN2_INT_TYPE_LSB 7
#define GPIO_PIN2_INT_TYPE_MASK 0x00000380
#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
#define GPIO_PIN2_PAD_DRIVER_MSB 2
#define GPIO_PIN2_PAD_DRIVER_LSB 2
#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
#define GPIO_PIN2_SOURCE_MSB 0
#define GPIO_PIN2_SOURCE_LSB 0
#define GPIO_PIN2_SOURCE_MASK 0x00000001
#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
#define GPIO_PIN3_ADDRESS 0x00000034
#define GPIO_PIN3_OFFSET 0x00000034
#define GPIO_PIN3_CONFIG_MSB 12
#define GPIO_PIN3_CONFIG_LSB 11
#define GPIO_PIN3_CONFIG_MASK 0x00001800
#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
#define GPIO_PIN3_INT_TYPE_MSB 9
#define GPIO_PIN3_INT_TYPE_LSB 7
#define GPIO_PIN3_INT_TYPE_MASK 0x00000380
#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
#define GPIO_PIN3_PAD_DRIVER_MSB 2
#define GPIO_PIN3_PAD_DRIVER_LSB 2
#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
#define GPIO_PIN3_SOURCE_MSB 0
#define GPIO_PIN3_SOURCE_LSB 0
#define GPIO_PIN3_SOURCE_MASK 0x00000001
#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
#define GPIO_PIN4_ADDRESS 0x00000038
#define GPIO_PIN4_OFFSET 0x00000038
#define GPIO_PIN4_CONFIG_MSB 12
#define GPIO_PIN4_CONFIG_LSB 11
#define GPIO_PIN4_CONFIG_MASK 0x00001800
#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
#define GPIO_PIN4_INT_TYPE_MSB 9
#define GPIO_PIN4_INT_TYPE_LSB 7
#define GPIO_PIN4_INT_TYPE_MASK 0x00000380
#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
#define GPIO_PIN4_PAD_DRIVER_MSB 2
#define GPIO_PIN4_PAD_DRIVER_LSB 2
#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
#define GPIO_PIN4_SOURCE_MSB 0
#define GPIO_PIN4_SOURCE_LSB 0
#define GPIO_PIN4_SOURCE_MASK 0x00000001
#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
#define GPIO_PIN5_ADDRESS 0x0000003c
#define GPIO_PIN5_OFFSET 0x0000003c
#define GPIO_PIN5_CONFIG_MSB 12
#define GPIO_PIN5_CONFIG_LSB 11
#define GPIO_PIN5_CONFIG_MASK 0x00001800
#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
#define GPIO_PIN5_INT_TYPE_MSB 9
#define GPIO_PIN5_INT_TYPE_LSB 7
#define GPIO_PIN5_INT_TYPE_MASK 0x00000380
#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
#define GPIO_PIN5_PAD_DRIVER_MSB 2
#define GPIO_PIN5_PAD_DRIVER_LSB 2
#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
#define GPIO_PIN5_SOURCE_MSB 0
#define GPIO_PIN5_SOURCE_LSB 0
#define GPIO_PIN5_SOURCE_MASK 0x00000001
#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
#define GPIO_PIN6_ADDRESS 0x00000040
#define GPIO_PIN6_OFFSET 0x00000040
#define GPIO_PIN6_CONFIG_MSB 12
#define GPIO_PIN6_CONFIG_LSB 11
#define GPIO_PIN6_CONFIG_MASK 0x00001800
#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
#define GPIO_PIN6_INT_TYPE_MSB 9
#define GPIO_PIN6_INT_TYPE_LSB 7
#define GPIO_PIN6_INT_TYPE_MASK 0x00000380
#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
#define GPIO_PIN6_PAD_DRIVER_MSB 2
#define GPIO_PIN6_PAD_DRIVER_LSB 2
#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
#define GPIO_PIN6_SOURCE_MSB 0
#define GPIO_PIN6_SOURCE_LSB 0
#define GPIO_PIN6_SOURCE_MASK 0x00000001
#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
#define GPIO_PIN7_ADDRESS 0x00000044
#define GPIO_PIN7_OFFSET 0x00000044
#define GPIO_PIN7_CONFIG_MSB 12
#define GPIO_PIN7_CONFIG_LSB 11
#define GPIO_PIN7_CONFIG_MASK 0x00001800
#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
#define GPIO_PIN7_INT_TYPE_MSB 9
#define GPIO_PIN7_INT_TYPE_LSB 7
#define GPIO_PIN7_INT_TYPE_MASK 0x00000380
#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
#define GPIO_PIN7_PAD_DRIVER_MSB 2
#define GPIO_PIN7_PAD_DRIVER_LSB 2
#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
#define GPIO_PIN7_SOURCE_MSB 0
#define GPIO_PIN7_SOURCE_LSB 0
#define GPIO_PIN7_SOURCE_MASK 0x00000001
#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
#define GPIO_PIN8_ADDRESS 0x00000048
#define GPIO_PIN8_OFFSET 0x00000048
#define GPIO_PIN8_CONFIG_MSB 12
#define GPIO_PIN8_CONFIG_LSB 11
#define GPIO_PIN8_CONFIG_MASK 0x00001800
#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
#define GPIO_PIN8_INT_TYPE_MSB 9
#define GPIO_PIN8_INT_TYPE_LSB 7
#define GPIO_PIN8_INT_TYPE_MASK 0x00000380
#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
#define GPIO_PIN8_PAD_DRIVER_MSB 2
#define GPIO_PIN8_PAD_DRIVER_LSB 2
#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
#define GPIO_PIN8_SOURCE_MSB 0
#define GPIO_PIN8_SOURCE_LSB 0
#define GPIO_PIN8_SOURCE_MASK 0x00000001
#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
#define GPIO_PIN9_ADDRESS 0x0000004c
#define GPIO_PIN9_OFFSET 0x0000004c
#define GPIO_PIN9_CONFIG_MSB 12
#define GPIO_PIN9_CONFIG_LSB 11
#define GPIO_PIN9_CONFIG_MASK 0x00001800
#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
#define GPIO_PIN9_INT_TYPE_MSB 9
#define GPIO_PIN9_INT_TYPE_LSB 7
#define GPIO_PIN9_INT_TYPE_MASK 0x00000380
#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
#define GPIO_PIN9_PAD_DRIVER_MSB 2
#define GPIO_PIN9_PAD_DRIVER_LSB 2
#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
#define GPIO_PIN9_SOURCE_MSB 0
#define GPIO_PIN9_SOURCE_LSB 0
#define GPIO_PIN9_SOURCE_MASK 0x00000001
#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
#define GPIO_PIN10_ADDRESS 0x00000050
#define GPIO_PIN10_OFFSET 0x00000050
#define GPIO_PIN10_CONFIG_MSB 12
#define GPIO_PIN10_CONFIG_LSB 11
#define GPIO_PIN10_CONFIG_MASK 0x00001800
#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
#define GPIO_PIN10_INT_TYPE_MSB 9
#define GPIO_PIN10_INT_TYPE_LSB 7
#define GPIO_PIN10_INT_TYPE_MASK 0x00000380
#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
#define GPIO_PIN10_PAD_DRIVER_MSB 2
#define GPIO_PIN10_PAD_DRIVER_LSB 2
#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
#define GPIO_PIN10_SOURCE_MSB 0
#define GPIO_PIN10_SOURCE_LSB 0
#define GPIO_PIN10_SOURCE_MASK 0x00000001
#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
#define GPIO_PIN11_ADDRESS 0x00000054
#define GPIO_PIN11_OFFSET 0x00000054
#define GPIO_PIN11_CONFIG_MSB 12
#define GPIO_PIN11_CONFIG_LSB 11
#define GPIO_PIN11_CONFIG_MASK 0x00001800
#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
#define GPIO_PIN11_INT_TYPE_MSB 9
#define GPIO_PIN11_INT_TYPE_LSB 7
#define GPIO_PIN11_INT_TYPE_MASK 0x00000380
#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
#define GPIO_PIN11_PAD_DRIVER_MSB 2
#define GPIO_PIN11_PAD_DRIVER_LSB 2
#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
#define GPIO_PIN11_SOURCE_MSB 0
#define GPIO_PIN11_SOURCE_LSB 0
#define GPIO_PIN11_SOURCE_MASK 0x00000001
#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
#define GPIO_PIN12_ADDRESS 0x00000058
#define GPIO_PIN12_OFFSET 0x00000058
#define GPIO_PIN12_CONFIG_MSB 12
#define GPIO_PIN12_CONFIG_LSB 11
#define GPIO_PIN12_CONFIG_MASK 0x00001800
#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
#define GPIO_PIN12_INT_TYPE_MSB 9
#define GPIO_PIN12_INT_TYPE_LSB 7
#define GPIO_PIN12_INT_TYPE_MASK 0x00000380
#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
#define GPIO_PIN12_PAD_DRIVER_MSB 2
#define GPIO_PIN12_PAD_DRIVER_LSB 2
#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
#define GPIO_PIN12_SOURCE_MSB 0
#define GPIO_PIN12_SOURCE_LSB 0
#define GPIO_PIN12_SOURCE_MASK 0x00000001
#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
#define GPIO_PIN13_ADDRESS 0x0000005c
#define GPIO_PIN13_OFFSET 0x0000005c
#define GPIO_PIN13_CONFIG_MSB 12
#define GPIO_PIN13_CONFIG_LSB 11
#define GPIO_PIN13_CONFIG_MASK 0x00001800
#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
#define GPIO_PIN13_INT_TYPE_MSB 9
#define GPIO_PIN13_INT_TYPE_LSB 7
#define GPIO_PIN13_INT_TYPE_MASK 0x00000380
#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
#define GPIO_PIN13_PAD_DRIVER_MSB 2
#define GPIO_PIN13_PAD_DRIVER_LSB 2
#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
#define GPIO_PIN13_SOURCE_MSB 0
#define GPIO_PIN13_SOURCE_LSB 0
#define GPIO_PIN13_SOURCE_MASK 0x00000001
#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
#define GPIO_PIN14_ADDRESS 0x00000060
#define GPIO_PIN14_OFFSET 0x00000060
#define GPIO_PIN14_CONFIG_MSB 12
#define GPIO_PIN14_CONFIG_LSB 11
#define GPIO_PIN14_CONFIG_MASK 0x00001800
#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
#define GPIO_PIN14_INT_TYPE_MSB 9
#define GPIO_PIN14_INT_TYPE_LSB 7
#define GPIO_PIN14_INT_TYPE_MASK 0x00000380
#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
#define GPIO_PIN14_PAD_DRIVER_MSB 2
#define GPIO_PIN14_PAD_DRIVER_LSB 2
#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
#define GPIO_PIN14_SOURCE_MSB 0
#define GPIO_PIN14_SOURCE_LSB 0
#define GPIO_PIN14_SOURCE_MASK 0x00000001
#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
#define GPIO_PIN15_ADDRESS 0x00000064
#define GPIO_PIN15_OFFSET 0x00000064
#define GPIO_PIN15_CONFIG_MSB 12
#define GPIO_PIN15_CONFIG_LSB 11
#define GPIO_PIN15_CONFIG_MASK 0x00001800
#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
#define GPIO_PIN15_INT_TYPE_MSB 9
#define GPIO_PIN15_INT_TYPE_LSB 7
#define GPIO_PIN15_INT_TYPE_MASK 0x00000380
#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
#define GPIO_PIN15_PAD_DRIVER_MSB 2
#define GPIO_PIN15_PAD_DRIVER_LSB 2
#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
#define GPIO_PIN15_SOURCE_MSB 0
#define GPIO_PIN15_SOURCE_LSB 0
#define GPIO_PIN15_SOURCE_MASK 0x00000001
#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
#define GPIO_PIN16_ADDRESS 0x00000068
#define GPIO_PIN16_OFFSET 0x00000068
#define GPIO_PIN16_CONFIG_MSB 12
#define GPIO_PIN16_CONFIG_LSB 11
#define GPIO_PIN16_CONFIG_MASK 0x00001800
#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
#define GPIO_PIN16_INT_TYPE_MSB 9
#define GPIO_PIN16_INT_TYPE_LSB 7
#define GPIO_PIN16_INT_TYPE_MASK 0x00000380
#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
#define GPIO_PIN16_PAD_DRIVER_MSB 2
#define GPIO_PIN16_PAD_DRIVER_LSB 2
#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
#define GPIO_PIN16_SOURCE_MSB 0
#define GPIO_PIN16_SOURCE_LSB 0
#define GPIO_PIN16_SOURCE_MASK 0x00000001
#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
#define GPIO_PIN17_ADDRESS 0x0000006c
#define GPIO_PIN17_OFFSET 0x0000006c
#define GPIO_PIN17_CONFIG_MSB 12
#define GPIO_PIN17_CONFIG_LSB 11
#define GPIO_PIN17_CONFIG_MASK 0x00001800
#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10
#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10
#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
#define GPIO_PIN17_INT_TYPE_MSB 9
#define GPIO_PIN17_INT_TYPE_LSB 7
#define GPIO_PIN17_INT_TYPE_MASK 0x00000380
#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
#define GPIO_PIN17_PAD_DRIVER_MSB 2
#define GPIO_PIN17_PAD_DRIVER_LSB 2
#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
#define GPIO_PIN17_SOURCE_MSB 0
#define GPIO_PIN17_SOURCE_LSB 0
#define GPIO_PIN17_SOURCE_MASK 0x00000001
#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
#define SDIO_PIN_ADDRESS 0x00000070
#define SDIO_PIN_OFFSET 0x00000070
#define SDIO_PIN_PAD_PULL_MSB 3
#define SDIO_PIN_PAD_PULL_LSB 2
#define SDIO_PIN_PAD_PULL_MASK 0x0000000c
#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
#define SDIO_PIN_PAD_STRENGTH_MSB 1
#define SDIO_PIN_PAD_STRENGTH_LSB 0
#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003
#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
#define CLK_REQ_PIN_ADDRESS 0x00000074
#define CLK_REQ_PIN_OFFSET 0x00000074
#define CLK_REQ_PIN_ATE_OE_L_MSB 4
#define CLK_REQ_PIN_ATE_OE_L_LSB 4
#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010
#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
#define CLK_REQ_PIN_PAD_PULL_MSB 3
#define CLK_REQ_PIN_PAD_PULL_LSB 2
#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c
#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1
#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0
#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003
#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
#define SIGMA_DELTA_ADDRESS 0x00000078
#define SIGMA_DELTA_OFFSET 0x00000078
#define SIGMA_DELTA_ENABLE_MSB 16
#define SIGMA_DELTA_ENABLE_LSB 16
#define SIGMA_DELTA_ENABLE_MASK 0x00010000
#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
#define SIGMA_DELTA_PRESCALAR_MSB 15
#define SIGMA_DELTA_PRESCALAR_LSB 8
#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
#define SIGMA_DELTA_TARGET_MSB 7
#define SIGMA_DELTA_TARGET_LSB 0
#define SIGMA_DELTA_TARGET_MASK 0x000000ff
#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
#define DEBUG_CONTROL_ADDRESS 0x0000007c
#define DEBUG_CONTROL_OFFSET 0x0000007c
#define DEBUG_CONTROL_OBS_OE_L_MSB 1
#define DEBUG_CONTROL_OBS_OE_L_LSB 1
#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002
#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
#define DEBUG_CONTROL_ENABLE_MSB 0
#define DEBUG_CONTROL_ENABLE_LSB 0
#define DEBUG_CONTROL_ENABLE_MASK 0x00000001
#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
#define DEBUG_INPUT_SEL_ADDRESS 0x00000080
#define DEBUG_INPUT_SEL_OFFSET 0x00000080
#define DEBUG_INPUT_SEL_SRC_MSB 3
#define DEBUG_INPUT_SEL_SRC_LSB 0
#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
#define DEBUG_OUT_ADDRESS 0x00000084
#define DEBUG_OUT_OFFSET 0x00000084
#define DEBUG_OUT_DATA_MSB 17
#define DEBUG_OUT_DATA_LSB 0
#define DEBUG_OUT_DATA_MASK 0x0003ffff
#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
#define LA_CONTROL_ADDRESS 0x00000088
#define LA_CONTROL_OFFSET 0x00000088
#define LA_CONTROL_RUN_MSB 1
#define LA_CONTROL_RUN_LSB 1
#define LA_CONTROL_RUN_MASK 0x00000002
#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
#define LA_CONTROL_TRIGGERED_MSB 0
#define LA_CONTROL_TRIGGERED_LSB 0
#define LA_CONTROL_TRIGGERED_MASK 0x00000001
#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
#define LA_CLOCK_ADDRESS 0x0000008c
#define LA_CLOCK_OFFSET 0x0000008c
#define LA_CLOCK_DIV_MSB 7
#define LA_CLOCK_DIV_LSB 0
#define LA_CLOCK_DIV_MASK 0x000000ff
#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
#define LA_STATUS_ADDRESS 0x00000090
#define LA_STATUS_OFFSET 0x00000090
#define LA_STATUS_INTERRUPT_MSB 0
#define LA_STATUS_INTERRUPT_LSB 0
#define LA_STATUS_INTERRUPT_MASK 0x00000001
#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094
#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094
#define LA_TRIGGER_SAMPLE_COUNT_MSB 15
#define LA_TRIGGER_SAMPLE_COUNT_LSB 0
#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff
#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
#define LA_TRIGGER_POSITION_ADDRESS 0x00000098
#define LA_TRIGGER_POSITION_OFFSET 0x00000098
#define LA_TRIGGER_POSITION_VALUE_MSB 15
#define LA_TRIGGER_POSITION_VALUE_LSB 0
#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff
#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
#define LA_PRE_TRIGGER_ADDRESS 0x0000009c
#define LA_PRE_TRIGGER_OFFSET 0x0000009c
#define LA_PRE_TRIGGER_COUNT_MSB 15
#define LA_PRE_TRIGGER_COUNT_LSB 0
#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff
#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
#define LA_POST_TRIGGER_ADDRESS 0x000000a0
#define LA_POST_TRIGGER_OFFSET 0x000000a0
#define LA_POST_TRIGGER_COUNT_MSB 15
#define LA_POST_TRIGGER_COUNT_LSB 0
#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff
#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
#define LA_FILTER_CONTROL_ADDRESS 0x000000a4
#define LA_FILTER_CONTROL_OFFSET 0x000000a4
#define LA_FILTER_CONTROL_DELTA_MSB 0
#define LA_FILTER_CONTROL_DELTA_LSB 0
#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001
#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
#define LA_FILTER_DATA_ADDRESS 0x000000a8
#define LA_FILTER_DATA_OFFSET 0x000000a8
#define LA_FILTER_DATA_MATCH_MSB 17
#define LA_FILTER_DATA_MATCH_LSB 0
#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff
#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac
#define LA_FILTER_WILDCARD_OFFSET 0x000000ac
#define LA_FILTER_WILDCARD_MATCH_MSB 17
#define LA_FILTER_WILDCARD_MATCH_LSB 0
#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0
#define LA_TRIGGERA_DATA_OFFSET 0x000000b0
#define LA_TRIGGERA_DATA_MATCH_MSB 17
#define LA_TRIGGERA_DATA_MATCH_LSB 0
#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff
#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4
#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4
#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17
#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0
#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8
#define LA_TRIGGERB_DATA_OFFSET 0x000000b8
#define LA_TRIGGERB_DATA_MATCH_MSB 17
#define LA_TRIGGERB_DATA_MATCH_LSB 0
#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff
#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc
#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc
#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17
#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0
#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff
#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
#define LA_TRIGGER_ADDRESS 0x000000c0
#define LA_TRIGGER_OFFSET 0x000000c0
#define LA_TRIGGER_EVENT_MSB 2
#define LA_TRIGGER_EVENT_LSB 0
#define LA_TRIGGER_EVENT_MASK 0x00000007
#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
#define LA_FIFO_ADDRESS 0x000000c4
#define LA_FIFO_OFFSET 0x000000c4
#define LA_FIFO_FULL_MSB 1
#define LA_FIFO_FULL_LSB 1
#define LA_FIFO_FULL_MASK 0x00000002
#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
#define LA_FIFO_EMPTY_MSB 0
#define LA_FIFO_EMPTY_LSB 0
#define LA_FIFO_EMPTY_MASK 0x00000001
#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
#define LA_ADDRESS 0x000000c8
#define LA_OFFSET 0x000000c8
#define LA_DATA_MSB 17
#define LA_DATA_LSB 0
#define LA_DATA_MASK 0x0003ffff
#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK)
#define ANT_PIN_ADDRESS 0x000000d0
#define ANT_PIN_OFFSET 0x000000d0
#define ANT_PIN_PAD_PULL_MSB 3
#define ANT_PIN_PAD_PULL_LSB 2
#define ANT_PIN_PAD_PULL_MASK 0x0000000c
#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
#define ANT_PIN_PAD_STRENGTH_MSB 1
#define ANT_PIN_PAD_STRENGTH_LSB 0
#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003
#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
#define ANTD_PIN_ADDRESS 0x000000d4
#define ANTD_PIN_OFFSET 0x000000d4
#define ANTD_PIN_PAD_PULL_MSB 1
#define ANTD_PIN_PAD_PULL_LSB 0
#define ANTD_PIN_PAD_PULL_MASK 0x00000003
#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
#define GPIO_PIN_ADDRESS 0x000000d8
#define GPIO_PIN_OFFSET 0x000000d8
#define GPIO_PIN_PAD_PULL_MSB 3
#define GPIO_PIN_PAD_PULL_LSB 2
#define GPIO_PIN_PAD_PULL_MASK 0x0000000c
#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
#define GPIO_PIN_PAD_STRENGTH_MSB 1
#define GPIO_PIN_PAD_STRENGTH_LSB 0
#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003
#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
#define GPIO_H_PIN_ADDRESS 0x000000dc
#define GPIO_H_PIN_OFFSET 0x000000dc
#define GPIO_H_PIN_PAD_PULL_MSB 1
#define GPIO_H_PIN_PAD_PULL_LSB 0
#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003
#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
#define BT_PIN_ADDRESS 0x000000e0
#define BT_PIN_OFFSET 0x000000e0
#define BT_PIN_PAD_PULL_MSB 3
#define BT_PIN_PAD_PULL_LSB 2
#define BT_PIN_PAD_PULL_MASK 0x0000000c
#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
#define BT_PIN_PAD_STRENGTH_MSB 1
#define BT_PIN_PAD_STRENGTH_LSB 0
#define BT_PIN_PAD_STRENGTH_MASK 0x00000003
#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
#define BT_WLAN_PIN_ADDRESS 0x000000e4
#define BT_WLAN_PIN_OFFSET 0x000000e4
#define BT_WLAN_PIN_PAD_PULL_MSB 1
#define BT_WLAN_PIN_PAD_PULL_LSB 0
#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003
#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
#define SI_UART_PIN_ADDRESS 0x000000e8
#define SI_UART_PIN_OFFSET 0x000000e8
#define SI_UART_PIN_PAD_PULL_MSB 3
#define SI_UART_PIN_PAD_PULL_LSB 2
#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c
#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
#define SI_UART_PIN_PAD_STRENGTH_MSB 1
#define SI_UART_PIN_PAD_STRENGTH_LSB 0
#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003
#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
#define CLK32K_PIN_ADDRESS 0x000000ec
#define CLK32K_PIN_OFFSET 0x000000ec
#define CLK32K_PIN_PAD_PULL_MSB 1
#define CLK32K_PIN_PAD_PULL_LSB 0
#define CLK32K_PIN_PAD_PULL_MASK 0x00000003
#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0
#define RESET_TUPLE_STATUS_OFFSET 0x000000f0
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
#ifndef __ASSEMBLER__
typedef struct gpio_reg_reg_s {
volatile unsigned int gpio_out;
volatile unsigned int gpio_out_w1ts;
volatile unsigned int gpio_out_w1tc;
volatile unsigned int gpio_enable;
volatile unsigned int gpio_enable_w1ts;
volatile unsigned int gpio_enable_w1tc;
volatile unsigned int gpio_in;
volatile unsigned int gpio_status;
volatile unsigned int gpio_status_w1ts;
volatile unsigned int gpio_status_w1tc;
volatile unsigned int gpio_pin0;
volatile unsigned int gpio_pin1;
volatile unsigned int gpio_pin2;
volatile unsigned int gpio_pin3;
volatile unsigned int gpio_pin4;
volatile unsigned int gpio_pin5;
volatile unsigned int gpio_pin6;
volatile unsigned int gpio_pin7;
volatile unsigned int gpio_pin8;
volatile unsigned int gpio_pin9;
volatile unsigned int gpio_pin10;
volatile unsigned int gpio_pin11;
volatile unsigned int gpio_pin12;
volatile unsigned int gpio_pin13;
volatile unsigned int gpio_pin14;
volatile unsigned int gpio_pin15;
volatile unsigned int gpio_pin16;
volatile unsigned int gpio_pin17;
volatile unsigned int sdio_pin;
volatile unsigned int clk_req_pin;
volatile unsigned int sigma_delta;
volatile unsigned int debug_control;
volatile unsigned int debug_input_sel;
volatile unsigned int debug_out;
volatile unsigned int la_control;
volatile unsigned int la_clock;
volatile unsigned int la_status;
volatile unsigned int la_trigger_sample;
volatile unsigned int la_trigger_position;
volatile unsigned int la_pre_trigger;
volatile unsigned int la_post_trigger;
volatile unsigned int la_filter_control;
volatile unsigned int la_filter_data;
volatile unsigned int la_filter_wildcard;
volatile unsigned int la_triggera_data;
volatile unsigned int la_triggera_wildcard;
volatile unsigned int la_triggerb_data;
volatile unsigned int la_triggerb_wildcard;
volatile unsigned int la_trigger;
volatile unsigned int la_fifo;
volatile unsigned int la[2];
volatile unsigned int ant_pin;
volatile unsigned int antd_pin;
volatile unsigned int gpio_pin;
volatile unsigned int gpio_h_pin;
volatile unsigned int bt_pin;
volatile unsigned int bt_wlan_pin;
volatile unsigned int si_uart_pin;
volatile unsigned int clk32k_pin;
volatile unsigned int reset_tuple_status;
} gpio_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _GPIO_REG_H_ */

386
drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_host_reg.h Normal file
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#ifndef _MBOX_HOST_REG_REG_H_
#define _MBOX_HOST_REG_REG_H_
#define HOST_INT_STATUS_ADDRESS 0x00000400
#define HOST_INT_STATUS_OFFSET 0x00000400
#define HOST_INT_STATUS_ERROR_MSB 7
#define HOST_INT_STATUS_ERROR_LSB 7
#define HOST_INT_STATUS_ERROR_MASK 0x00000080
#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_CPU_MSB 6
#define HOST_INT_STATUS_CPU_LSB 6
#define HOST_INT_STATUS_CPU_MASK 0x00000040
#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_DRAGON_INT_MSB 5
#define HOST_INT_STATUS_DRAGON_INT_LSB 5
#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
#define HOST_INT_STATUS_COUNTER_MSB 4
#define HOST_INT_STATUS_COUNTER_LSB 4
#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_MBOX_DATA_MSB 3
#define HOST_INT_STATUS_MBOX_DATA_LSB 0
#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ADDRESS 0x00000401
#define CPU_INT_STATUS_OFFSET 0x00000401
#define CPU_INT_STATUS_BIT_MSB 7
#define CPU_INT_STATUS_BIT_LSB 0
#define CPU_INT_STATUS_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
#define ERROR_INT_STATUS_ADDRESS 0x00000402
#define ERROR_INT_STATUS_OFFSET 0x00000402
#define ERROR_INT_STATUS_SPI_MSB 3
#define ERROR_INT_STATUS_SPI_LSB 3
#define ERROR_INT_STATUS_SPI_MASK 0x00000008
#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
#define ERROR_INT_STATUS_WAKEUP_MSB 2
#define ERROR_INT_STATUS_WAKEUP_LSB 2
#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ADDRESS 0x00000403
#define COUNTER_INT_STATUS_OFFSET 0x00000403
#define COUNTER_INT_STATUS_COUNTER_MSB 7
#define COUNTER_INT_STATUS_COUNTER_LSB 0
#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
#define MBOX_FRAME_ADDRESS 0x00000404
#define MBOX_FRAME_OFFSET 0x00000404
#define MBOX_FRAME_RX_EOM_MSB 7
#define MBOX_FRAME_RX_EOM_LSB 4
#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
#define MBOX_FRAME_RX_SOM_MSB 3
#define MBOX_FRAME_RX_SOM_LSB 0
#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
#define RX_LOOKAHEAD0_ADDRESS 0x00000408
#define RX_LOOKAHEAD0_OFFSET 0x00000408
#define RX_LOOKAHEAD0_DATA_MSB 7
#define RX_LOOKAHEAD0_DATA_LSB 0
#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
#define RX_LOOKAHEAD1_OFFSET 0x0000040c
#define RX_LOOKAHEAD1_DATA_MSB 7
#define RX_LOOKAHEAD1_DATA_LSB 0
#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
#define RX_LOOKAHEAD2_ADDRESS 0x00000410
#define RX_LOOKAHEAD2_OFFSET 0x00000410
#define RX_LOOKAHEAD2_DATA_MSB 7
#define RX_LOOKAHEAD2_DATA_LSB 0
#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
#define RX_LOOKAHEAD3_ADDRESS 0x00000414
#define RX_LOOKAHEAD3_OFFSET 0x00000414
#define RX_LOOKAHEAD3_DATA_MSB 7
#define RX_LOOKAHEAD3_DATA_LSB 0
#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
#define INT_STATUS_ENABLE_ADDRESS 0x00000418
#define INT_STATUS_ENABLE_OFFSET 0x00000418
#define INT_STATUS_ENABLE_ERROR_MSB 7
#define INT_STATUS_ENABLE_ERROR_LSB 7
#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_MSB 6
#define INT_STATUS_ENABLE_CPU_LSB 6
#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
#define INT_STATUS_ENABLE_COUNTER_MSB 4
#define INT_STATUS_ENABLE_COUNTER_LSB 4
#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define COUNT_ADDRESS 0x00000420
#define COUNT_OFFSET 0x00000420
#define COUNT_VALUE_MSB 7
#define COUNT_VALUE_LSB 0
#define COUNT_VALUE_MASK 0x000000ff
#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
#define COUNT_DEC_ADDRESS 0x00000440
#define COUNT_DEC_OFFSET 0x00000440
#define COUNT_DEC_VALUE_MSB 7
#define COUNT_DEC_VALUE_LSB 0
#define COUNT_DEC_VALUE_MASK 0x000000ff
#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
#define SCRATCH_ADDRESS 0x00000460
#define SCRATCH_OFFSET 0x00000460
#define SCRATCH_VALUE_MSB 7
#define SCRATCH_VALUE_LSB 0
#define SCRATCH_VALUE_MASK 0x000000ff
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
#define FIFO_TIMEOUT_ADDRESS 0x00000468
#define FIFO_TIMEOUT_OFFSET 0x00000468
#define FIFO_TIMEOUT_VALUE_MSB 7
#define FIFO_TIMEOUT_VALUE_LSB 0
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
#define DISABLE_SLEEP_ADDRESS 0x0000046a
#define DISABLE_SLEEP_OFFSET 0x0000046a
#define DISABLE_SLEEP_FOR_INT_MSB 1
#define DISABLE_SLEEP_FOR_INT_LSB 1
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
#define DISABLE_SLEEP_ON_MSB 0
#define DISABLE_SLEEP_ON_LSB 0
#define DISABLE_SLEEP_ON_MASK 0x00000001
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
#define LOCAL_BUS_ADDRESS 0x00000470
#define LOCAL_BUS_OFFSET 0x00000470
#define LOCAL_BUS_STATE_MSB 1
#define LOCAL_BUS_STATE_LSB 0
#define LOCAL_BUS_STATE_MASK 0x00000003
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
#define INT_WLAN_ADDRESS 0x00000472
#define INT_WLAN_OFFSET 0x00000472
#define INT_WLAN_VECTOR_MSB 7
#define INT_WLAN_VECTOR_LSB 0
#define INT_WLAN_VECTOR_MASK 0x000000ff
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
#define WINDOW_DATA_ADDRESS 0x00000474
#define WINDOW_DATA_OFFSET 0x00000474
#define WINDOW_DATA_DATA_MSB 7
#define WINDOW_DATA_DATA_LSB 0
#define WINDOW_DATA_DATA_MASK 0x000000ff
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
#define WINDOW_READ_ADDR_ADDR_MSB 7
#define WINDOW_READ_ADDR_ADDR_LSB 0
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
#define SPI_CONFIG_ADDRESS 0x00000480
#define SPI_CONFIG_OFFSET 0x00000480
#define SPI_CONFIG_SPI_RESET_MSB 4
#define SPI_CONFIG_SPI_RESET_LSB 4
#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
#define SPI_CONFIG_TEST_MODE_MSB 2
#define SPI_CONFIG_TEST_MODE_LSB 2
#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
#define SPI_CONFIG_DATA_SIZE_MSB 1
#define SPI_CONFIG_DATA_SIZE_LSB 0
#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
#define SPI_STATUS_ADDRESS 0x00000481
#define SPI_STATUS_OFFSET 0x00000481
#define SPI_STATUS_ADDR_ERR_MSB 3
#define SPI_STATUS_ADDR_ERR_LSB 3
#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
#define SPI_STATUS_RD_ERR_MSB 2
#define SPI_STATUS_RD_ERR_LSB 2
#define SPI_STATUS_RD_ERR_MASK 0x00000004
#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
#define SPI_STATUS_WR_ERR_MSB 1
#define SPI_STATUS_WR_ERR_LSB 1
#define SPI_STATUS_WR_ERR_MASK 0x00000002
#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
#define SPI_STATUS_READY_MSB 0
#define SPI_STATUS_READY_LSB 0
#define SPI_STATUS_READY_MASK 0x00000001
#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
#define CIS_WINDOW_ADDRESS 0x00000600
#define CIS_WINDOW_OFFSET 0x00000600
#define CIS_WINDOW_DATA_MSB 7
#define CIS_WINDOW_DATA_LSB 0
#define CIS_WINDOW_DATA_MASK 0x000000ff
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_host_reg_reg_s {
unsigned char pad0[1024]; /* pad to 0x400 */
volatile unsigned char host_int_status;
volatile unsigned char cpu_int_status;
volatile unsigned char error_int_status;
volatile unsigned char counter_int_status;
volatile unsigned char mbox_frame;
volatile unsigned char rx_lookahead_valid;
unsigned char pad1[2]; /* pad to 0x408 */
volatile unsigned char rx_lookahead0[4];
volatile unsigned char rx_lookahead1[4];
volatile unsigned char rx_lookahead2[4];
volatile unsigned char rx_lookahead3[4];
volatile unsigned char int_status_enable;
volatile unsigned char cpu_int_status_enable;
volatile unsigned char error_status_enable;
volatile unsigned char counter_int_status_enable;
unsigned char pad2[4]; /* pad to 0x420 */
volatile unsigned char count[8];
unsigned char pad3[24]; /* pad to 0x440 */
volatile unsigned char count_dec[32];
volatile unsigned char scratch[8];
volatile unsigned char fifo_timeout;
volatile unsigned char fifo_timeout_enable;
volatile unsigned char disable_sleep;
unsigned char pad4[5]; /* pad to 0x470 */
volatile unsigned char local_bus;
unsigned char pad5[1]; /* pad to 0x472 */
volatile unsigned char int_wlan;
unsigned char pad6[1]; /* pad to 0x474 */
volatile unsigned char window_data[4];
volatile unsigned char window_write_addr[4];
volatile unsigned char window_read_addr[4];
volatile unsigned char spi_config;
volatile unsigned char spi_status;
volatile unsigned char non_assoc_sleep_en;
unsigned char pad7[381]; /* pad to 0x600 */
volatile unsigned char cis_window[512];
} mbox_host_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_HOST_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw.0/mbox_reg.h Normal file
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#ifndef _MBOX_REG_REG_H_
#define _MBOX_REG_REG_H_
#define MBOX_FIFO_ADDRESS 0x00000000
#define MBOX_FIFO_OFFSET 0x00000000
#define MBOX_FIFO_DATA_MSB 19
#define MBOX_FIFO_DATA_LSB 0
#define MBOX_FIFO_DATA_MASK 0x000fffff
#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
#define MBOX_FIFO_STATUS_ADDRESS 0x00000010
#define MBOX_FIFO_STATUS_OFFSET 0x00000010
#define MBOX_FIFO_STATUS_EMPTY_MSB 19
#define MBOX_FIFO_STATUS_EMPTY_LSB 16
#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
#define MBOX_FIFO_STATUS_FULL_MSB 15
#define MBOX_FIFO_STATUS_FULL_LSB 12
#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
#define MBOX_DMA_POLICY_ADDRESS 0x00000014
#define MBOX_DMA_POLICY_OFFSET 0x00000014
#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX0_DMA_RX_CONTROL_START_MSB 1
#define MBOX0_DMA_RX_CONTROL_START_LSB 1
#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX0_DMA_TX_CONTROL_START_MSB 1
#define MBOX0_DMA_TX_CONTROL_START_LSB 1
#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX1_DMA_RX_CONTROL_START_MSB 1
#define MBOX1_DMA_RX_CONTROL_START_LSB 1
#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX1_DMA_TX_CONTROL_START_MSB 1
#define MBOX1_DMA_TX_CONTROL_START_LSB 1
#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX2_DMA_RX_CONTROL_START_MSB 1
#define MBOX2_DMA_RX_CONTROL_START_LSB 1
#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX2_DMA_TX_CONTROL_START_MSB 1
#define MBOX2_DMA_TX_CONTROL_START_LSB 1
#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
#define MBOX3_DMA_RX_CONTROL_START_MSB 1
#define MBOX3_DMA_RX_CONTROL_START_LSB 1
#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
#define MBOX3_DMA_TX_CONTROL_START_MSB 1
#define MBOX3_DMA_TX_CONTROL_START_LSB 1
#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
#define MBOX_INT_STATUS_ADDRESS 0x00000058
#define MBOX_INT_STATUS_OFFSET 0x00000058
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define MBOX_INT_STATUS_HOST_MSB 7
#define MBOX_INT_STATUS_HOST_LSB 0
#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
#define MBOX_INT_ENABLE_ADDRESS 0x0000005c
#define MBOX_INT_ENABLE_OFFSET 0x0000005c
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define MBOX_INT_ENABLE_HOST_MSB 7
#define MBOX_INT_ENABLE_HOST_LSB 0
#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
#define INT_HOST_ADDRESS 0x00000060
#define INT_HOST_OFFSET 0x00000060
#define INT_HOST_VECTOR_MSB 7
#define INT_HOST_VECTOR_LSB 0
#define INT_HOST_VECTOR_MASK 0x000000ff
#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
#define LOCAL_COUNT_ADDRESS 0x00000080
#define LOCAL_COUNT_OFFSET 0x00000080
#define LOCAL_COUNT_VALUE_MSB 7
#define LOCAL_COUNT_VALUE_LSB 0
#define LOCAL_COUNT_VALUE_MASK 0x000000ff
#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
#define COUNT_INC_ADDRESS 0x000000a0
#define COUNT_INC_OFFSET 0x000000a0
#define COUNT_INC_VALUE_MSB 7
#define COUNT_INC_VALUE_LSB 0
#define COUNT_INC_VALUE_MASK 0x000000ff
#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
#define LOCAL_SCRATCH_ADDRESS 0x000000c0
#define LOCAL_SCRATCH_OFFSET 0x000000c0
#define LOCAL_SCRATCH_VALUE_MSB 7
#define LOCAL_SCRATCH_VALUE_LSB 0
#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
#define USE_LOCAL_BUS_ADDRESS 0x000000e0
#define USE_LOCAL_BUS_OFFSET 0x000000e0
#define USE_LOCAL_BUS_PIN_INIT_MSB 0
#define USE_LOCAL_BUS_PIN_INIT_LSB 0
#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
#define SDIO_CONFIG_ADDRESS 0x000000e4
#define SDIO_CONFIG_OFFSET 0x000000e4
#define SDIO_CONFIG_CCCR_IOR1_MSB 0
#define SDIO_CONFIG_CCCR_IOR1_LSB 0
#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
#define MBOX_DEBUG_ADDRESS 0x000000e8
#define MBOX_DEBUG_OFFSET 0x000000e8
#define MBOX_DEBUG_SEL_MSB 2
#define MBOX_DEBUG_SEL_LSB 0
#define MBOX_DEBUG_SEL_MASK 0x00000007
#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
#define MBOX_FIFO_RESET_ADDRESS 0x000000ec
#define MBOX_FIFO_RESET_OFFSET 0x000000ec
#define MBOX_FIFO_RESET_INIT_MSB 0
#define MBOX_FIFO_RESET_INIT_LSB 0
#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
#define MBOX_TXFIFO_POP_OFFSET 0x000000f0
#define MBOX_TXFIFO_POP_DATA_MSB 0
#define MBOX_TXFIFO_POP_DATA_LSB 0
#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
#define MBOX_RXFIFO_POP_ADDRESS 0x00000100
#define MBOX_RXFIFO_POP_OFFSET 0x00000100
#define MBOX_RXFIFO_POP_DATA_MSB 0
#define MBOX_RXFIFO_POP_DATA_LSB 0
#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
#define SDIO_DEBUG_ADDRESS 0x00000110
#define SDIO_DEBUG_OFFSET 0x00000110
#define SDIO_DEBUG_SEL_MSB 3
#define SDIO_DEBUG_SEL_LSB 0
#define SDIO_DEBUG_SEL_MASK 0x0000000f
#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
#define HOST_IF_WINDOW_ADDRESS 0x00002000
#define HOST_IF_WINDOW_OFFSET 0x00002000
#define HOST_IF_WINDOW_DATA_MSB 7
#define HOST_IF_WINDOW_DATA_LSB 0
#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_reg_reg_s {
volatile unsigned int mbox_fifo[4];
volatile unsigned int mbox_fifo_status;
volatile unsigned int mbox_dma_policy;
volatile unsigned int mbox0_dma_rx_descriptor_base;
volatile unsigned int mbox0_dma_rx_control;
volatile unsigned int mbox0_dma_tx_descriptor_base;
volatile unsigned int mbox0_dma_tx_control;
volatile unsigned int mbox1_dma_rx_descriptor_base;
volatile unsigned int mbox1_dma_rx_control;
volatile unsigned int mbox1_dma_tx_descriptor_base;
volatile unsigned int mbox1_dma_tx_control;
volatile unsigned int mbox2_dma_rx_descriptor_base;
volatile unsigned int mbox2_dma_rx_control;
volatile unsigned int mbox2_dma_tx_descriptor_base;
volatile unsigned int mbox2_dma_tx_control;
volatile unsigned int mbox3_dma_rx_descriptor_base;
volatile unsigned int mbox3_dma_rx_control;
volatile unsigned int mbox3_dma_tx_descriptor_base;
volatile unsigned int mbox3_dma_tx_control;
volatile unsigned int mbox_int_status;
volatile unsigned int mbox_int_enable;
volatile unsigned int int_host;
unsigned char pad0[28]; /* pad to 0x80 */
volatile unsigned int local_count[8];
volatile unsigned int count_inc[8];
volatile unsigned int local_scratch[8];
volatile unsigned int use_local_bus;
volatile unsigned int sdio_config;
volatile unsigned int mbox_debug;
volatile unsigned int mbox_fifo_reset;
volatile unsigned int mbox_txfifo_pop[4];
volatile unsigned int mbox_rxfifo_pop[4];
volatile unsigned int sdio_debug;
unsigned char pad1[7916]; /* pad to 0x2000 */
volatile unsigned int host_if_window[2048];
} mbox_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw.0/rtc_reg.h Normal file
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#ifndef _SI_REG_REG_H_
#define _SI_REG_REG_H_
#define SI_CONFIG_ADDRESS 0x00000000
#define SI_CONFIG_OFFSET 0x00000000
#define SI_CONFIG_ERR_INT_MSB 19
#define SI_CONFIG_ERR_INT_LSB 19
#define SI_CONFIG_ERR_INT_MASK 0x00080000
#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_MSB 16
#define SI_CONFIG_I2C_LSB 16
#define SI_CONFIG_I2C_MASK 0x00010000
#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_MSB 7
#define SI_CONFIG_POS_SAMPLE_LSB 7
#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_POS_DRIVE_MSB 6
#define SI_CONFIG_POS_DRIVE_LSB 6
#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
#define SI_CONFIG_INACTIVE_DATA_MSB 5
#define SI_CONFIG_INACTIVE_DATA_LSB 5
#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_INACTIVE_CLK_MSB 4
#define SI_CONFIG_INACTIVE_CLK_LSB 4
#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_DIVIDER_MSB 3
#define SI_CONFIG_DIVIDER_LSB 0
#define SI_CONFIG_DIVIDER_MASK 0x0000000f
#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_ADDRESS 0x00000004
#define SI_CS_OFFSET 0x00000004
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
#define SI_CS_DONE_ERR_MSB 10
#define SI_CS_DONE_ERR_LSB 10
#define SI_CS_DONE_ERR_MASK 0x00000400
#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MSB 9
#define SI_CS_DONE_INT_LSB 9
#define SI_CS_DONE_INT_MASK 0x00000200
#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
#define SI_CS_START_MSB 8
#define SI_CS_START_LSB 8
#define SI_CS_START_MASK 0x00000100
#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_MSB 7
#define SI_CS_RX_CNT_LSB 4
#define SI_CS_RX_CNT_MASK 0x000000f0
#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_MSB 3
#define SI_CS_TX_CNT_LSB 0
#define SI_CS_TX_CNT_MASK 0x0000000f
#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define SI_TX_DATA0_ADDRESS 0x00000008
#define SI_TX_DATA0_OFFSET 0x00000008
#define SI_TX_DATA0_DATA3_MSB 31
#define SI_TX_DATA0_DATA3_LSB 24
#define SI_TX_DATA0_DATA3_MASK 0xff000000
#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
#define SI_TX_DATA0_DATA2_MSB 23
#define SI_TX_DATA0_DATA2_LSB 16
#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
#define SI_TX_DATA0_DATA1_MSB 15
#define SI_TX_DATA0_DATA1_LSB 8
#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
#define SI_TX_DATA0_DATA0_MSB 7
#define SI_TX_DATA0_DATA0_LSB 0
#define SI_TX_DATA0_DATA0_MASK 0x000000ff
#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
#define SI_TX_DATA1_ADDRESS 0x0000000c
#define SI_TX_DATA1_OFFSET 0x0000000c
#define SI_TX_DATA1_DATA7_MSB 31
#define SI_TX_DATA1_DATA7_LSB 24
#define SI_TX_DATA1_DATA7_MASK 0xff000000
#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
#define SI_TX_DATA1_DATA6_MSB 23
#define SI_TX_DATA1_DATA6_LSB 16
#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
#define SI_TX_DATA1_DATA5_MSB 15
#define SI_TX_DATA1_DATA5_LSB 8
#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
#define SI_TX_DATA1_DATA4_MSB 7
#define SI_TX_DATA1_DATA4_LSB 0
#define SI_TX_DATA1_DATA4_MASK 0x000000ff
#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
#define SI_RX_DATA0_ADDRESS 0x00000010
#define SI_RX_DATA0_OFFSET 0x00000010
#define SI_RX_DATA0_DATA3_MSB 31
#define SI_RX_DATA0_DATA3_LSB 24
#define SI_RX_DATA0_DATA3_MASK 0xff000000
#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
#define SI_RX_DATA0_DATA2_MSB 23
#define SI_RX_DATA0_DATA2_LSB 16
#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
#define SI_RX_DATA0_DATA1_MSB 15
#define SI_RX_DATA0_DATA1_LSB 8
#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
#define SI_RX_DATA0_DATA0_MSB 7
#define SI_RX_DATA0_DATA0_LSB 0
#define SI_RX_DATA0_DATA0_MASK 0x000000ff
#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
#define SI_RX_DATA1_ADDRESS 0x00000014
#define SI_RX_DATA1_OFFSET 0x00000014
#define SI_RX_DATA1_DATA7_MSB 31
#define SI_RX_DATA1_DATA7_LSB 24
#define SI_RX_DATA1_DATA7_MASK 0xff000000
#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
#define SI_RX_DATA1_DATA6_MSB 23
#define SI_RX_DATA1_DATA6_LSB 16
#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
#define SI_RX_DATA1_DATA5_MSB 15
#define SI_RX_DATA1_DATA5_LSB 8
#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
#define SI_RX_DATA1_DATA4_MSB 7
#define SI_RX_DATA1_DATA4_LSB 0
#define SI_RX_DATA1_DATA4_MASK 0x000000ff
#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
#ifndef __ASSEMBLER__
typedef struct si_reg_reg_s {
volatile unsigned int si_config;
volatile unsigned int si_cs;
volatile unsigned int si_tx_data0;
volatile unsigned int si_tx_data1;
volatile unsigned int si_rx_data0;
volatile unsigned int si_rx_data1;
} si_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _SI_REG_H_ */

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#ifndef _UART_REG_REG_H_
#define _UART_REG_REG_H_
#define RBR_ADDRESS 0x00000000
#define RBR_OFFSET 0x00000000
#define RBR_RBR_MSB 7
#define RBR_RBR_LSB 0
#define RBR_RBR_MASK 0x000000ff
#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
#define THR_ADDRESS 0x00000000
#define THR_OFFSET 0x00000000
#define THR_THR_MSB 7
#define THR_THR_LSB 0
#define THR_THR_MASK 0x000000ff
#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
#define DLL_ADDRESS 0x00000000
#define DLL_OFFSET 0x00000000
#define DLL_DLL_MSB 7
#define DLL_DLL_LSB 0
#define DLL_DLL_MASK 0x000000ff
#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
#define DLH_ADDRESS 0x00000004
#define DLH_OFFSET 0x00000004
#define DLH_DLH_MSB 7
#define DLH_DLH_LSB 0
#define DLH_DLH_MASK 0x000000ff
#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
#define IER_ADDRESS 0x00000004
#define IER_OFFSET 0x00000004
#define IER_EDDSI_MSB 3
#define IER_EDDSI_LSB 3
#define IER_EDDSI_MASK 0x00000008
#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
#define IER_ELSI_MSB 2
#define IER_ELSI_LSB 2
#define IER_ELSI_MASK 0x00000004
#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
#define IER_ETBEI_MSB 1
#define IER_ETBEI_LSB 1
#define IER_ETBEI_MASK 0x00000002
#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
#define IER_ERBFI_MSB 0
#define IER_ERBFI_LSB 0
#define IER_ERBFI_MASK 0x00000001
#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
#define IIR_ADDRESS 0x00000008
#define IIR_OFFSET 0x00000008
#define IIR_FIFO_STATUS_MSB 7
#define IIR_FIFO_STATUS_LSB 6
#define IIR_FIFO_STATUS_MASK 0x000000c0
#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
#define IIR_IID_MSB 3
#define IIR_IID_LSB 0
#define IIR_IID_MASK 0x0000000f
#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
#define FCR_ADDRESS 0x00000008
#define FCR_OFFSET 0x00000008
#define FCR_RCVR_TRIG_MSB 7
#define FCR_RCVR_TRIG_LSB 6
#define FCR_RCVR_TRIG_MASK 0x000000c0
#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
#define FCR_DMA_MODE_MSB 3
#define FCR_DMA_MODE_LSB 3
#define FCR_DMA_MODE_MASK 0x00000008
#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
#define FCR_XMIT_FIFO_RST_MSB 2
#define FCR_XMIT_FIFO_RST_LSB 2
#define FCR_XMIT_FIFO_RST_MASK 0x00000004
#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
#define FCR_RCVR_FIFO_RST_MSB 1
#define FCR_RCVR_FIFO_RST_LSB 1
#define FCR_RCVR_FIFO_RST_MASK 0x00000002
#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
#define FCR_FIFO_EN_MSB 0
#define FCR_FIFO_EN_LSB 0
#define FCR_FIFO_EN_MASK 0x00000001
#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
#define LCR_ADDRESS 0x0000000c
#define LCR_OFFSET 0x0000000c
#define LCR_DLAB_MSB 7
#define LCR_DLAB_LSB 7
#define LCR_DLAB_MASK 0x00000080
#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
#define LCR_BREAK_MSB 6
#define LCR_BREAK_LSB 6
#define LCR_BREAK_MASK 0x00000040
#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
#define LCR_EPS_MSB 4
#define LCR_EPS_LSB 4
#define LCR_EPS_MASK 0x00000010
#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
#define LCR_PEN_MSB 3
#define LCR_PEN_LSB 3
#define LCR_PEN_MASK 0x00000008
#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
#define LCR_STOP_MSB 2
#define LCR_STOP_LSB 2
#define LCR_STOP_MASK 0x00000004
#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
#define LCR_CLS_MSB 1
#define LCR_CLS_LSB 0
#define LCR_CLS_MASK 0x00000003
#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
#define MCR_ADDRESS 0x00000010
#define MCR_OFFSET 0x00000010
#define MCR_LOOPBACK_MSB 5
#define MCR_LOOPBACK_LSB 5
#define MCR_LOOPBACK_MASK 0x00000020
#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
#define MCR_OUT2_MSB 3
#define MCR_OUT2_LSB 3
#define MCR_OUT2_MASK 0x00000008
#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
#define MCR_OUT1_MSB 2
#define MCR_OUT1_LSB 2
#define MCR_OUT1_MASK 0x00000004
#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
#define MCR_RTS_MSB 1
#define MCR_RTS_LSB 1
#define MCR_RTS_MASK 0x00000002
#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
#define MCR_DTR_MSB 0
#define MCR_DTR_LSB 0
#define MCR_DTR_MASK 0x00000001
#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
#define LSR_ADDRESS 0x00000014
#define LSR_OFFSET 0x00000014
#define LSR_FERR_MSB 7
#define LSR_FERR_LSB 7
#define LSR_FERR_MASK 0x00000080
#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
#define LSR_TEMT_MSB 6
#define LSR_TEMT_LSB 6
#define LSR_TEMT_MASK 0x00000040
#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
#define LSR_THRE_MSB 5
#define LSR_THRE_LSB 5
#define LSR_THRE_MASK 0x00000020
#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
#define LSR_BI_MSB 4
#define LSR_BI_LSB 4
#define LSR_BI_MASK 0x00000010
#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
#define LSR_FE_MSB 3
#define LSR_FE_LSB 3
#define LSR_FE_MASK 0x00000008
#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
#define LSR_PE_MSB 2
#define LSR_PE_LSB 2
#define LSR_PE_MASK 0x00000004
#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
#define LSR_OE_MSB 1
#define LSR_OE_LSB 1
#define LSR_OE_MASK 0x00000002
#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
#define LSR_DR_MSB 0
#define LSR_DR_LSB 0
#define LSR_DR_MASK 0x00000001
#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
#define MSR_ADDRESS 0x00000018
#define MSR_OFFSET 0x00000018
#define MSR_DCD_MSB 7
#define MSR_DCD_LSB 7
#define MSR_DCD_MASK 0x00000080
#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
#define MSR_RI_MSB 6
#define MSR_RI_LSB 6
#define MSR_RI_MASK 0x00000040
#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
#define MSR_DSR_MSB 5
#define MSR_DSR_LSB 5
#define MSR_DSR_MASK 0x00000020
#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
#define MSR_CTS_MSB 4
#define MSR_CTS_LSB 4
#define MSR_CTS_MASK 0x00000010
#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
#define MSR_DDCD_MSB 3
#define MSR_DDCD_LSB 3
#define MSR_DDCD_MASK 0x00000008
#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
#define MSR_TERI_MSB 2
#define MSR_TERI_LSB 2
#define MSR_TERI_MASK 0x00000004
#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
#define MSR_DDSR_MSB 1
#define MSR_DDSR_LSB 1
#define MSR_DDSR_MASK 0x00000002
#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
#define MSR_DCTS_MSB 0
#define MSR_DCTS_LSB 0
#define MSR_DCTS_MASK 0x00000001
#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
#define SCR_ADDRESS 0x0000001c
#define SCR_OFFSET 0x0000001c
#define SCR_SCR_MSB 7
#define SCR_SCR_LSB 0
#define SCR_SCR_MASK 0x000000ff
#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
#define SRBR_ADDRESS 0x00000020
#define SRBR_OFFSET 0x00000020
#define SRBR_SRBR_MSB 7
#define SRBR_SRBR_LSB 0
#define SRBR_SRBR_MASK 0x000000ff
#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
#define SIIR_ADDRESS 0x00000028
#define SIIR_OFFSET 0x00000028
#define SIIR_SIIR_MSB 7
#define SIIR_SIIR_LSB 0
#define SIIR_SIIR_MASK 0x000000ff
#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
#define MWR_ADDRESS 0x0000002c
#define MWR_OFFSET 0x0000002c
#define MWR_MWR_MSB 31
#define MWR_MWR_LSB 0
#define MWR_MWR_MASK 0xffffffff
#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
#define SLSR_ADDRESS 0x00000034
#define SLSR_OFFSET 0x00000034
#define SLSR_SLSR_MSB 7
#define SLSR_SLSR_LSB 0
#define SLSR_SLSR_MASK 0x000000ff
#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
#define SMSR_ADDRESS 0x00000038
#define SMSR_OFFSET 0x00000038
#define SMSR_SMSR_MSB 7
#define SMSR_SMSR_LSB 0
#define SMSR_SMSR_MASK 0x000000ff
#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
#define MRR_ADDRESS 0x0000003c
#define MRR_OFFSET 0x0000003c
#define MRR_MRR_MSB 31
#define MRR_MRR_LSB 0
#define MRR_MRR_MASK 0xffffffff
#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
#ifndef __ASSEMBLER__
typedef struct uart_reg_reg_s {
volatile unsigned int rbr;
volatile unsigned int dlh;
volatile unsigned int iir;
volatile unsigned int lcr;
volatile unsigned int mcr;
volatile unsigned int lsr;
volatile unsigned int msr;
volatile unsigned int scr;
volatile unsigned int srbr;
unsigned char pad0[4]; /* pad to 0x28 */
volatile unsigned int siir;
volatile unsigned int mwr;
unsigned char pad1[4]; /* pad to 0x34 */
volatile unsigned int slsr;
volatile unsigned int smsr;
volatile unsigned int mrr;
} uart_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UART_REG_H_ */

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#ifndef _VMC_REG_REG_H_
#define _VMC_REG_REG_H_
#define MC_TCAM_VALID_ADDRESS 0x00000000
#define MC_TCAM_VALID_OFFSET 0x00000000
#define MC_TCAM_VALID_BIT_MSB 0
#define MC_TCAM_VALID_BIT_LSB 0
#define MC_TCAM_VALID_BIT_MASK 0x00000001
#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
#define MC_TCAM_MASK_ADDRESS 0x00000080
#define MC_TCAM_MASK_OFFSET 0x00000080
#define MC_TCAM_MASK_SIZE_MSB 2
#define MC_TCAM_MASK_SIZE_LSB 0
#define MC_TCAM_MASK_SIZE_MASK 0x00000007
#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
#define MC_TCAM_COMPARE_ADDRESS 0x00000100
#define MC_TCAM_COMPARE_OFFSET 0x00000100
#define MC_TCAM_COMPARE_KEY_MSB 21
#define MC_TCAM_COMPARE_KEY_LSB 5
#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
#define MC_TCAM_TARGET_ADDRESS 0x00000180
#define MC_TCAM_TARGET_OFFSET 0x00000180
#define MC_TCAM_TARGET_ADDR_MSB 21
#define MC_TCAM_TARGET_ADDR_LSB 5
#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
#define ADDR_ERROR_CONTROL_OFFSET 0x00000200
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
#define ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
#define ADDR_ERROR_STATUS_ADDRESS 0x00000204
#define ADDR_ERROR_STATUS_OFFSET 0x00000204
#define ADDR_ERROR_STATUS_WRITE_MSB 25
#define ADDR_ERROR_STATUS_WRITE_LSB 25
#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
#define ADDR_ERROR_STATUS_ADDRESS_MSB 24
#define ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
#ifndef __ASSEMBLER__
typedef struct vmc_reg_reg_s {
volatile unsigned int mc_tcam_valid[32];
volatile unsigned int mc_tcam_mask[32];
volatile unsigned int mc_tcam_compare[32];
volatile unsigned int mc_tcam_target[32];
volatile unsigned int addr_error_control;
volatile unsigned int addr_error_status;
} vmc_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _VMC_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "analog_intf_athr_wlan_reg.h"
#ifndef BT_HEADERS
#endif
#endif

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _APB_ATHR_WLAN_MAP_H_
#define _APB_ATHR_WLAN_MAP_H_
#define WLAN_RTC_BASE_ADDRESS 0x00004000
#define WLAN_VMC_BASE_ADDRESS 0x00008000
#define WLAN_UART_BASE_ADDRESS 0x0000c000
#define WLAN_DBG_UART_BASE_ADDRESS 0x0000d000
#define WLAN_UMBOX_BASE_ADDRESS 0x0000e000
#define WLAN_SI_BASE_ADDRESS 0x00010000
#define WLAN_GPIO_BASE_ADDRESS 0x00014000
#define WLAN_MBOX_BASE_ADDRESS 0x00018000
#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
#define WLAN_MAC_BASE_ADDRESS 0x00020000
#define WLAN_RDMA_BASE_ADDRESS 0x00030100
#define EFUSE_BASE_ADDRESS 0x00031000
#endif /* _APB_ATHR_WLAN_MAP_REG_H_ */

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "apb_athr_wlan_map.h"
#ifndef BT_HEADERS
#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
#define VMC_BASE_ADDRESS WLAN_VMC_BASE_ADDRESS
#define UART_BASE_ADDRESS WLAN_UART_BASE_ADDRESS
#define DBG_UART_BASE_ADDRESS WLAN_DBG_UART_BASE_ADDRESS
#define UMBOX_BASE_ADDRESS WLAN_UMBOX_BASE_ADDRESS
#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
#define MBOX_BASE_ADDRESS WLAN_MBOX_BASE_ADDRESS
#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
#endif
#endif

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _EFUSE_REG_REG_H_
#define _EFUSE_REG_REG_H_
#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
#define EFUSE_WR_ENABLE_REG_V_MSB 0
#define EFUSE_WR_ENABLE_REG_V_LSB 0
#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
#define EFUSE_INT_ENABLE_REG_V_MSB 0
#define EFUSE_INT_ENABLE_REG_V_LSB 0
#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
#define EFUSE_INT_STATUS_REG_V_MSB 0
#define EFUSE_INT_STATUS_REG_V_LSB 0
#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
#define BITMASK_WR_REG_ADDRESS 0x0000000c
#define BITMASK_WR_REG_OFFSET 0x0000000c
#define BITMASK_WR_REG_V_MSB 31
#define BITMASK_WR_REG_V_LSB 0
#define BITMASK_WR_REG_V_MASK 0xffffffff
#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
#define VDDQ_SETTLE_TIME_REG_V_MSB 31
#define VDDQ_SETTLE_TIME_REG_V_LSB 0
#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
#define RD_STROBE_PW_REG_ADDRESS 0x00000014
#define RD_STROBE_PW_REG_OFFSET 0x00000014
#define RD_STROBE_PW_REG_V_MSB 31
#define RD_STROBE_PW_REG_V_LSB 0
#define RD_STROBE_PW_REG_V_MASK 0xffffffff
#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
#define PG_STROBE_PW_REG_ADDRESS 0x00000018
#define PG_STROBE_PW_REG_OFFSET 0x00000018
#define PG_STROBE_PW_REG_V_MSB 31
#define PG_STROBE_PW_REG_V_LSB 0
#define PG_STROBE_PW_REG_V_MASK 0xffffffff
#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
#define EFUSE_INTF_ADDRESS 0x00000800
#define EFUSE_INTF_OFFSET 0x00000800
#define EFUSE_INTF_R_MSB 31
#define EFUSE_INTF_R_LSB 0
#define EFUSE_INTF_R_MASK 0xffffffff
#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
#ifndef __ASSEMBLER__
typedef struct efuse_reg_reg_s {
volatile unsigned int efuse_wr_enable_reg;
volatile unsigned int efuse_int_enable_reg;
volatile unsigned int efuse_int_status_reg;
volatile unsigned int bitmask_wr_reg;
volatile unsigned int vddq_settle_time_reg;
volatile unsigned int rd_strobe_pw_reg;
volatile unsigned int pg_strobe_pw_reg;
unsigned char pad0[2020]; /* pad to 0x800 */
volatile unsigned int efuse_intf[512];
} efuse_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _EFUSE_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2002-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
/*****************************************************************************/
/* AR6003 WLAN MAC DMA register definitions */
/*****************************************************************************/
#ifndef _AR6000_DMAREG_H_
#define _AR6000_DMAREG_H_
/*
* Definitions for the Atheros AR6003 chipset.
*/
/* DMA Control and Interrupt Registers */
#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */
#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */
#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */
#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */
#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */
#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */
#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */
#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */
#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */
#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */
#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */
#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */
#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */
#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */
#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF
#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */
#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */
#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */
#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */
#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */
#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */
#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */
#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */
#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
#define MAC_DMA_FTRIG_64B 0x00000010 /* default */
#define MAC_DMA_FTRIG_128B 0x00000020
#define MAC_DMA_FTRIG_192B 0x00000030
#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */
#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */
#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */
#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */
#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */
#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */
#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */
#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */
#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */
#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */
#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */
#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
/* for which frame completions will cause */
/* a reset of the no frame xmit'd timeout */
#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */
#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */
#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */
#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */
#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */
#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */
/*
* Interrupt Status Registers
*
* Only the bits in the ISR_P register and the IMR_P registers
* control whether the MAC's INTA# output is asserted. The bits in
* the secondary interrupt status/mask registers control what bits
* are set in the primary interrupt status register; however the
* IMR_S* registers DO NOT determine whether INTA# is asserted.
* That is INTA# is asserted only when the logical AND of ISR_P
* and IMR_P is non-zero. The secondary interrupt mask/status
* registers affect what bits are set in ISR_P but they do not
* directly affect whether INTA# is asserted.
*/
#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */
#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */
#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */
#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */
#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */
#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */
#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */
#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */
#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_ISR_S2_CST_MASK 0x00400000
#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000
#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */
#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */
#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */
#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */
/*
* Interrupt Mask Registers
*
* Only the bits in the IMR control whether the MAC's INTA#
* output will be asserted. The bits in the secondary interrupt
* mask registers control what bits get set in the primary
* interrupt status register; however the IMR_S* registers
* DO NOT determine whether INTA# is asserted.
*/
#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */
#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */
#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */
#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */
#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */
#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */
#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/
#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */
#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0
#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */
#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16
#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */
#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0
#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */
#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16
#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */
#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0
#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800
#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000
#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000
#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000
#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000
#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000
#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
#define MAC_DMA_IMR_S2_CST_MASK 0x00400000
#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000
#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */
#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */
#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */
#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */
#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */
#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16
#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */
#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */
#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i))
#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000
#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */
/* Shadow copies with read-and-clear access */
#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */
#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */
#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */
#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */
#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */
#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */
#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */
#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */
#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */
/* QCU registers */
#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */
#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */
#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */
#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */
#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */
#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */
#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */
#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */
#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */
#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */
#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */
#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */
#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */
#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */
#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */
#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */
#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */
#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */
#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */
#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */
#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */
#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */
#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */
#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */
#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */
#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */
#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */
#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */
#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */
#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */
#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr
(empty q) */
#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr
(empty beacon q) */
#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */
#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */
#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */
#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */
#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */
#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */
#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */
#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */
#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */
/* DCU registers */
#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */
#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */
#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */
#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */
#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */
#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */
#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */
#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */
#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */
#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */
#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */
#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */
#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */
#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */
#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */
#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0
#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */
#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10
#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */
#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20
/*
* Note: even though this field is 8 bits wide the
* maximum supported AIFS value is 0xFc. Setting the AIFS value
* to 0xFd 0xFe, or 0xFf will not work correctly and will cause
* the DCU to hang.
*/
#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */
#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */
#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */
#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */
#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */
#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */
#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */
#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */
#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */
#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */
#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */
#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */
#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14
#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */
#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */
#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */
#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */
#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */
#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */
#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */
#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */
#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */
#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */
#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */
#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */
#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */
#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */
#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */
#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */
#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000
#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */
#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
#define MAC_DMA_D0_EOL_ADDRESS 0x00001180
#define MAC_DMA_D1_EOL_ADDRESS 0x00001184
#define MAC_DMA_D2_EOL_ADDRESS 0x00001188
#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C
#define MAC_DMA_D4_EOL_ADDRESS 0x00001190
#define MAC_DMA_D5_EOL_ADDRESS 0x00001194
#define MAC_DMA_D6_EOL_ADDRESS 0x00001198
#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C
#define MAC_DMA_D8_EOL_ADDRESS 0x00001200
#define MAC_DMA_D9_EOL_ADDRESS 0x00001204
#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */
#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0
#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series
station RTS/data failure
count reset policy */
#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series
CW reset policy */
#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */
#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */
#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */
#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor
setting */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision
handling policy */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/
#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */
#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */
#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */
#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */
#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */
#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */
#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */
#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */
#endif /* _AR6000_DMMAEG_H_ */

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "mbox_wlan_host_reg.h"
#ifndef BT_HEADERS
#endif
#endif

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "mbox_wlan_reg.h"
#ifndef BT_HEADERS
#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
#define MBOX_FIFO_OFFSET WLAN_MBOX_FIFO_OFFSET
#define MBOX_FIFO_DATA_MSB WLAN_MBOX_FIFO_DATA_MSB
#define MBOX_FIFO_DATA_LSB WLAN_MBOX_FIFO_DATA_LSB
#define MBOX_FIFO_DATA_MASK WLAN_MBOX_FIFO_DATA_MASK
#define MBOX_FIFO_DATA_GET(x) WLAN_MBOX_FIFO_DATA_GET(x)
#define MBOX_FIFO_DATA_SET(x) WLAN_MBOX_FIFO_DATA_SET(x)
#define MBOX_FIFO_STATUS_ADDRESS WLAN_MBOX_FIFO_STATUS_ADDRESS
#define MBOX_FIFO_STATUS_OFFSET WLAN_MBOX_FIFO_STATUS_OFFSET
#define MBOX_FIFO_STATUS_EMPTY_MSB WLAN_MBOX_FIFO_STATUS_EMPTY_MSB
#define MBOX_FIFO_STATUS_EMPTY_LSB WLAN_MBOX_FIFO_STATUS_EMPTY_LSB
#define MBOX_FIFO_STATUS_EMPTY_MASK WLAN_MBOX_FIFO_STATUS_EMPTY_MASK
#define MBOX_FIFO_STATUS_EMPTY_GET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x)
#define MBOX_FIFO_STATUS_EMPTY_SET(x) WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x)
#define MBOX_FIFO_STATUS_FULL_MSB WLAN_MBOX_FIFO_STATUS_FULL_MSB
#define MBOX_FIFO_STATUS_FULL_LSB WLAN_MBOX_FIFO_STATUS_FULL_LSB
#define MBOX_FIFO_STATUS_FULL_MASK WLAN_MBOX_FIFO_STATUS_FULL_MASK
#define MBOX_FIFO_STATUS_FULL_GET(x) WLAN_MBOX_FIFO_STATUS_FULL_GET(x)
#define MBOX_FIFO_STATUS_FULL_SET(x) WLAN_MBOX_FIFO_STATUS_FULL_SET(x)
#define MBOX_DMA_POLICY_ADDRESS WLAN_MBOX_DMA_POLICY_ADDRESS
#define MBOX_DMA_POLICY_OFFSET WLAN_MBOX_DMA_POLICY_OFFSET
#define MBOX_DMA_POLICY_TX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB
#define MBOX_DMA_POLICY_TX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB
#define MBOX_DMA_POLICY_TX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK
#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x)
#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x)
#define MBOX_DMA_POLICY_TX_ORDER_MSB WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB
#define MBOX_DMA_POLICY_TX_ORDER_LSB WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB
#define MBOX_DMA_POLICY_TX_ORDER_MASK WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK
#define MBOX_DMA_POLICY_TX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x)
#define MBOX_DMA_POLICY_TX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x)
#define MBOX_DMA_POLICY_RX_QUANTUM_MSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB
#define MBOX_DMA_POLICY_RX_QUANTUM_LSB WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB
#define MBOX_DMA_POLICY_RX_QUANTUM_MASK WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK
#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x)
#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x)
#define MBOX_DMA_POLICY_RX_ORDER_MSB WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB
#define MBOX_DMA_POLICY_RX_ORDER_LSB WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB
#define MBOX_DMA_POLICY_RX_ORDER_MASK WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK
#define MBOX_DMA_POLICY_RX_ORDER_GET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x)
#define MBOX_DMA_POLICY_RX_ORDER_SET(x) WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX0_DMA_RX_CONTROL_ADDRESS WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS
#define MBOX0_DMA_RX_CONTROL_OFFSET WLAN_MBOX0_DMA_RX_CONTROL_OFFSET
#define MBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB
#define MBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB
#define MBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK
#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX0_DMA_RX_CONTROL_START_MSB WLAN_MBOX0_DMA_RX_CONTROL_START_MSB
#define MBOX0_DMA_RX_CONTROL_START_LSB WLAN_MBOX0_DMA_RX_CONTROL_START_LSB
#define MBOX0_DMA_RX_CONTROL_START_MASK WLAN_MBOX0_DMA_RX_CONTROL_START_MASK
#define MBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x)
#define MBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x)
#define MBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB
#define MBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB
#define MBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK
#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX0_DMA_TX_CONTROL_ADDRESS WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS
#define MBOX0_DMA_TX_CONTROL_OFFSET WLAN_MBOX0_DMA_TX_CONTROL_OFFSET
#define MBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB
#define MBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB
#define MBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK
#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX0_DMA_TX_CONTROL_START_MSB WLAN_MBOX0_DMA_TX_CONTROL_START_MSB
#define MBOX0_DMA_TX_CONTROL_START_LSB WLAN_MBOX0_DMA_TX_CONTROL_START_LSB
#define MBOX0_DMA_TX_CONTROL_START_MASK WLAN_MBOX0_DMA_TX_CONTROL_START_MASK
#define MBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x)
#define MBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x)
#define MBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB
#define MBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB
#define MBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK
#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX1_DMA_RX_CONTROL_ADDRESS WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS
#define MBOX1_DMA_RX_CONTROL_OFFSET WLAN_MBOX1_DMA_RX_CONTROL_OFFSET
#define MBOX1_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB
#define MBOX1_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB
#define MBOX1_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK
#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX1_DMA_RX_CONTROL_START_MSB WLAN_MBOX1_DMA_RX_CONTROL_START_MSB
#define MBOX1_DMA_RX_CONTROL_START_LSB WLAN_MBOX1_DMA_RX_CONTROL_START_LSB
#define MBOX1_DMA_RX_CONTROL_START_MASK WLAN_MBOX1_DMA_RX_CONTROL_START_MASK
#define MBOX1_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x)
#define MBOX1_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x)
#define MBOX1_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB
#define MBOX1_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB
#define MBOX1_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK
#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX1_DMA_TX_CONTROL_ADDRESS WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS
#define MBOX1_DMA_TX_CONTROL_OFFSET WLAN_MBOX1_DMA_TX_CONTROL_OFFSET
#define MBOX1_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB
#define MBOX1_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB
#define MBOX1_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK
#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX1_DMA_TX_CONTROL_START_MSB WLAN_MBOX1_DMA_TX_CONTROL_START_MSB
#define MBOX1_DMA_TX_CONTROL_START_LSB WLAN_MBOX1_DMA_TX_CONTROL_START_LSB
#define MBOX1_DMA_TX_CONTROL_START_MASK WLAN_MBOX1_DMA_TX_CONTROL_START_MASK
#define MBOX1_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x)
#define MBOX1_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x)
#define MBOX1_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB
#define MBOX1_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB
#define MBOX1_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK
#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX2_DMA_RX_CONTROL_ADDRESS WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS
#define MBOX2_DMA_RX_CONTROL_OFFSET WLAN_MBOX2_DMA_RX_CONTROL_OFFSET
#define MBOX2_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB
#define MBOX2_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB
#define MBOX2_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK
#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX2_DMA_RX_CONTROL_START_MSB WLAN_MBOX2_DMA_RX_CONTROL_START_MSB
#define MBOX2_DMA_RX_CONTROL_START_LSB WLAN_MBOX2_DMA_RX_CONTROL_START_LSB
#define MBOX2_DMA_RX_CONTROL_START_MASK WLAN_MBOX2_DMA_RX_CONTROL_START_MASK
#define MBOX2_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x)
#define MBOX2_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x)
#define MBOX2_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB
#define MBOX2_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB
#define MBOX2_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK
#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX2_DMA_TX_CONTROL_ADDRESS WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS
#define MBOX2_DMA_TX_CONTROL_OFFSET WLAN_MBOX2_DMA_TX_CONTROL_OFFSET
#define MBOX2_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB
#define MBOX2_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB
#define MBOX2_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK
#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX2_DMA_TX_CONTROL_START_MSB WLAN_MBOX2_DMA_TX_CONTROL_START_MSB
#define MBOX2_DMA_TX_CONTROL_START_LSB WLAN_MBOX2_DMA_TX_CONTROL_START_LSB
#define MBOX2_DMA_TX_CONTROL_START_MASK WLAN_MBOX2_DMA_TX_CONTROL_START_MASK
#define MBOX2_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x)
#define MBOX2_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x)
#define MBOX2_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB
#define MBOX2_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB
#define MBOX2_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK
#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX3_DMA_RX_CONTROL_ADDRESS WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS
#define MBOX3_DMA_RX_CONTROL_OFFSET WLAN_MBOX3_DMA_RX_CONTROL_OFFSET
#define MBOX3_DMA_RX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB
#define MBOX3_DMA_RX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB
#define MBOX3_DMA_RX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK
#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x)
#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x)
#define MBOX3_DMA_RX_CONTROL_START_MSB WLAN_MBOX3_DMA_RX_CONTROL_START_MSB
#define MBOX3_DMA_RX_CONTROL_START_LSB WLAN_MBOX3_DMA_RX_CONTROL_START_LSB
#define MBOX3_DMA_RX_CONTROL_START_MASK WLAN_MBOX3_DMA_RX_CONTROL_START_MASK
#define MBOX3_DMA_RX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x)
#define MBOX3_DMA_RX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x)
#define MBOX3_DMA_RX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB
#define MBOX3_DMA_RX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB
#define MBOX3_DMA_RX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK
#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x)
#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define MBOX3_DMA_TX_CONTROL_ADDRESS WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS
#define MBOX3_DMA_TX_CONTROL_OFFSET WLAN_MBOX3_DMA_TX_CONTROL_OFFSET
#define MBOX3_DMA_TX_CONTROL_RESUME_MSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB
#define MBOX3_DMA_TX_CONTROL_RESUME_LSB WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB
#define MBOX3_DMA_TX_CONTROL_RESUME_MASK WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK
#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x)
#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x)
#define MBOX3_DMA_TX_CONTROL_START_MSB WLAN_MBOX3_DMA_TX_CONTROL_START_MSB
#define MBOX3_DMA_TX_CONTROL_START_LSB WLAN_MBOX3_DMA_TX_CONTROL_START_LSB
#define MBOX3_DMA_TX_CONTROL_START_MASK WLAN_MBOX3_DMA_TX_CONTROL_START_MASK
#define MBOX3_DMA_TX_CONTROL_START_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x)
#define MBOX3_DMA_TX_CONTROL_START_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x)
#define MBOX3_DMA_TX_CONTROL_STOP_MSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB
#define MBOX3_DMA_TX_CONTROL_STOP_LSB WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB
#define MBOX3_DMA_TX_CONTROL_STOP_MASK WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK
#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x)
#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x)
#define MBOX_INT_STATUS_ADDRESS WLAN_MBOX_INT_STATUS_ADDRESS
#define MBOX_INT_STATUS_OFFSET WLAN_MBOX_INT_STATUS_OFFSET
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
#define MBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB
#define MBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB
#define MBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK
#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x)
#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x)
#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB
#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB
#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK
#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB
#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB
#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK
#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
#define MBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB
#define MBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB
#define MBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK
#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x)
#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x)
#define MBOX_INT_STATUS_HOST_MSB WLAN_MBOX_INT_STATUS_HOST_MSB
#define MBOX_INT_STATUS_HOST_LSB WLAN_MBOX_INT_STATUS_HOST_LSB
#define MBOX_INT_STATUS_HOST_MASK WLAN_MBOX_INT_STATUS_HOST_MASK
#define MBOX_INT_STATUS_HOST_GET(x) WLAN_MBOX_INT_STATUS_HOST_GET(x)
#define MBOX_INT_STATUS_HOST_SET(x) WLAN_MBOX_INT_STATUS_HOST_SET(x)
#define MBOX_INT_ENABLE_ADDRESS WLAN_MBOX_INT_ENABLE_ADDRESS
#define MBOX_INT_ENABLE_OFFSET WLAN_MBOX_INT_ENABLE_OFFSET
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB
#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB
#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK
#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB
#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB
#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK
#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB
#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB
#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK
#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
#define MBOX_INT_ENABLE_HOST_MSB WLAN_MBOX_INT_ENABLE_HOST_MSB
#define MBOX_INT_ENABLE_HOST_LSB WLAN_MBOX_INT_ENABLE_HOST_LSB
#define MBOX_INT_ENABLE_HOST_MASK WLAN_MBOX_INT_ENABLE_HOST_MASK
#define MBOX_INT_ENABLE_HOST_GET(x) WLAN_MBOX_INT_ENABLE_HOST_GET(x)
#define MBOX_INT_ENABLE_HOST_SET(x) WLAN_MBOX_INT_ENABLE_HOST_SET(x)
#define INT_HOST_ADDRESS WLAN_INT_HOST_ADDRESS
#define INT_HOST_OFFSET WLAN_INT_HOST_OFFSET
#define INT_HOST_VECTOR_MSB WLAN_INT_HOST_VECTOR_MSB
#define INT_HOST_VECTOR_LSB WLAN_INT_HOST_VECTOR_LSB
#define INT_HOST_VECTOR_MASK WLAN_INT_HOST_VECTOR_MASK
#define INT_HOST_VECTOR_GET(x) WLAN_INT_HOST_VECTOR_GET(x)
#define INT_HOST_VECTOR_SET(x) WLAN_INT_HOST_VECTOR_SET(x)
#define LOCAL_COUNT_ADDRESS WLAN_LOCAL_COUNT_ADDRESS
#define LOCAL_COUNT_OFFSET WLAN_LOCAL_COUNT_OFFSET
#define LOCAL_COUNT_VALUE_MSB WLAN_LOCAL_COUNT_VALUE_MSB
#define LOCAL_COUNT_VALUE_LSB WLAN_LOCAL_COUNT_VALUE_LSB
#define LOCAL_COUNT_VALUE_MASK WLAN_LOCAL_COUNT_VALUE_MASK
#define LOCAL_COUNT_VALUE_GET(x) WLAN_LOCAL_COUNT_VALUE_GET(x)
#define LOCAL_COUNT_VALUE_SET(x) WLAN_LOCAL_COUNT_VALUE_SET(x)
#define COUNT_INC_ADDRESS WLAN_COUNT_INC_ADDRESS
#define COUNT_INC_OFFSET WLAN_COUNT_INC_OFFSET
#define COUNT_INC_VALUE_MSB WLAN_COUNT_INC_VALUE_MSB
#define COUNT_INC_VALUE_LSB WLAN_COUNT_INC_VALUE_LSB
#define COUNT_INC_VALUE_MASK WLAN_COUNT_INC_VALUE_MASK
#define COUNT_INC_VALUE_GET(x) WLAN_COUNT_INC_VALUE_GET(x)
#define COUNT_INC_VALUE_SET(x) WLAN_COUNT_INC_VALUE_SET(x)
#define LOCAL_SCRATCH_ADDRESS WLAN_LOCAL_SCRATCH_ADDRESS
#define LOCAL_SCRATCH_OFFSET WLAN_LOCAL_SCRATCH_OFFSET
#define LOCAL_SCRATCH_VALUE_MSB WLAN_LOCAL_SCRATCH_VALUE_MSB
#define LOCAL_SCRATCH_VALUE_LSB WLAN_LOCAL_SCRATCH_VALUE_LSB
#define LOCAL_SCRATCH_VALUE_MASK WLAN_LOCAL_SCRATCH_VALUE_MASK
#define LOCAL_SCRATCH_VALUE_GET(x) WLAN_LOCAL_SCRATCH_VALUE_GET(x)
#define LOCAL_SCRATCH_VALUE_SET(x) WLAN_LOCAL_SCRATCH_VALUE_SET(x)
#define USE_LOCAL_BUS_ADDRESS WLAN_USE_LOCAL_BUS_ADDRESS
#define USE_LOCAL_BUS_OFFSET WLAN_USE_LOCAL_BUS_OFFSET
#define USE_LOCAL_BUS_PIN_INIT_MSB WLAN_USE_LOCAL_BUS_PIN_INIT_MSB
#define USE_LOCAL_BUS_PIN_INIT_LSB WLAN_USE_LOCAL_BUS_PIN_INIT_LSB
#define USE_LOCAL_BUS_PIN_INIT_MASK WLAN_USE_LOCAL_BUS_PIN_INIT_MASK
#define USE_LOCAL_BUS_PIN_INIT_GET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x)
#define USE_LOCAL_BUS_PIN_INIT_SET(x) WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x)
#define SDIO_CONFIG_ADDRESS WLAN_SDIO_CONFIG_ADDRESS
#define SDIO_CONFIG_OFFSET WLAN_SDIO_CONFIG_OFFSET
#define SDIO_CONFIG_CCCR_IOR1_MSB WLAN_SDIO_CONFIG_CCCR_IOR1_MSB
#define SDIO_CONFIG_CCCR_IOR1_LSB WLAN_SDIO_CONFIG_CCCR_IOR1_LSB
#define SDIO_CONFIG_CCCR_IOR1_MASK WLAN_SDIO_CONFIG_CCCR_IOR1_MASK
#define SDIO_CONFIG_CCCR_IOR1_GET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x)
#define SDIO_CONFIG_CCCR_IOR1_SET(x) WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x)
#define MBOX_DEBUG_ADDRESS WLAN_MBOX_DEBUG_ADDRESS
#define MBOX_DEBUG_OFFSET WLAN_MBOX_DEBUG_OFFSET
#define MBOX_DEBUG_SEL_MSB WLAN_MBOX_DEBUG_SEL_MSB
#define MBOX_DEBUG_SEL_LSB WLAN_MBOX_DEBUG_SEL_LSB
#define MBOX_DEBUG_SEL_MASK WLAN_MBOX_DEBUG_SEL_MASK
#define MBOX_DEBUG_SEL_GET(x) WLAN_MBOX_DEBUG_SEL_GET(x)
#define MBOX_DEBUG_SEL_SET(x) WLAN_MBOX_DEBUG_SEL_SET(x)
#define MBOX_FIFO_RESET_ADDRESS WLAN_MBOX_FIFO_RESET_ADDRESS
#define MBOX_FIFO_RESET_OFFSET WLAN_MBOX_FIFO_RESET_OFFSET
#define MBOX_FIFO_RESET_INIT_MSB WLAN_MBOX_FIFO_RESET_INIT_MSB
#define MBOX_FIFO_RESET_INIT_LSB WLAN_MBOX_FIFO_RESET_INIT_LSB
#define MBOX_FIFO_RESET_INIT_MASK WLAN_MBOX_FIFO_RESET_INIT_MASK
#define MBOX_FIFO_RESET_INIT_GET(x) WLAN_MBOX_FIFO_RESET_INIT_GET(x)
#define MBOX_FIFO_RESET_INIT_SET(x) WLAN_MBOX_FIFO_RESET_INIT_SET(x)
#define MBOX_TXFIFO_POP_ADDRESS WLAN_MBOX_TXFIFO_POP_ADDRESS
#define MBOX_TXFIFO_POP_OFFSET WLAN_MBOX_TXFIFO_POP_OFFSET
#define MBOX_TXFIFO_POP_DATA_MSB WLAN_MBOX_TXFIFO_POP_DATA_MSB
#define MBOX_TXFIFO_POP_DATA_LSB WLAN_MBOX_TXFIFO_POP_DATA_LSB
#define MBOX_TXFIFO_POP_DATA_MASK WLAN_MBOX_TXFIFO_POP_DATA_MASK
#define MBOX_TXFIFO_POP_DATA_GET(x) WLAN_MBOX_TXFIFO_POP_DATA_GET(x)
#define MBOX_TXFIFO_POP_DATA_SET(x) WLAN_MBOX_TXFIFO_POP_DATA_SET(x)
#define MBOX_RXFIFO_POP_ADDRESS WLAN_MBOX_RXFIFO_POP_ADDRESS
#define MBOX_RXFIFO_POP_OFFSET WLAN_MBOX_RXFIFO_POP_OFFSET
#define MBOX_RXFIFO_POP_DATA_MSB WLAN_MBOX_RXFIFO_POP_DATA_MSB
#define MBOX_RXFIFO_POP_DATA_LSB WLAN_MBOX_RXFIFO_POP_DATA_LSB
#define MBOX_RXFIFO_POP_DATA_MASK WLAN_MBOX_RXFIFO_POP_DATA_MASK
#define MBOX_RXFIFO_POP_DATA_GET(x) WLAN_MBOX_RXFIFO_POP_DATA_GET(x)
#define MBOX_RXFIFO_POP_DATA_SET(x) WLAN_MBOX_RXFIFO_POP_DATA_SET(x)
#define SDIO_DEBUG_ADDRESS WLAN_SDIO_DEBUG_ADDRESS
#define SDIO_DEBUG_OFFSET WLAN_SDIO_DEBUG_OFFSET
#define SDIO_DEBUG_SEL_MSB WLAN_SDIO_DEBUG_SEL_MSB
#define SDIO_DEBUG_SEL_LSB WLAN_SDIO_DEBUG_SEL_LSB
#define SDIO_DEBUG_SEL_MASK WLAN_SDIO_DEBUG_SEL_MASK
#define SDIO_DEBUG_SEL_GET(x) WLAN_SDIO_DEBUG_SEL_GET(x)
#define SDIO_DEBUG_SEL_SET(x) WLAN_SDIO_DEBUG_SEL_SET(x)
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define GMBOX0_DMA_RX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS
#define GMBOX0_DMA_RX_CONTROL_OFFSET WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET
#define GMBOX0_DMA_RX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB
#define GMBOX0_DMA_RX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB
#define GMBOX0_DMA_RX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK
#define GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x)
#define GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x)
#define GMBOX0_DMA_RX_CONTROL_START_MSB WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB
#define GMBOX0_DMA_RX_CONTROL_START_LSB WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB
#define GMBOX0_DMA_RX_CONTROL_START_MASK WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK
#define GMBOX0_DMA_RX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x)
#define GMBOX0_DMA_RX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x)
#define GMBOX0_DMA_RX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB
#define GMBOX0_DMA_RX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB
#define GMBOX0_DMA_RX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK
#define GMBOX0_DMA_RX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x)
#define GMBOX0_DMA_RX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x)
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x)
#define GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x)
#define GMBOX0_DMA_TX_CONTROL_ADDRESS WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS
#define GMBOX0_DMA_TX_CONTROL_OFFSET WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET
#define GMBOX0_DMA_TX_CONTROL_RESUME_MSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB
#define GMBOX0_DMA_TX_CONTROL_RESUME_LSB WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB
#define GMBOX0_DMA_TX_CONTROL_RESUME_MASK WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK
#define GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x)
#define GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x)
#define GMBOX0_DMA_TX_CONTROL_START_MSB WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB
#define GMBOX0_DMA_TX_CONTROL_START_LSB WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB
#define GMBOX0_DMA_TX_CONTROL_START_MASK WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK
#define GMBOX0_DMA_TX_CONTROL_START_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x)
#define GMBOX0_DMA_TX_CONTROL_START_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x)
#define GMBOX0_DMA_TX_CONTROL_STOP_MSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB
#define GMBOX0_DMA_TX_CONTROL_STOP_LSB WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB
#define GMBOX0_DMA_TX_CONTROL_STOP_MASK WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK
#define GMBOX0_DMA_TX_CONTROL_STOP_GET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x)
#define GMBOX0_DMA_TX_CONTROL_STOP_SET(x) WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x)
#define GMBOX_INT_STATUS_ADDRESS WLAN_GMBOX_INT_STATUS_ADDRESS
#define GMBOX_INT_STATUS_OFFSET WLAN_GMBOX_INT_STATUS_OFFSET
#define GMBOX_INT_STATUS_TX_OVERFLOW_MSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB
#define GMBOX_INT_STATUS_TX_OVERFLOW_LSB WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB
#define GMBOX_INT_STATUS_TX_OVERFLOW_MASK WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK
#define GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x)
#define GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x)
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB
#define GMBOX_INT_STATUS_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB
#define GMBOX_INT_STATUS_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK
#define GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x)
#define GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x)
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x)
#define GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x)
#define GMBOX_INT_STATUS_RX_NOT_FULL_MSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB
#define GMBOX_INT_STATUS_RX_NOT_FULL_LSB WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB
#define GMBOX_INT_STATUS_RX_NOT_FULL_MASK WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK
#define GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x)
#define GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x)
#define GMBOX_INT_ENABLE_ADDRESS WLAN_GMBOX_INT_ENABLE_ADDRESS
#define GMBOX_INT_ENABLE_OFFSET WLAN_GMBOX_INT_ENABLE_OFFSET
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB
#define GMBOX_INT_ENABLE_TX_OVERFLOW_LSB WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB
#define GMBOX_INT_ENABLE_TX_OVERFLOW_MASK WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK
#define GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x)
#define GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x)
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x)
#define GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x)
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x)
#define GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x)
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x)
#define GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x)
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB
#define GMBOX_INT_ENABLE_RX_NOT_FULL_LSB WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB
#define GMBOX_INT_ENABLE_RX_NOT_FULL_MASK WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK
#define GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x)
#define GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x)
#define HOST_IF_WINDOW_ADDRESS WLAN_HOST_IF_WINDOW_ADDRESS
#define HOST_IF_WINDOW_OFFSET WLAN_HOST_IF_WINDOW_OFFSET
#define HOST_IF_WINDOW_DATA_MSB WLAN_HOST_IF_WINDOW_DATA_MSB
#define HOST_IF_WINDOW_DATA_LSB WLAN_HOST_IF_WINDOW_DATA_LSB
#define HOST_IF_WINDOW_DATA_MASK WLAN_HOST_IF_WINDOW_DATA_MASK
#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
#endif
#endif

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _MBOX_WLAN_HOST_REG_REG_H_
#define _MBOX_WLAN_HOST_REG_REG_H_
#define HOST_INT_STATUS_ADDRESS 0x00000400
#define HOST_INT_STATUS_OFFSET 0x00000400
#define HOST_INT_STATUS_ERROR_MSB 7
#define HOST_INT_STATUS_ERROR_LSB 7
#define HOST_INT_STATUS_ERROR_MASK 0x00000080
#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
#define HOST_INT_STATUS_CPU_MSB 6
#define HOST_INT_STATUS_CPU_LSB 6
#define HOST_INT_STATUS_CPU_MASK 0x00000040
#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
#define HOST_INT_STATUS_INT_MSB 5
#define HOST_INT_STATUS_INT_LSB 5
#define HOST_INT_STATUS_INT_MASK 0x00000020
#define HOST_INT_STATUS_INT_GET(x) (((x) & HOST_INT_STATUS_INT_MASK) >> HOST_INT_STATUS_INT_LSB)
#define HOST_INT_STATUS_INT_SET(x) (((x) << HOST_INT_STATUS_INT_LSB) & HOST_INT_STATUS_INT_MASK)
#define HOST_INT_STATUS_COUNTER_MSB 4
#define HOST_INT_STATUS_COUNTER_LSB 4
#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
#define HOST_INT_STATUS_MBOX_DATA_MSB 3
#define HOST_INT_STATUS_MBOX_DATA_LSB 0
#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ADDRESS 0x00000401
#define CPU_INT_STATUS_OFFSET 0x00000401
#define CPU_INT_STATUS_BIT_MSB 7
#define CPU_INT_STATUS_BIT_LSB 0
#define CPU_INT_STATUS_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
#define ERROR_INT_STATUS_ADDRESS 0x00000402
#define ERROR_INT_STATUS_OFFSET 0x00000402
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_SYNC_ERROR_MASK)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MSB 5
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB 5
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_OVERFLOW_MASK)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MSB 4
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB 4
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_INT_STATUS_UART_HCI_FRAMER_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_SPI_MSB 3
#define ERROR_INT_STATUS_SPI_LSB 3
#define ERROR_INT_STATUS_SPI_MASK 0x00000008
#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
#define ERROR_INT_STATUS_WAKEUP_MSB 2
#define ERROR_INT_STATUS_WAKEUP_LSB 2
#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ADDRESS 0x00000403
#define COUNTER_INT_STATUS_OFFSET 0x00000403
#define COUNTER_INT_STATUS_COUNTER_MSB 7
#define COUNTER_INT_STATUS_COUNTER_LSB 0
#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
#define MBOX_FRAME_ADDRESS 0x00000404
#define MBOX_FRAME_OFFSET 0x00000404
#define MBOX_FRAME_RX_EOM_MSB 7
#define MBOX_FRAME_RX_EOM_LSB 4
#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
#define MBOX_FRAME_RX_SOM_MSB 3
#define MBOX_FRAME_RX_SOM_LSB 0
#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
#define HOST_INT_STATUS2_ADDRESS 0x00000406
#define HOST_INT_STATUS2_OFFSET 0x00000406
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MSB 2
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB 2
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK 0x00000004
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB)
#define HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_RX_UNDERFLOW_MASK)
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MSB 1
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB 1
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK 0x00000002
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK) >> HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB)
#define HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_LSB) & HOST_INT_STATUS2_GMBOX_TX_OVERFLOW_MASK)
#define HOST_INT_STATUS2_GMBOX_DATA_MSB 0
#define HOST_INT_STATUS2_GMBOX_DATA_LSB 0
#define HOST_INT_STATUS2_GMBOX_DATA_MASK 0x00000001
#define HOST_INT_STATUS2_GMBOX_DATA_GET(x) (((x) & HOST_INT_STATUS2_GMBOX_DATA_MASK) >> HOST_INT_STATUS2_GMBOX_DATA_LSB)
#define HOST_INT_STATUS2_GMBOX_DATA_SET(x) (((x) << HOST_INT_STATUS2_GMBOX_DATA_LSB) & HOST_INT_STATUS2_GMBOX_DATA_MASK)
#define GMBOX_RX_AVAIL_ADDRESS 0x00000407
#define GMBOX_RX_AVAIL_OFFSET 0x00000407
#define GMBOX_RX_AVAIL_BYTE_MSB 6
#define GMBOX_RX_AVAIL_BYTE_LSB 0
#define GMBOX_RX_AVAIL_BYTE_MASK 0x0000007f
#define GMBOX_RX_AVAIL_BYTE_GET(x) (((x) & GMBOX_RX_AVAIL_BYTE_MASK) >> GMBOX_RX_AVAIL_BYTE_LSB)
#define GMBOX_RX_AVAIL_BYTE_SET(x) (((x) << GMBOX_RX_AVAIL_BYTE_LSB) & GMBOX_RX_AVAIL_BYTE_MASK)
#define RX_LOOKAHEAD0_ADDRESS 0x00000408
#define RX_LOOKAHEAD0_OFFSET 0x00000408
#define RX_LOOKAHEAD0_DATA_MSB 7
#define RX_LOOKAHEAD0_DATA_LSB 0
#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
#define RX_LOOKAHEAD1_OFFSET 0x0000040c
#define RX_LOOKAHEAD1_DATA_MSB 7
#define RX_LOOKAHEAD1_DATA_LSB 0
#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
#define RX_LOOKAHEAD2_ADDRESS 0x00000410
#define RX_LOOKAHEAD2_OFFSET 0x00000410
#define RX_LOOKAHEAD2_DATA_MSB 7
#define RX_LOOKAHEAD2_DATA_LSB 0
#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
#define RX_LOOKAHEAD3_ADDRESS 0x00000414
#define RX_LOOKAHEAD3_OFFSET 0x00000414
#define RX_LOOKAHEAD3_DATA_MSB 7
#define RX_LOOKAHEAD3_DATA_LSB 0
#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
#define INT_STATUS_ENABLE_ADDRESS 0x00000418
#define INT_STATUS_ENABLE_OFFSET 0x00000418
#define INT_STATUS_ENABLE_ERROR_MSB 7
#define INT_STATUS_ENABLE_ERROR_LSB 7
#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
#define INT_STATUS_ENABLE_CPU_MSB 6
#define INT_STATUS_ENABLE_CPU_LSB 6
#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
#define INT_STATUS_ENABLE_INT_MSB 5
#define INT_STATUS_ENABLE_INT_LSB 5
#define INT_STATUS_ENABLE_INT_MASK 0x00000020
#define INT_STATUS_ENABLE_INT_GET(x) (((x) & INT_STATUS_ENABLE_INT_MASK) >> INT_STATUS_ENABLE_INT_LSB)
#define INT_STATUS_ENABLE_INT_SET(x) (((x) << INT_STATUS_ENABLE_INT_LSB) & INT_STATUS_ENABLE_INT_MASK)
#define INT_STATUS_ENABLE_COUNTER_MSB 4
#define INT_STATUS_ENABLE_COUNTER_LSB 4
#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MSB 6
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB 6
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK 0x00000040
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_SYNC_ERROR_MASK)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MSB 5
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB 5
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK 0x00000020
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_OVERFLOW_MASK)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MSB 4
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB 4
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK 0x00000010
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_UART_HCI_FRAMER_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
#define COUNT_ADDRESS 0x00000420
#define COUNT_OFFSET 0x00000420
#define COUNT_VALUE_MSB 7
#define COUNT_VALUE_LSB 0
#define COUNT_VALUE_MASK 0x000000ff
#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
#define COUNT_DEC_ADDRESS 0x00000440
#define COUNT_DEC_OFFSET 0x00000440
#define COUNT_DEC_VALUE_MSB 7
#define COUNT_DEC_VALUE_LSB 0
#define COUNT_DEC_VALUE_MASK 0x000000ff
#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
#define SCRATCH_ADDRESS 0x00000460
#define SCRATCH_OFFSET 0x00000460
#define SCRATCH_VALUE_MSB 7
#define SCRATCH_VALUE_LSB 0
#define SCRATCH_VALUE_MASK 0x000000ff
#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
#define FIFO_TIMEOUT_ADDRESS 0x00000468
#define FIFO_TIMEOUT_OFFSET 0x00000468
#define FIFO_TIMEOUT_VALUE_MSB 7
#define FIFO_TIMEOUT_VALUE_LSB 0
#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
#define DISABLE_SLEEP_ADDRESS 0x0000046a
#define DISABLE_SLEEP_OFFSET 0x0000046a
#define DISABLE_SLEEP_FOR_INT_MSB 1
#define DISABLE_SLEEP_FOR_INT_LSB 1
#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
#define DISABLE_SLEEP_ON_MSB 0
#define DISABLE_SLEEP_ON_LSB 0
#define DISABLE_SLEEP_ON_MASK 0x00000001
#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
#define LOCAL_BUS_ADDRESS 0x00000470
#define LOCAL_BUS_OFFSET 0x00000470
#define LOCAL_BUS_STATE_MSB 1
#define LOCAL_BUS_STATE_LSB 0
#define LOCAL_BUS_STATE_MASK 0x00000003
#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
#define INT_WLAN_ADDRESS 0x00000472
#define INT_WLAN_OFFSET 0x00000472
#define INT_WLAN_VECTOR_MSB 7
#define INT_WLAN_VECTOR_LSB 0
#define INT_WLAN_VECTOR_MASK 0x000000ff
#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
#define WINDOW_DATA_ADDRESS 0x00000474
#define WINDOW_DATA_OFFSET 0x00000474
#define WINDOW_DATA_DATA_MSB 7
#define WINDOW_DATA_DATA_LSB 0
#define WINDOW_DATA_DATA_MASK 0x000000ff
#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
#define WINDOW_WRITE_ADDR_ADDR_MSB 7
#define WINDOW_WRITE_ADDR_ADDR_LSB 0
#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
#define WINDOW_READ_ADDR_OFFSET 0x0000047c
#define WINDOW_READ_ADDR_ADDR_MSB 7
#define WINDOW_READ_ADDR_ADDR_LSB 0
#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
#define HOST_CTRL_SPI_CONFIG_ADDRESS 0x00000480
#define HOST_CTRL_SPI_CONFIG_OFFSET 0x00000480
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MSB 4
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB 4
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK 0x00000010
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK) >> HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB)
#define HOST_CTRL_SPI_CONFIG_SPI_RESET_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_SPI_RESET_LSB) & HOST_CTRL_SPI_CONFIG_SPI_RESET_MASK)
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB)
#define HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_LSB) & HOST_CTRL_SPI_CONFIG_INTERRUPT_ENABLE_MASK)
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MSB 2
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB 2
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK 0x00000004
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK) >> HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB)
#define HOST_CTRL_SPI_CONFIG_TEST_MODE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_TEST_MODE_LSB) & HOST_CTRL_SPI_CONFIG_TEST_MODE_MASK)
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MSB 1
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB 0
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK 0x00000003
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_GET(x) (((x) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK) >> HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB)
#define HOST_CTRL_SPI_CONFIG_DATA_SIZE_SET(x) (((x) << HOST_CTRL_SPI_CONFIG_DATA_SIZE_LSB) & HOST_CTRL_SPI_CONFIG_DATA_SIZE_MASK)
#define HOST_CTRL_SPI_STATUS_ADDRESS 0x00000481
#define HOST_CTRL_SPI_STATUS_OFFSET 0x00000481
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MSB 3
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB 3
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK 0x00000008
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_ADDR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_ADDR_ERR_LSB) & HOST_CTRL_SPI_STATUS_ADDR_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_RD_ERR_MSB 2
#define HOST_CTRL_SPI_STATUS_RD_ERR_LSB 2
#define HOST_CTRL_SPI_STATUS_RD_ERR_MASK 0x00000004
#define HOST_CTRL_SPI_STATUS_RD_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK) >> HOST_CTRL_SPI_STATUS_RD_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_RD_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_RD_ERR_LSB) & HOST_CTRL_SPI_STATUS_RD_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_WR_ERR_MSB 1
#define HOST_CTRL_SPI_STATUS_WR_ERR_LSB 1
#define HOST_CTRL_SPI_STATUS_WR_ERR_MASK 0x00000002
#define HOST_CTRL_SPI_STATUS_WR_ERR_GET(x) (((x) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK) >> HOST_CTRL_SPI_STATUS_WR_ERR_LSB)
#define HOST_CTRL_SPI_STATUS_WR_ERR_SET(x) (((x) << HOST_CTRL_SPI_STATUS_WR_ERR_LSB) & HOST_CTRL_SPI_STATUS_WR_ERR_MASK)
#define HOST_CTRL_SPI_STATUS_READY_MSB 0
#define HOST_CTRL_SPI_STATUS_READY_LSB 0
#define HOST_CTRL_SPI_STATUS_READY_MASK 0x00000001
#define HOST_CTRL_SPI_STATUS_READY_GET(x) (((x) & HOST_CTRL_SPI_STATUS_READY_MASK) >> HOST_CTRL_SPI_STATUS_READY_LSB)
#define HOST_CTRL_SPI_STATUS_READY_SET(x) (((x) << HOST_CTRL_SPI_STATUS_READY_LSB) & HOST_CTRL_SPI_STATUS_READY_MASK)
#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
#define CPU_DBG_SEL_ADDRESS 0x00000483
#define CPU_DBG_SEL_OFFSET 0x00000483
#define CPU_DBG_SEL_BIT_MSB 5
#define CPU_DBG_SEL_BIT_LSB 0
#define CPU_DBG_SEL_BIT_MASK 0x0000003f
#define CPU_DBG_SEL_BIT_GET(x) (((x) & CPU_DBG_SEL_BIT_MASK) >> CPU_DBG_SEL_BIT_LSB)
#define CPU_DBG_SEL_BIT_SET(x) (((x) << CPU_DBG_SEL_BIT_LSB) & CPU_DBG_SEL_BIT_MASK)
#define CPU_DBG_ADDRESS 0x00000484
#define CPU_DBG_OFFSET 0x00000484
#define CPU_DBG_DATA_MSB 7
#define CPU_DBG_DATA_LSB 0
#define CPU_DBG_DATA_MASK 0x000000ff
#define CPU_DBG_DATA_GET(x) (((x) & CPU_DBG_DATA_MASK) >> CPU_DBG_DATA_LSB)
#define CPU_DBG_DATA_SET(x) (((x) << CPU_DBG_DATA_LSB) & CPU_DBG_DATA_MASK)
#define INT_STATUS2_ENABLE_ADDRESS 0x00000488
#define INT_STATUS2_ENABLE_OFFSET 0x00000488
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MSB 2
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB 2
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK 0x00000004
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB)
#define INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_RX_UNDERFLOW_MASK)
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MSB 1
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB 1
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK 0x00000002
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK) >> INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB)
#define INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_LSB) & INT_STATUS2_ENABLE_GMBOX_TX_OVERFLOW_MASK)
#define INT_STATUS2_ENABLE_GMBOX_DATA_MSB 0
#define INT_STATUS2_ENABLE_GMBOX_DATA_LSB 0
#define INT_STATUS2_ENABLE_GMBOX_DATA_MASK 0x00000001
#define INT_STATUS2_ENABLE_GMBOX_DATA_GET(x) (((x) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK) >> INT_STATUS2_ENABLE_GMBOX_DATA_LSB)
#define INT_STATUS2_ENABLE_GMBOX_DATA_SET(x) (((x) << INT_STATUS2_ENABLE_GMBOX_DATA_LSB) & INT_STATUS2_ENABLE_GMBOX_DATA_MASK)
#define GMBOX_RX_LOOKAHEAD_ADDRESS 0x00000490
#define GMBOX_RX_LOOKAHEAD_OFFSET 0x00000490
#define GMBOX_RX_LOOKAHEAD_DATA_MSB 7
#define GMBOX_RX_LOOKAHEAD_DATA_LSB 0
#define GMBOX_RX_LOOKAHEAD_DATA_MASK 0x000000ff
#define GMBOX_RX_LOOKAHEAD_DATA_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_DATA_MASK) >> GMBOX_RX_LOOKAHEAD_DATA_LSB)
#define GMBOX_RX_LOOKAHEAD_DATA_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_DATA_LSB) & GMBOX_RX_LOOKAHEAD_DATA_MASK)
#define GMBOX_RX_LOOKAHEAD_MUX_ADDRESS 0x00000498
#define GMBOX_RX_LOOKAHEAD_MUX_OFFSET 0x00000498
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MSB 0
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB 0
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK 0x00000001
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_GET(x) (((x) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK) >> GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB)
#define GMBOX_RX_LOOKAHEAD_MUX_SEL_SET(x) (((x) << GMBOX_RX_LOOKAHEAD_MUX_SEL_LSB) & GMBOX_RX_LOOKAHEAD_MUX_SEL_MASK)
#define CIS_WINDOW_ADDRESS 0x00000600
#define CIS_WINDOW_OFFSET 0x00000600
#define CIS_WINDOW_DATA_MSB 7
#define CIS_WINDOW_DATA_LSB 0
#define CIS_WINDOW_DATA_MASK 0x000000ff
#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_host_reg_reg_s {
unsigned char pad0[1024]; /* pad to 0x400 */
volatile unsigned char host_int_status;
volatile unsigned char cpu_int_status;
volatile unsigned char error_int_status;
volatile unsigned char counter_int_status;
volatile unsigned char mbox_frame;
volatile unsigned char rx_lookahead_valid;
volatile unsigned char host_int_status2;
volatile unsigned char gmbox_rx_avail;
volatile unsigned char rx_lookahead0[4];
volatile unsigned char rx_lookahead1[4];
volatile unsigned char rx_lookahead2[4];
volatile unsigned char rx_lookahead3[4];
volatile unsigned char int_status_enable;
volatile unsigned char cpu_int_status_enable;
volatile unsigned char error_status_enable;
volatile unsigned char counter_int_status_enable;
unsigned char pad1[4]; /* pad to 0x420 */
volatile unsigned char count[8];
unsigned char pad2[24]; /* pad to 0x440 */
volatile unsigned char count_dec[32];
volatile unsigned char scratch[8];
volatile unsigned char fifo_timeout;
volatile unsigned char fifo_timeout_enable;
volatile unsigned char disable_sleep;
unsigned char pad3[5]; /* pad to 0x470 */
volatile unsigned char local_bus;
unsigned char pad4[1]; /* pad to 0x472 */
volatile unsigned char int_wlan;
unsigned char pad5[1]; /* pad to 0x474 */
volatile unsigned char window_data[4];
volatile unsigned char window_write_addr[4];
volatile unsigned char window_read_addr[4];
volatile unsigned char host_ctrl_spi_config;
volatile unsigned char host_ctrl_spi_status;
volatile unsigned char non_assoc_sleep_en;
volatile unsigned char cpu_dbg_sel;
volatile unsigned char cpu_dbg[4];
volatile unsigned char int_status2_enable;
unsigned char pad6[7]; /* pad to 0x490 */
volatile unsigned char gmbox_rx_lookahead[8];
volatile unsigned char gmbox_rx_lookahead_mux;
unsigned char pad7[359]; /* pad to 0x600 */
volatile unsigned char cis_window[512];
} mbox_wlan_host_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_HOST_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _MBOX_WLAN_REG_REG_H_
#define _MBOX_WLAN_REG_REG_H_
#define WLAN_MBOX_FIFO_ADDRESS 0x00000000
#define WLAN_MBOX_FIFO_OFFSET 0x00000000
#define WLAN_MBOX_FIFO_DATA_MSB 19
#define WLAN_MBOX_FIFO_DATA_LSB 0
#define WLAN_MBOX_FIFO_DATA_MASK 0x000fffff
#define WLAN_MBOX_FIFO_DATA_GET(x) (((x) & WLAN_MBOX_FIFO_DATA_MASK) >> WLAN_MBOX_FIFO_DATA_LSB)
#define WLAN_MBOX_FIFO_DATA_SET(x) (((x) << WLAN_MBOX_FIFO_DATA_LSB) & WLAN_MBOX_FIFO_DATA_MASK)
#define WLAN_MBOX_FIFO_STATUS_ADDRESS 0x00000010
#define WLAN_MBOX_FIFO_STATUS_OFFSET 0x00000010
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MSB 19
#define WLAN_MBOX_FIFO_STATUS_EMPTY_LSB 16
#define WLAN_MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
#define WLAN_MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK) >> WLAN_MBOX_FIFO_STATUS_EMPTY_LSB)
#define WLAN_MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_EMPTY_LSB) & WLAN_MBOX_FIFO_STATUS_EMPTY_MASK)
#define WLAN_MBOX_FIFO_STATUS_FULL_MSB 15
#define WLAN_MBOX_FIFO_STATUS_FULL_LSB 12
#define WLAN_MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
#define WLAN_MBOX_FIFO_STATUS_FULL_GET(x) (((x) & WLAN_MBOX_FIFO_STATUS_FULL_MASK) >> WLAN_MBOX_FIFO_STATUS_FULL_LSB)
#define WLAN_MBOX_FIFO_STATUS_FULL_SET(x) (((x) << WLAN_MBOX_FIFO_STATUS_FULL_LSB) & WLAN_MBOX_FIFO_STATUS_FULL_MASK)
#define WLAN_MBOX_DMA_POLICY_ADDRESS 0x00000014
#define WLAN_MBOX_DMA_POLICY_OFFSET 0x00000014
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define WLAN_MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MSB 2
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB 2
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB)
#define WLAN_MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_TX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_TX_ORDER_MASK)
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define WLAN_MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_QUANTUM_LSB) & WLAN_MBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MSB 0
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB 0
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK) >> WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB)
#define WLAN_MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << WLAN_MBOX_DMA_POLICY_RX_ORDER_LSB) & WLAN_MBOX_DMA_POLICY_RX_ORDER_MASK)
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
#define WLAN_MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX0_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
#define WLAN_MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX0_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX0_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
#define WLAN_MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX1_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
#define WLAN_MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX1_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX1_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX1_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
#define WLAN_MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX2_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
#define WLAN_MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX2_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX2_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX2_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
#define WLAN_MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MSB 1
#define WLAN_MBOX3_DMA_RX_CONTROL_START_LSB 1
#define WLAN_MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_START_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_START_MASK)
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_RX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
#define WLAN_MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_RESUME_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MSB 1
#define WLAN_MBOX3_DMA_TX_CONTROL_START_LSB 1
#define WLAN_MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_START_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_START_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_START_MASK)
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK) >> WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_MBOX3_DMA_TX_CONTROL_STOP_LSB) & WLAN_MBOX3_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_MBOX_INT_STATUS_ADDRESS 0x00000058
#define WLAN_MBOX_INT_STATUS_OFFSET 0x00000058
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define WLAN_MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define WLAN_MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define WLAN_MBOX_INT_STATUS_HOST_MSB 7
#define WLAN_MBOX_INT_STATUS_HOST_LSB 0
#define WLAN_MBOX_INT_STATUS_HOST_MASK 0x000000ff
#define WLAN_MBOX_INT_STATUS_HOST_GET(x) (((x) & WLAN_MBOX_INT_STATUS_HOST_MASK) >> WLAN_MBOX_INT_STATUS_HOST_LSB)
#define WLAN_MBOX_INT_STATUS_HOST_SET(x) (((x) << WLAN_MBOX_INT_STATUS_HOST_LSB) & WLAN_MBOX_INT_STATUS_HOST_MASK)
#define WLAN_MBOX_INT_ENABLE_ADDRESS 0x0000005c
#define WLAN_MBOX_INT_ENABLE_OFFSET 0x0000005c
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define WLAN_MBOX_INT_ENABLE_HOST_MSB 7
#define WLAN_MBOX_INT_ENABLE_HOST_LSB 0
#define WLAN_MBOX_INT_ENABLE_HOST_MASK 0x000000ff
#define WLAN_MBOX_INT_ENABLE_HOST_GET(x) (((x) & WLAN_MBOX_INT_ENABLE_HOST_MASK) >> WLAN_MBOX_INT_ENABLE_HOST_LSB)
#define WLAN_MBOX_INT_ENABLE_HOST_SET(x) (((x) << WLAN_MBOX_INT_ENABLE_HOST_LSB) & WLAN_MBOX_INT_ENABLE_HOST_MASK)
#define WLAN_INT_HOST_ADDRESS 0x00000060
#define WLAN_INT_HOST_OFFSET 0x00000060
#define WLAN_INT_HOST_VECTOR_MSB 7
#define WLAN_INT_HOST_VECTOR_LSB 0
#define WLAN_INT_HOST_VECTOR_MASK 0x000000ff
#define WLAN_INT_HOST_VECTOR_GET(x) (((x) & WLAN_INT_HOST_VECTOR_MASK) >> WLAN_INT_HOST_VECTOR_LSB)
#define WLAN_INT_HOST_VECTOR_SET(x) (((x) << WLAN_INT_HOST_VECTOR_LSB) & WLAN_INT_HOST_VECTOR_MASK)
#define WLAN_LOCAL_COUNT_ADDRESS 0x00000080
#define WLAN_LOCAL_COUNT_OFFSET 0x00000080
#define WLAN_LOCAL_COUNT_VALUE_MSB 7
#define WLAN_LOCAL_COUNT_VALUE_LSB 0
#define WLAN_LOCAL_COUNT_VALUE_MASK 0x000000ff
#define WLAN_LOCAL_COUNT_VALUE_GET(x) (((x) & WLAN_LOCAL_COUNT_VALUE_MASK) >> WLAN_LOCAL_COUNT_VALUE_LSB)
#define WLAN_LOCAL_COUNT_VALUE_SET(x) (((x) << WLAN_LOCAL_COUNT_VALUE_LSB) & WLAN_LOCAL_COUNT_VALUE_MASK)
#define WLAN_COUNT_INC_ADDRESS 0x000000a0
#define WLAN_COUNT_INC_OFFSET 0x000000a0
#define WLAN_COUNT_INC_VALUE_MSB 7
#define WLAN_COUNT_INC_VALUE_LSB 0
#define WLAN_COUNT_INC_VALUE_MASK 0x000000ff
#define WLAN_COUNT_INC_VALUE_GET(x) (((x) & WLAN_COUNT_INC_VALUE_MASK) >> WLAN_COUNT_INC_VALUE_LSB)
#define WLAN_COUNT_INC_VALUE_SET(x) (((x) << WLAN_COUNT_INC_VALUE_LSB) & WLAN_COUNT_INC_VALUE_MASK)
#define WLAN_LOCAL_SCRATCH_ADDRESS 0x000000c0
#define WLAN_LOCAL_SCRATCH_OFFSET 0x000000c0
#define WLAN_LOCAL_SCRATCH_VALUE_MSB 7
#define WLAN_LOCAL_SCRATCH_VALUE_LSB 0
#define WLAN_LOCAL_SCRATCH_VALUE_MASK 0x000000ff
#define WLAN_LOCAL_SCRATCH_VALUE_GET(x) (((x) & WLAN_LOCAL_SCRATCH_VALUE_MASK) >> WLAN_LOCAL_SCRATCH_VALUE_LSB)
#define WLAN_LOCAL_SCRATCH_VALUE_SET(x) (((x) << WLAN_LOCAL_SCRATCH_VALUE_LSB) & WLAN_LOCAL_SCRATCH_VALUE_MASK)
#define WLAN_USE_LOCAL_BUS_ADDRESS 0x000000e0
#define WLAN_USE_LOCAL_BUS_OFFSET 0x000000e0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MSB 0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_LSB 0
#define WLAN_USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
#define WLAN_USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK) >> WLAN_USE_LOCAL_BUS_PIN_INIT_LSB)
#define WLAN_USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << WLAN_USE_LOCAL_BUS_PIN_INIT_LSB) & WLAN_USE_LOCAL_BUS_PIN_INIT_MASK)
#define WLAN_SDIO_CONFIG_ADDRESS 0x000000e4
#define WLAN_SDIO_CONFIG_OFFSET 0x000000e4
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MSB 0
#define WLAN_SDIO_CONFIG_CCCR_IOR1_LSB 0
#define WLAN_SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
#define WLAN_SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK) >> WLAN_SDIO_CONFIG_CCCR_IOR1_LSB)
#define WLAN_SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << WLAN_SDIO_CONFIG_CCCR_IOR1_LSB) & WLAN_SDIO_CONFIG_CCCR_IOR1_MASK)
#define WLAN_MBOX_DEBUG_ADDRESS 0x000000e8
#define WLAN_MBOX_DEBUG_OFFSET 0x000000e8
#define WLAN_MBOX_DEBUG_SEL_MSB 2
#define WLAN_MBOX_DEBUG_SEL_LSB 0
#define WLAN_MBOX_DEBUG_SEL_MASK 0x00000007
#define WLAN_MBOX_DEBUG_SEL_GET(x) (((x) & WLAN_MBOX_DEBUG_SEL_MASK) >> WLAN_MBOX_DEBUG_SEL_LSB)
#define WLAN_MBOX_DEBUG_SEL_SET(x) (((x) << WLAN_MBOX_DEBUG_SEL_LSB) & WLAN_MBOX_DEBUG_SEL_MASK)
#define WLAN_MBOX_FIFO_RESET_ADDRESS 0x000000ec
#define WLAN_MBOX_FIFO_RESET_OFFSET 0x000000ec
#define WLAN_MBOX_FIFO_RESET_INIT_MSB 0
#define WLAN_MBOX_FIFO_RESET_INIT_LSB 0
#define WLAN_MBOX_FIFO_RESET_INIT_MASK 0x00000001
#define WLAN_MBOX_FIFO_RESET_INIT_GET(x) (((x) & WLAN_MBOX_FIFO_RESET_INIT_MASK) >> WLAN_MBOX_FIFO_RESET_INIT_LSB)
#define WLAN_MBOX_FIFO_RESET_INIT_SET(x) (((x) << WLAN_MBOX_FIFO_RESET_INIT_LSB) & WLAN_MBOX_FIFO_RESET_INIT_MASK)
#define WLAN_MBOX_TXFIFO_POP_ADDRESS 0x000000f0
#define WLAN_MBOX_TXFIFO_POP_OFFSET 0x000000f0
#define WLAN_MBOX_TXFIFO_POP_DATA_MSB 0
#define WLAN_MBOX_TXFIFO_POP_DATA_LSB 0
#define WLAN_MBOX_TXFIFO_POP_DATA_MASK 0x00000001
#define WLAN_MBOX_TXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_TXFIFO_POP_DATA_MASK) >> WLAN_MBOX_TXFIFO_POP_DATA_LSB)
#define WLAN_MBOX_TXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_TXFIFO_POP_DATA_LSB) & WLAN_MBOX_TXFIFO_POP_DATA_MASK)
#define WLAN_MBOX_RXFIFO_POP_ADDRESS 0x00000100
#define WLAN_MBOX_RXFIFO_POP_OFFSET 0x00000100
#define WLAN_MBOX_RXFIFO_POP_DATA_MSB 0
#define WLAN_MBOX_RXFIFO_POP_DATA_LSB 0
#define WLAN_MBOX_RXFIFO_POP_DATA_MASK 0x00000001
#define WLAN_MBOX_RXFIFO_POP_DATA_GET(x) (((x) & WLAN_MBOX_RXFIFO_POP_DATA_MASK) >> WLAN_MBOX_RXFIFO_POP_DATA_LSB)
#define WLAN_MBOX_RXFIFO_POP_DATA_SET(x) (((x) << WLAN_MBOX_RXFIFO_POP_DATA_LSB) & WLAN_MBOX_RXFIFO_POP_DATA_MASK)
#define WLAN_SDIO_DEBUG_ADDRESS 0x00000110
#define WLAN_SDIO_DEBUG_OFFSET 0x00000110
#define WLAN_SDIO_DEBUG_SEL_MSB 3
#define WLAN_SDIO_DEBUG_SEL_LSB 0
#define WLAN_SDIO_DEBUG_SEL_MASK 0x0000000f
#define WLAN_SDIO_DEBUG_SEL_GET(x) (((x) & WLAN_SDIO_DEBUG_SEL_MASK) >> WLAN_SDIO_DEBUG_SEL_LSB)
#define WLAN_SDIO_DEBUG_SEL_SET(x) (((x) << WLAN_SDIO_DEBUG_SEL_LSB) & WLAN_SDIO_DEBUG_SEL_MASK)
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000114
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000114
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000118
#define WLAN_GMBOX0_DMA_RX_CONTROL_OFFSET 0x00000118
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MSB 1
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB 1
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_START_MASK)
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB)
#define WLAN_GMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_RX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_RX_CONTROL_STOP_MASK)
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x0000011c
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x0000011c
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & WLAN_GMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_ADDRESS 0x00000120
#define WLAN_GMBOX0_DMA_TX_CONTROL_OFFSET 0x00000120
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MSB 1
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB 1
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_START_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_START_MASK)
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK) >> WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB)
#define WLAN_GMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << WLAN_GMBOX0_DMA_TX_CONTROL_STOP_LSB) & WLAN_GMBOX0_DMA_TX_CONTROL_STOP_MASK)
#define WLAN_GMBOX_INT_STATUS_ADDRESS 0x00000124
#define WLAN_GMBOX_INT_STATUS_OFFSET 0x00000124
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MSB 6
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB 6
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000040
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MSB 5
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB 5
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000020
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 4
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 4
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000010
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 3
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 3
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000008
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 2
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 2
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000004
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define WLAN_GMBOX_INT_ENABLE_ADDRESS 0x00000128
#define WLAN_GMBOX_INT_ENABLE_OFFSET 0x00000128
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MSB 6
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB 6
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000040
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 5
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 5
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000020
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & WLAN_GMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 4
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 4
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000010
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 3
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 3
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000008
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 2
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 2
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000004
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & WLAN_GMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & WLAN_GMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & WLAN_GMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define WLAN_HOST_IF_WINDOW_ADDRESS 0x00002000
#define WLAN_HOST_IF_WINDOW_OFFSET 0x00002000
#define WLAN_HOST_IF_WINDOW_DATA_MSB 7
#define WLAN_HOST_IF_WINDOW_DATA_LSB 0
#define WLAN_HOST_IF_WINDOW_DATA_MASK 0x000000ff
#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
#ifndef __ASSEMBLER__
typedef struct mbox_wlan_reg_reg_s {
volatile unsigned int wlan_mbox_fifo[4];
volatile unsigned int wlan_mbox_fifo_status;
volatile unsigned int wlan_mbox_dma_policy;
volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_rx_control;
volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox0_dma_tx_control;
volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_rx_control;
volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox1_dma_tx_control;
volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_rx_control;
volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox2_dma_tx_control;
volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_rx_control;
volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
volatile unsigned int wlan_mbox3_dma_tx_control;
volatile unsigned int wlan_mbox_int_status;
volatile unsigned int wlan_mbox_int_enable;
volatile unsigned int wlan_int_host;
unsigned char pad0[28]; /* pad to 0x80 */
volatile unsigned int wlan_local_count[8];
volatile unsigned int wlan_count_inc[8];
volatile unsigned int wlan_local_scratch[8];
volatile unsigned int wlan_use_local_bus;
volatile unsigned int wlan_sdio_config;
volatile unsigned int wlan_mbox_debug;
volatile unsigned int wlan_mbox_fifo_reset;
volatile unsigned int wlan_mbox_txfifo_pop[4];
volatile unsigned int wlan_mbox_rxfifo_pop[4];
volatile unsigned int wlan_sdio_debug;
volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_rx_control;
volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
volatile unsigned int wlan_gmbox0_dma_tx_control;
volatile unsigned int wlan_gmbox_int_status;
volatile unsigned int wlan_gmbox_int_enable;
unsigned char pad1[7892]; /* pad to 0x2000 */
volatile unsigned int wlan_host_if_window[2048];
} mbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _MBOX_WLAN_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _RDMA_REG_REG_H_
#define _RDMA_REG_REG_H_
#define DMA_CONFIG_ADDRESS 0x00000000
#define DMA_CONFIG_OFFSET 0x00000000
#define DMA_CONFIG_WLBB_PWD_EN_MSB 4
#define DMA_CONFIG_WLBB_PWD_EN_LSB 4
#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010
#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3
#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008
#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
#define DMA_CONFIG_ENABLE_RETENTION_MSB 2
#define DMA_CONFIG_ENABLE_RETENTION_LSB 2
#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004
#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
#define DMA_CONFIG_RTC_PRIORITY_MSB 1
#define DMA_CONFIG_RTC_PRIORITY_LSB 1
#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002
#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
#define DMA_CONFIG_DMA_TYPE_MSB 0
#define DMA_CONFIG_DMA_TYPE_LSB 0
#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001
#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
#define DMA_CONTROL_ADDRESS 0x00000004
#define DMA_CONTROL_OFFSET 0x00000004
#define DMA_CONTROL_START_MSB 1
#define DMA_CONTROL_START_LSB 1
#define DMA_CONTROL_START_MASK 0x00000002
#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
#define DMA_CONTROL_STOP_MSB 0
#define DMA_CONTROL_STOP_LSB 0
#define DMA_CONTROL_STOP_MASK 0x00000001
#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
#define DMA_SRC_ADDRESS 0x00000008
#define DMA_SRC_OFFSET 0x00000008
#define DMA_SRC_ADDR_MSB 31
#define DMA_SRC_ADDR_LSB 2
#define DMA_SRC_ADDR_MASK 0xfffffffc
#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
#define DMA_DEST_ADDRESS 0x0000000c
#define DMA_DEST_OFFSET 0x0000000c
#define DMA_DEST_ADDR_MSB 31
#define DMA_DEST_ADDR_LSB 2
#define DMA_DEST_ADDR_MASK 0xfffffffc
#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
#define DMA_LENGTH_ADDRESS 0x00000010
#define DMA_LENGTH_OFFSET 0x00000010
#define DMA_LENGTH_WORDS_MSB 11
#define DMA_LENGTH_WORDS_LSB 0
#define DMA_LENGTH_WORDS_MASK 0x00000fff
#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
#define VMC_BASE_ADDRESS 0x00000014
#define VMC_BASE_OFFSET 0x00000014
#define VMC_BASE_ADDR_MSB 31
#define VMC_BASE_ADDR_LSB 2
#define VMC_BASE_ADDR_MASK 0xfffffffc
#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
#define INDIRECT_REG_ADDRESS 0x00000018
#define INDIRECT_REG_OFFSET 0x00000018
#define INDIRECT_REG_ID_MSB 31
#define INDIRECT_REG_ID_LSB 2
#define INDIRECT_REG_ID_MASK 0xfffffffc
#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
#define INDIRECT_RETURN_ADDRESS 0x0000001c
#define INDIRECT_RETURN_OFFSET 0x0000001c
#define INDIRECT_RETURN_ADDR_MSB 31
#define INDIRECT_RETURN_ADDR_LSB 2
#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc
#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
#define RDMA_REGION_0__ADDRESS 0x00000020
#define RDMA_REGION_0__OFFSET 0x00000020
#define RDMA_REGION_0__ADDR_MSB 31
#define RDMA_REGION_0__ADDR_LSB 13
#define RDMA_REGION_0__ADDR_MASK 0xffffe000
#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
#define RDMA_REGION_0__LENGTH_MSB 12
#define RDMA_REGION_0__LENGTH_LSB 2
#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
#define RDMA_REGION_0__INDI_MSB 1
#define RDMA_REGION_0__INDI_LSB 1
#define RDMA_REGION_0__INDI_MASK 0x00000002
#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
#define RDMA_REGION_0__NEXT_MSB 0
#define RDMA_REGION_0__NEXT_LSB 0
#define RDMA_REGION_0__NEXT_MASK 0x00000001
#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
#define RDMA_REGION_1__ADDRESS 0x00000024
#define RDMA_REGION_1__OFFSET 0x00000024
#define RDMA_REGION_1__ADDR_MSB 31
#define RDMA_REGION_1__ADDR_LSB 13
#define RDMA_REGION_1__ADDR_MASK 0xffffe000
#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
#define RDMA_REGION_1__LENGTH_MSB 12
#define RDMA_REGION_1__LENGTH_LSB 2
#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
#define RDMA_REGION_1__INDI_MSB 1
#define RDMA_REGION_1__INDI_LSB 1
#define RDMA_REGION_1__INDI_MASK 0x00000002
#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
#define RDMA_REGION_1__NEXT_MSB 0
#define RDMA_REGION_1__NEXT_LSB 0
#define RDMA_REGION_1__NEXT_MASK 0x00000001
#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
#define RDMA_REGION_2__ADDRESS 0x00000028
#define RDMA_REGION_2__OFFSET 0x00000028
#define RDMA_REGION_2__ADDR_MSB 31
#define RDMA_REGION_2__ADDR_LSB 13
#define RDMA_REGION_2__ADDR_MASK 0xffffe000
#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
#define RDMA_REGION_2__LENGTH_MSB 12
#define RDMA_REGION_2__LENGTH_LSB 2
#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
#define RDMA_REGION_2__INDI_MSB 1
#define RDMA_REGION_2__INDI_LSB 1
#define RDMA_REGION_2__INDI_MASK 0x00000002
#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
#define RDMA_REGION_2__NEXT_MSB 0
#define RDMA_REGION_2__NEXT_LSB 0
#define RDMA_REGION_2__NEXT_MASK 0x00000001
#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
#define RDMA_REGION_3__ADDRESS 0x0000002c
#define RDMA_REGION_3__OFFSET 0x0000002c
#define RDMA_REGION_3__ADDR_MSB 31
#define RDMA_REGION_3__ADDR_LSB 13
#define RDMA_REGION_3__ADDR_MASK 0xffffe000
#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
#define RDMA_REGION_3__LENGTH_MSB 12
#define RDMA_REGION_3__LENGTH_LSB 2
#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
#define RDMA_REGION_3__INDI_MSB 1
#define RDMA_REGION_3__INDI_LSB 1
#define RDMA_REGION_3__INDI_MASK 0x00000002
#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
#define RDMA_REGION_3__NEXT_MSB 0
#define RDMA_REGION_3__NEXT_LSB 0
#define RDMA_REGION_3__NEXT_MASK 0x00000001
#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
#define RDMA_REGION_4__ADDRESS 0x00000030
#define RDMA_REGION_4__OFFSET 0x00000030
#define RDMA_REGION_4__ADDR_MSB 31
#define RDMA_REGION_4__ADDR_LSB 13
#define RDMA_REGION_4__ADDR_MASK 0xffffe000
#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
#define RDMA_REGION_4__LENGTH_MSB 12
#define RDMA_REGION_4__LENGTH_LSB 2
#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
#define RDMA_REGION_4__INDI_MSB 1
#define RDMA_REGION_4__INDI_LSB 1
#define RDMA_REGION_4__INDI_MASK 0x00000002
#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
#define RDMA_REGION_4__NEXT_MSB 0
#define RDMA_REGION_4__NEXT_LSB 0
#define RDMA_REGION_4__NEXT_MASK 0x00000001
#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
#define RDMA_REGION_5__ADDRESS 0x00000034
#define RDMA_REGION_5__OFFSET 0x00000034
#define RDMA_REGION_5__ADDR_MSB 31
#define RDMA_REGION_5__ADDR_LSB 13
#define RDMA_REGION_5__ADDR_MASK 0xffffe000
#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
#define RDMA_REGION_5__LENGTH_MSB 12
#define RDMA_REGION_5__LENGTH_LSB 2
#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
#define RDMA_REGION_5__INDI_MSB 1
#define RDMA_REGION_5__INDI_LSB 1
#define RDMA_REGION_5__INDI_MASK 0x00000002
#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
#define RDMA_REGION_5__NEXT_MSB 0
#define RDMA_REGION_5__NEXT_LSB 0
#define RDMA_REGION_5__NEXT_MASK 0x00000001
#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
#define RDMA_REGION_6__ADDRESS 0x00000038
#define RDMA_REGION_6__OFFSET 0x00000038
#define RDMA_REGION_6__ADDR_MSB 31
#define RDMA_REGION_6__ADDR_LSB 13
#define RDMA_REGION_6__ADDR_MASK 0xffffe000
#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
#define RDMA_REGION_6__LENGTH_MSB 12
#define RDMA_REGION_6__LENGTH_LSB 2
#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
#define RDMA_REGION_6__INDI_MSB 1
#define RDMA_REGION_6__INDI_LSB 1
#define RDMA_REGION_6__INDI_MASK 0x00000002
#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
#define RDMA_REGION_6__NEXT_MSB 0
#define RDMA_REGION_6__NEXT_LSB 0
#define RDMA_REGION_6__NEXT_MASK 0x00000001
#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
#define RDMA_REGION_7__ADDRESS 0x0000003c
#define RDMA_REGION_7__OFFSET 0x0000003c
#define RDMA_REGION_7__ADDR_MSB 31
#define RDMA_REGION_7__ADDR_LSB 13
#define RDMA_REGION_7__ADDR_MASK 0xffffe000
#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
#define RDMA_REGION_7__LENGTH_MSB 12
#define RDMA_REGION_7__LENGTH_LSB 2
#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
#define RDMA_REGION_7__INDI_MSB 1
#define RDMA_REGION_7__INDI_LSB 1
#define RDMA_REGION_7__INDI_MASK 0x00000002
#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
#define RDMA_REGION_7__NEXT_MSB 0
#define RDMA_REGION_7__NEXT_LSB 0
#define RDMA_REGION_7__NEXT_MASK 0x00000001
#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
#define RDMA_REGION_8__ADDRESS 0x00000040
#define RDMA_REGION_8__OFFSET 0x00000040
#define RDMA_REGION_8__ADDR_MSB 31
#define RDMA_REGION_8__ADDR_LSB 13
#define RDMA_REGION_8__ADDR_MASK 0xffffe000
#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
#define RDMA_REGION_8__LENGTH_MSB 12
#define RDMA_REGION_8__LENGTH_LSB 2
#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
#define RDMA_REGION_8__INDI_MSB 1
#define RDMA_REGION_8__INDI_LSB 1
#define RDMA_REGION_8__INDI_MASK 0x00000002
#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
#define RDMA_REGION_8__NEXT_MSB 0
#define RDMA_REGION_8__NEXT_LSB 0
#define RDMA_REGION_8__NEXT_MASK 0x00000001
#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
#define RDMA_REGION_9__ADDRESS 0x00000044
#define RDMA_REGION_9__OFFSET 0x00000044
#define RDMA_REGION_9__ADDR_MSB 31
#define RDMA_REGION_9__ADDR_LSB 13
#define RDMA_REGION_9__ADDR_MASK 0xffffe000
#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
#define RDMA_REGION_9__LENGTH_MSB 12
#define RDMA_REGION_9__LENGTH_LSB 2
#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
#define RDMA_REGION_9__INDI_MSB 1
#define RDMA_REGION_9__INDI_LSB 1
#define RDMA_REGION_9__INDI_MASK 0x00000002
#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
#define RDMA_REGION_9__NEXT_MSB 0
#define RDMA_REGION_9__NEXT_LSB 0
#define RDMA_REGION_9__NEXT_MASK 0x00000001
#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
#define RDMA_REGION_10__ADDRESS 0x00000048
#define RDMA_REGION_10__OFFSET 0x00000048
#define RDMA_REGION_10__ADDR_MSB 31
#define RDMA_REGION_10__ADDR_LSB 13
#define RDMA_REGION_10__ADDR_MASK 0xffffe000
#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
#define RDMA_REGION_10__LENGTH_MSB 12
#define RDMA_REGION_10__LENGTH_LSB 2
#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
#define RDMA_REGION_10__INDI_MSB 1
#define RDMA_REGION_10__INDI_LSB 1
#define RDMA_REGION_10__INDI_MASK 0x00000002
#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
#define RDMA_REGION_10__NEXT_MSB 0
#define RDMA_REGION_10__NEXT_LSB 0
#define RDMA_REGION_10__NEXT_MASK 0x00000001
#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
#define RDMA_REGION_11__ADDRESS 0x0000004c
#define RDMA_REGION_11__OFFSET 0x0000004c
#define RDMA_REGION_11__ADDR_MSB 31
#define RDMA_REGION_11__ADDR_LSB 13
#define RDMA_REGION_11__ADDR_MASK 0xffffe000
#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
#define RDMA_REGION_11__LENGTH_MSB 12
#define RDMA_REGION_11__LENGTH_LSB 2
#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
#define RDMA_REGION_11__INDI_MSB 1
#define RDMA_REGION_11__INDI_LSB 1
#define RDMA_REGION_11__INDI_MASK 0x00000002
#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
#define RDMA_REGION_11__NEXT_MSB 0
#define RDMA_REGION_11__NEXT_LSB 0
#define RDMA_REGION_11__NEXT_MASK 0x00000001
#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
#define RDMA_REGION_12__ADDRESS 0x00000050
#define RDMA_REGION_12__OFFSET 0x00000050
#define RDMA_REGION_12__ADDR_MSB 31
#define RDMA_REGION_12__ADDR_LSB 13
#define RDMA_REGION_12__ADDR_MASK 0xffffe000
#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
#define RDMA_REGION_12__LENGTH_MSB 12
#define RDMA_REGION_12__LENGTH_LSB 2
#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
#define RDMA_REGION_12__INDI_MSB 1
#define RDMA_REGION_12__INDI_LSB 1
#define RDMA_REGION_12__INDI_MASK 0x00000002
#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
#define RDMA_REGION_12__NEXT_MSB 0
#define RDMA_REGION_12__NEXT_LSB 0
#define RDMA_REGION_12__NEXT_MASK 0x00000001
#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
#define RDMA_REGION_13__ADDRESS 0x00000054
#define RDMA_REGION_13__OFFSET 0x00000054
#define RDMA_REGION_13__ADDR_MSB 31
#define RDMA_REGION_13__ADDR_LSB 13
#define RDMA_REGION_13__ADDR_MASK 0xffffe000
#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
#define RDMA_REGION_13__LENGTH_MSB 12
#define RDMA_REGION_13__LENGTH_LSB 2
#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
#define RDMA_REGION_13__INDI_MSB 1
#define RDMA_REGION_13__INDI_LSB 1
#define RDMA_REGION_13__INDI_MASK 0x00000002
#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
#define RDMA_REGION_13__NEXT_MSB 0
#define RDMA_REGION_13__NEXT_LSB 0
#define RDMA_REGION_13__NEXT_MASK 0x00000001
#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
#define RDMA_REGION_14__ADDRESS 0x00000058
#define RDMA_REGION_14__OFFSET 0x00000058
#define RDMA_REGION_14__ADDR_MSB 31
#define RDMA_REGION_14__ADDR_LSB 13
#define RDMA_REGION_14__ADDR_MASK 0xffffe000
#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
#define RDMA_REGION_14__LENGTH_MSB 12
#define RDMA_REGION_14__LENGTH_LSB 2
#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
#define RDMA_REGION_14__INDI_MSB 1
#define RDMA_REGION_14__INDI_LSB 1
#define RDMA_REGION_14__INDI_MASK 0x00000002
#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
#define RDMA_REGION_14__NEXT_MSB 0
#define RDMA_REGION_14__NEXT_LSB 0
#define RDMA_REGION_14__NEXT_MASK 0x00000001
#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
#define RDMA_REGION_15__ADDRESS 0x0000005c
#define RDMA_REGION_15__OFFSET 0x0000005c
#define RDMA_REGION_15__ADDR_MSB 31
#define RDMA_REGION_15__ADDR_LSB 13
#define RDMA_REGION_15__ADDR_MASK 0xffffe000
#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
#define RDMA_REGION_15__LENGTH_MSB 12
#define RDMA_REGION_15__LENGTH_LSB 2
#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc
#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
#define RDMA_REGION_15__INDI_MSB 1
#define RDMA_REGION_15__INDI_LSB 1
#define RDMA_REGION_15__INDI_MASK 0x00000002
#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
#define RDMA_REGION_15__NEXT_MSB 0
#define RDMA_REGION_15__NEXT_LSB 0
#define RDMA_REGION_15__NEXT_MASK 0x00000001
#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
#define DMA_STATUS_ADDRESS 0x00000060
#define DMA_STATUS_OFFSET 0x00000060
#define DMA_STATUS_ERROR_CODE_MSB 14
#define DMA_STATUS_ERROR_CODE_LSB 4
#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0
#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
#define DMA_STATUS_ERROR_MSB 3
#define DMA_STATUS_ERROR_LSB 3
#define DMA_STATUS_ERROR_MASK 0x00000008
#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
#define DMA_STATUS_DONE_MSB 2
#define DMA_STATUS_DONE_LSB 2
#define DMA_STATUS_DONE_MASK 0x00000004
#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
#define DMA_STATUS_STOPPED_MSB 1
#define DMA_STATUS_STOPPED_LSB 1
#define DMA_STATUS_STOPPED_MASK 0x00000002
#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
#define DMA_STATUS_RUNNING_MSB 0
#define DMA_STATUS_RUNNING_LSB 0
#define DMA_STATUS_RUNNING_MASK 0x00000001
#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
#define DMA_INT_EN_ADDRESS 0x00000064
#define DMA_INT_EN_OFFSET 0x00000064
#define DMA_INT_EN_ERROR_ENA_MSB 3
#define DMA_INT_EN_ERROR_ENA_LSB 3
#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008
#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
#define DMA_INT_EN_DONE_ENA_MSB 2
#define DMA_INT_EN_DONE_ENA_LSB 2
#define DMA_INT_EN_DONE_ENA_MASK 0x00000004
#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
#define DMA_INT_EN_STOPPED_ENA_MSB 1
#define DMA_INT_EN_STOPPED_ENA_LSB 1
#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002
#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
#ifndef __ASSEMBLER__
typedef struct rdma_reg_reg_s {
volatile unsigned int dma_config;
volatile unsigned int dma_control;
volatile unsigned int dma_src;
volatile unsigned int dma_dest;
volatile unsigned int dma_length;
volatile unsigned int vmc_base;
volatile unsigned int indirect_reg;
volatile unsigned int indirect_return;
volatile unsigned int rdma_region_0_;
volatile unsigned int rdma_region_1_;
volatile unsigned int rdma_region_2_;
volatile unsigned int rdma_region_3_;
volatile unsigned int rdma_region_4_;
volatile unsigned int rdma_region_5_;
volatile unsigned int rdma_region_6_;
volatile unsigned int rdma_region_7_;
volatile unsigned int rdma_region_8_;
volatile unsigned int rdma_region_9_;
volatile unsigned int rdma_region_10_;
volatile unsigned int rdma_region_11_;
volatile unsigned int rdma_region_12_;
volatile unsigned int rdma_region_13_;
volatile unsigned int rdma_region_14_;
volatile unsigned int rdma_region_15_;
volatile unsigned int dma_status;
volatile unsigned int dma_int_en;
} rdma_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _RDMA_REG_H_ */

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@ -0,0 +1,975 @@
// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "rtc_wlan_reg.h"
#ifndef BT_HEADERS
#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
#define RESET_CONTROL_OFFSET WLAN_RESET_CONTROL_OFFSET
#define RESET_CONTROL_DEBUG_UART_RST_MSB WLAN_RESET_CONTROL_DEBUG_UART_RST_MSB
#define RESET_CONTROL_DEBUG_UART_RST_LSB WLAN_RESET_CONTROL_DEBUG_UART_RST_LSB
#define RESET_CONTROL_DEBUG_UART_RST_MASK WLAN_RESET_CONTROL_DEBUG_UART_RST_MASK
#define RESET_CONTROL_DEBUG_UART_RST_GET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_GET(x)
#define RESET_CONTROL_DEBUG_UART_RST_SET(x) WLAN_RESET_CONTROL_DEBUG_UART_RST_SET(x)
#define RESET_CONTROL_BB_COLD_RST_MSB WLAN_RESET_CONTROL_BB_COLD_RST_MSB
#define RESET_CONTROL_BB_COLD_RST_LSB WLAN_RESET_CONTROL_BB_COLD_RST_LSB
#define RESET_CONTROL_BB_COLD_RST_MASK WLAN_RESET_CONTROL_BB_COLD_RST_MASK
#define RESET_CONTROL_BB_COLD_RST_GET(x) WLAN_RESET_CONTROL_BB_COLD_RST_GET(x)
#define RESET_CONTROL_BB_COLD_RST_SET(x) WLAN_RESET_CONTROL_BB_COLD_RST_SET(x)
#define RESET_CONTROL_BB_WARM_RST_MSB WLAN_RESET_CONTROL_BB_WARM_RST_MSB
#define RESET_CONTROL_BB_WARM_RST_LSB WLAN_RESET_CONTROL_BB_WARM_RST_LSB
#define RESET_CONTROL_BB_WARM_RST_MASK WLAN_RESET_CONTROL_BB_WARM_RST_MASK
#define RESET_CONTROL_BB_WARM_RST_GET(x) WLAN_RESET_CONTROL_BB_WARM_RST_GET(x)
#define RESET_CONTROL_BB_WARM_RST_SET(x) WLAN_RESET_CONTROL_BB_WARM_RST_SET(x)
#define RESET_CONTROL_CPU_INIT_RESET_MSB WLAN_RESET_CONTROL_CPU_INIT_RESET_MSB
#define RESET_CONTROL_CPU_INIT_RESET_LSB WLAN_RESET_CONTROL_CPU_INIT_RESET_LSB
#define RESET_CONTROL_CPU_INIT_RESET_MASK WLAN_RESET_CONTROL_CPU_INIT_RESET_MASK
#define RESET_CONTROL_CPU_INIT_RESET_GET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_GET(x)
#define RESET_CONTROL_CPU_INIT_RESET_SET(x) WLAN_RESET_CONTROL_CPU_INIT_RESET_SET(x)
#define RESET_CONTROL_VMC_REMAP_RESET_MSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_MSB
#define RESET_CONTROL_VMC_REMAP_RESET_LSB WLAN_RESET_CONTROL_VMC_REMAP_RESET_LSB
#define RESET_CONTROL_VMC_REMAP_RESET_MASK WLAN_RESET_CONTROL_VMC_REMAP_RESET_MASK
#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_GET(x)
#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) WLAN_RESET_CONTROL_VMC_REMAP_RESET_SET(x)
#define RESET_CONTROL_RST_OUT_MSB WLAN_RESET_CONTROL_RST_OUT_MSB
#define RESET_CONTROL_RST_OUT_LSB WLAN_RESET_CONTROL_RST_OUT_LSB
#define RESET_CONTROL_RST_OUT_MASK WLAN_RESET_CONTROL_RST_OUT_MASK
#define RESET_CONTROL_RST_OUT_GET(x) WLAN_RESET_CONTROL_RST_OUT_GET(x)
#define RESET_CONTROL_RST_OUT_SET(x) WLAN_RESET_CONTROL_RST_OUT_SET(x)
#define RESET_CONTROL_COLD_RST_MSB WLAN_RESET_CONTROL_COLD_RST_MSB
#define RESET_CONTROL_COLD_RST_LSB WLAN_RESET_CONTROL_COLD_RST_LSB
#define RESET_CONTROL_COLD_RST_MASK WLAN_RESET_CONTROL_COLD_RST_MASK
#define RESET_CONTROL_COLD_RST_GET(x) WLAN_RESET_CONTROL_COLD_RST_GET(x)
#define RESET_CONTROL_COLD_RST_SET(x) WLAN_RESET_CONTROL_COLD_RST_SET(x)
#define RESET_CONTROL_WARM_RST_MSB WLAN_RESET_CONTROL_WARM_RST_MSB
#define RESET_CONTROL_WARM_RST_LSB WLAN_RESET_CONTROL_WARM_RST_LSB
#define RESET_CONTROL_WARM_RST_MASK WLAN_RESET_CONTROL_WARM_RST_MASK
#define RESET_CONTROL_WARM_RST_GET(x) WLAN_RESET_CONTROL_WARM_RST_GET(x)
#define RESET_CONTROL_WARM_RST_SET(x) WLAN_RESET_CONTROL_WARM_RST_SET(x)
#define RESET_CONTROL_CPU_WARM_RST_MSB WLAN_RESET_CONTROL_CPU_WARM_RST_MSB
#define RESET_CONTROL_CPU_WARM_RST_LSB WLAN_RESET_CONTROL_CPU_WARM_RST_LSB
#define RESET_CONTROL_CPU_WARM_RST_MASK WLAN_RESET_CONTROL_CPU_WARM_RST_MASK
#define RESET_CONTROL_CPU_WARM_RST_GET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_GET(x)
#define RESET_CONTROL_CPU_WARM_RST_SET(x) WLAN_RESET_CONTROL_CPU_WARM_RST_SET(x)
#define RESET_CONTROL_MAC_COLD_RST_MSB WLAN_RESET_CONTROL_MAC_COLD_RST_MSB
#define RESET_CONTROL_MAC_COLD_RST_LSB WLAN_RESET_CONTROL_MAC_COLD_RST_LSB
#define RESET_CONTROL_MAC_COLD_RST_MASK WLAN_RESET_CONTROL_MAC_COLD_RST_MASK
#define RESET_CONTROL_MAC_COLD_RST_GET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_GET(x)
#define RESET_CONTROL_MAC_COLD_RST_SET(x) WLAN_RESET_CONTROL_MAC_COLD_RST_SET(x)
#define RESET_CONTROL_MAC_WARM_RST_MSB WLAN_RESET_CONTROL_MAC_WARM_RST_MSB
#define RESET_CONTROL_MAC_WARM_RST_LSB WLAN_RESET_CONTROL_MAC_WARM_RST_LSB
#define RESET_CONTROL_MAC_WARM_RST_MASK WLAN_RESET_CONTROL_MAC_WARM_RST_MASK
#define RESET_CONTROL_MAC_WARM_RST_GET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_GET(x)
#define RESET_CONTROL_MAC_WARM_RST_SET(x) WLAN_RESET_CONTROL_MAC_WARM_RST_SET(x)
#define RESET_CONTROL_MBOX_RST_MSB WLAN_RESET_CONTROL_MBOX_RST_MSB
#define RESET_CONTROL_MBOX_RST_LSB WLAN_RESET_CONTROL_MBOX_RST_LSB
#define RESET_CONTROL_MBOX_RST_MASK WLAN_RESET_CONTROL_MBOX_RST_MASK
#define RESET_CONTROL_MBOX_RST_GET(x) WLAN_RESET_CONTROL_MBOX_RST_GET(x)
#define RESET_CONTROL_MBOX_RST_SET(x) WLAN_RESET_CONTROL_MBOX_RST_SET(x)
#define RESET_CONTROL_UART_RST_MSB WLAN_RESET_CONTROL_UART_RST_MSB
#define RESET_CONTROL_UART_RST_LSB WLAN_RESET_CONTROL_UART_RST_LSB
#define RESET_CONTROL_UART_RST_MASK WLAN_RESET_CONTROL_UART_RST_MASK
#define RESET_CONTROL_UART_RST_GET(x) WLAN_RESET_CONTROL_UART_RST_GET(x)
#define RESET_CONTROL_UART_RST_SET(x) WLAN_RESET_CONTROL_UART_RST_SET(x)
#define RESET_CONTROL_SI0_RST_MSB WLAN_RESET_CONTROL_SI0_RST_MSB
#define RESET_CONTROL_SI0_RST_LSB WLAN_RESET_CONTROL_SI0_RST_LSB
#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
#define CPU_CLOCK_STANDARD_LSB WLAN_CPU_CLOCK_STANDARD_LSB
#define CPU_CLOCK_STANDARD_MASK WLAN_CPU_CLOCK_STANDARD_MASK
#define CPU_CLOCK_STANDARD_GET(x) WLAN_CPU_CLOCK_STANDARD_GET(x)
#define CPU_CLOCK_STANDARD_SET(x) WLAN_CPU_CLOCK_STANDARD_SET(x)
#define CLOCK_OUT_ADDRESS WLAN_CLOCK_OUT_ADDRESS
#define CLOCK_OUT_OFFSET WLAN_CLOCK_OUT_OFFSET
#define CLOCK_OUT_SELECT_MSB WLAN_CLOCK_OUT_SELECT_MSB
#define CLOCK_OUT_SELECT_LSB WLAN_CLOCK_OUT_SELECT_LSB
#define CLOCK_OUT_SELECT_MASK WLAN_CLOCK_OUT_SELECT_MASK
#define CLOCK_OUT_SELECT_GET(x) WLAN_CLOCK_OUT_SELECT_GET(x)
#define CLOCK_OUT_SELECT_SET(x) WLAN_CLOCK_OUT_SELECT_SET(x)
#define CLOCK_CONTROL_ADDRESS WLAN_CLOCK_CONTROL_ADDRESS
#define CLOCK_CONTROL_OFFSET WLAN_CLOCK_CONTROL_OFFSET
#define CLOCK_CONTROL_LF_CLK32_MSB WLAN_CLOCK_CONTROL_LF_CLK32_MSB
#define CLOCK_CONTROL_LF_CLK32_LSB WLAN_CLOCK_CONTROL_LF_CLK32_LSB
#define CLOCK_CONTROL_LF_CLK32_MASK WLAN_CLOCK_CONTROL_LF_CLK32_MASK
#define CLOCK_CONTROL_LF_CLK32_GET(x) WLAN_CLOCK_CONTROL_LF_CLK32_GET(x)
#define CLOCK_CONTROL_LF_CLK32_SET(x) WLAN_CLOCK_CONTROL_LF_CLK32_SET(x)
#define CLOCK_CONTROL_SI0_CLK_MSB WLAN_CLOCK_CONTROL_SI0_CLK_MSB
#define CLOCK_CONTROL_SI0_CLK_LSB WLAN_CLOCK_CONTROL_SI0_CLK_LSB
#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
#define WDT_ADDRESS WLAN_WDT_ADDRESS
#define WDT_OFFSET WLAN_WDT_OFFSET
#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
#define RESET_CAUSE_LAST_LSB WLAN_RESET_CAUSE_LAST_LSB
#define RESET_CAUSE_LAST_MASK WLAN_RESET_CAUSE_LAST_MASK
#define RESET_CAUSE_LAST_GET(x) WLAN_RESET_CAUSE_LAST_GET(x)
#define RESET_CAUSE_LAST_SET(x) WLAN_RESET_CAUSE_LAST_SET(x)
#define SYSTEM_SLEEP_ADDRESS WLAN_SYSTEM_SLEEP_ADDRESS
#define SYSTEM_SLEEP_OFFSET WLAN_SYSTEM_SLEEP_OFFSET
#define SYSTEM_SLEEP_HOST_IF_MSB WLAN_SYSTEM_SLEEP_HOST_IF_MSB
#define SYSTEM_SLEEP_HOST_IF_LSB WLAN_SYSTEM_SLEEP_HOST_IF_LSB
#define SYSTEM_SLEEP_HOST_IF_MASK WLAN_SYSTEM_SLEEP_HOST_IF_MASK
#define SYSTEM_SLEEP_HOST_IF_GET(x) WLAN_SYSTEM_SLEEP_HOST_IF_GET(x)
#define SYSTEM_SLEEP_HOST_IF_SET(x) WLAN_SYSTEM_SLEEP_HOST_IF_SET(x)
#define SYSTEM_SLEEP_MBOX_MSB WLAN_SYSTEM_SLEEP_MBOX_MSB
#define SYSTEM_SLEEP_MBOX_LSB WLAN_SYSTEM_SLEEP_MBOX_LSB
#define SYSTEM_SLEEP_MBOX_MASK WLAN_SYSTEM_SLEEP_MBOX_MASK
#define SYSTEM_SLEEP_MBOX_GET(x) WLAN_SYSTEM_SLEEP_MBOX_GET(x)
#define SYSTEM_SLEEP_MBOX_SET(x) WLAN_SYSTEM_SLEEP_MBOX_SET(x)
#define SYSTEM_SLEEP_MAC_IF_MSB WLAN_SYSTEM_SLEEP_MAC_IF_MSB
#define SYSTEM_SLEEP_MAC_IF_LSB WLAN_SYSTEM_SLEEP_MAC_IF_LSB
#define SYSTEM_SLEEP_MAC_IF_MASK WLAN_SYSTEM_SLEEP_MAC_IF_MASK
#define SYSTEM_SLEEP_MAC_IF_GET(x) WLAN_SYSTEM_SLEEP_MAC_IF_GET(x)
#define SYSTEM_SLEEP_MAC_IF_SET(x) WLAN_SYSTEM_SLEEP_MAC_IF_SET(x)
#define SYSTEM_SLEEP_LIGHT_MSB WLAN_SYSTEM_SLEEP_LIGHT_MSB
#define SYSTEM_SLEEP_LIGHT_LSB WLAN_SYSTEM_SLEEP_LIGHT_LSB
#define SYSTEM_SLEEP_LIGHT_MASK WLAN_SYSTEM_SLEEP_LIGHT_MASK
#define SYSTEM_SLEEP_LIGHT_GET(x) WLAN_SYSTEM_SLEEP_LIGHT_GET(x)
#define SYSTEM_SLEEP_LIGHT_SET(x) WLAN_SYSTEM_SLEEP_LIGHT_SET(x)
#define SYSTEM_SLEEP_DISABLE_MSB WLAN_SYSTEM_SLEEP_DISABLE_MSB
#define SYSTEM_SLEEP_DISABLE_LSB WLAN_SYSTEM_SLEEP_DISABLE_LSB
#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
#define LPO_INIT_DIVIDEND_INT_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB
#define LPO_INIT_DIVIDEND_INT_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK
#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x)
#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x)
#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS
#define LPO_INIT_DIVIDEND_FRACTION_OFFSET WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x)
#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x)
#define LPO_CAL_ADDRESS WLAN_LPO_CAL_ADDRESS
#define LPO_CAL_OFFSET WLAN_LPO_CAL_OFFSET
#define LPO_CAL_ENABLE_MSB WLAN_LPO_CAL_ENABLE_MSB
#define LPO_CAL_ENABLE_LSB WLAN_LPO_CAL_ENABLE_LSB
#define LPO_CAL_ENABLE_MASK WLAN_LPO_CAL_ENABLE_MASK
#define LPO_CAL_ENABLE_GET(x) WLAN_LPO_CAL_ENABLE_GET(x)
#define LPO_CAL_ENABLE_SET(x) WLAN_LPO_CAL_ENABLE_SET(x)
#define LPO_CAL_COUNT_MSB WLAN_LPO_CAL_COUNT_MSB
#define LPO_CAL_COUNT_LSB WLAN_LPO_CAL_COUNT_LSB
#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
#endif
#endif

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h Normal file
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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _SI_REG_REG_H_
#define _SI_REG_REG_H_
#define SI_CONFIG_ADDRESS 0x00000000
#define SI_CONFIG_OFFSET 0x00000000
#define SI_CONFIG_ERR_INT_MSB 19
#define SI_CONFIG_ERR_INT_LSB 19
#define SI_CONFIG_ERR_INT_MASK 0x00080000
#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
#define SI_CONFIG_I2C_MSB 16
#define SI_CONFIG_I2C_LSB 16
#define SI_CONFIG_I2C_MASK 0x00010000
#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
#define SI_CONFIG_POS_SAMPLE_MSB 7
#define SI_CONFIG_POS_SAMPLE_LSB 7
#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
#define SI_CONFIG_POS_DRIVE_MSB 6
#define SI_CONFIG_POS_DRIVE_LSB 6
#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
#define SI_CONFIG_INACTIVE_DATA_MSB 5
#define SI_CONFIG_INACTIVE_DATA_LSB 5
#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
#define SI_CONFIG_INACTIVE_CLK_MSB 4
#define SI_CONFIG_INACTIVE_CLK_LSB 4
#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
#define SI_CONFIG_DIVIDER_MSB 3
#define SI_CONFIG_DIVIDER_LSB 0
#define SI_CONFIG_DIVIDER_MASK 0x0000000f
#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
#define SI_CS_ADDRESS 0x00000004
#define SI_CS_OFFSET 0x00000004
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
#define SI_CS_DONE_ERR_MSB 10
#define SI_CS_DONE_ERR_LSB 10
#define SI_CS_DONE_ERR_MASK 0x00000400
#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
#define SI_CS_DONE_INT_MSB 9
#define SI_CS_DONE_INT_LSB 9
#define SI_CS_DONE_INT_MASK 0x00000200
#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
#define SI_CS_START_MSB 8
#define SI_CS_START_LSB 8
#define SI_CS_START_MASK 0x00000100
#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
#define SI_CS_RX_CNT_MSB 7
#define SI_CS_RX_CNT_LSB 4
#define SI_CS_RX_CNT_MASK 0x000000f0
#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
#define SI_CS_TX_CNT_MSB 3
#define SI_CS_TX_CNT_LSB 0
#define SI_CS_TX_CNT_MASK 0x0000000f
#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
#define SI_TX_DATA0_ADDRESS 0x00000008
#define SI_TX_DATA0_OFFSET 0x00000008
#define SI_TX_DATA0_DATA3_MSB 31
#define SI_TX_DATA0_DATA3_LSB 24
#define SI_TX_DATA0_DATA3_MASK 0xff000000
#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
#define SI_TX_DATA0_DATA2_MSB 23
#define SI_TX_DATA0_DATA2_LSB 16
#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
#define SI_TX_DATA0_DATA1_MSB 15
#define SI_TX_DATA0_DATA1_LSB 8
#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
#define SI_TX_DATA0_DATA0_MSB 7
#define SI_TX_DATA0_DATA0_LSB 0
#define SI_TX_DATA0_DATA0_MASK 0x000000ff
#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
#define SI_TX_DATA1_ADDRESS 0x0000000c
#define SI_TX_DATA1_OFFSET 0x0000000c
#define SI_TX_DATA1_DATA7_MSB 31
#define SI_TX_DATA1_DATA7_LSB 24
#define SI_TX_DATA1_DATA7_MASK 0xff000000
#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
#define SI_TX_DATA1_DATA6_MSB 23
#define SI_TX_DATA1_DATA6_LSB 16
#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
#define SI_TX_DATA1_DATA5_MSB 15
#define SI_TX_DATA1_DATA5_LSB 8
#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
#define SI_TX_DATA1_DATA4_MSB 7
#define SI_TX_DATA1_DATA4_LSB 0
#define SI_TX_DATA1_DATA4_MASK 0x000000ff
#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
#define SI_RX_DATA0_ADDRESS 0x00000010
#define SI_RX_DATA0_OFFSET 0x00000010
#define SI_RX_DATA0_DATA3_MSB 31
#define SI_RX_DATA0_DATA3_LSB 24
#define SI_RX_DATA0_DATA3_MASK 0xff000000
#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
#define SI_RX_DATA0_DATA2_MSB 23
#define SI_RX_DATA0_DATA2_LSB 16
#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
#define SI_RX_DATA0_DATA1_MSB 15
#define SI_RX_DATA0_DATA1_LSB 8
#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
#define SI_RX_DATA0_DATA0_MSB 7
#define SI_RX_DATA0_DATA0_LSB 0
#define SI_RX_DATA0_DATA0_MASK 0x000000ff
#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
#define SI_RX_DATA1_ADDRESS 0x00000014
#define SI_RX_DATA1_OFFSET 0x00000014
#define SI_RX_DATA1_DATA7_MSB 31
#define SI_RX_DATA1_DATA7_LSB 24
#define SI_RX_DATA1_DATA7_MASK 0xff000000
#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
#define SI_RX_DATA1_DATA6_MSB 23
#define SI_RX_DATA1_DATA6_LSB 16
#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
#define SI_RX_DATA1_DATA5_MSB 15
#define SI_RX_DATA1_DATA5_LSB 8
#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
#define SI_RX_DATA1_DATA4_MSB 7
#define SI_RX_DATA1_DATA4_LSB 0
#define SI_RX_DATA1_DATA4_MASK 0x000000ff
#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
#ifndef __ASSEMBLER__
typedef struct si_reg_reg_s {
volatile unsigned int si_config;
volatile unsigned int si_cs;
volatile unsigned int si_tx_data0;
volatile unsigned int si_tx_data1;
volatile unsigned int si_rx_data0;
volatile unsigned int si_rx_data1;
} si_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _SI_REG_H_ */

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _UART_REG_REG_H_
#define _UART_REG_REG_H_
#define UART_DATA_ADDRESS 0x00000000
#define UART_DATA_OFFSET 0x00000000
#define UART_DATA_TX_CSR_MSB 9
#define UART_DATA_TX_CSR_LSB 9
#define UART_DATA_TX_CSR_MASK 0x00000200
#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
#define UART_DATA_RX_CSR_MSB 8
#define UART_DATA_RX_CSR_LSB 8
#define UART_DATA_RX_CSR_MASK 0x00000100
#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
#define UART_DATA_TXRX_DATA_MSB 7
#define UART_DATA_TXRX_DATA_LSB 0
#define UART_DATA_TXRX_DATA_MASK 0x000000ff
#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
#define UART_CONTROL_ADDRESS 0x00000004
#define UART_CONTROL_OFFSET 0x00000004
#define UART_CONTROL_RX_BUSY_MSB 15
#define UART_CONTROL_RX_BUSY_LSB 15
#define UART_CONTROL_RX_BUSY_MASK 0x00008000
#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
#define UART_CONTROL_TX_BUSY_MSB 14
#define UART_CONTROL_TX_BUSY_LSB 14
#define UART_CONTROL_TX_BUSY_MASK 0x00004000
#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
#define UART_CONTROL_HOST_INT_ENABLE_MSB 13
#define UART_CONTROL_HOST_INT_ENABLE_LSB 13
#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000
#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
#define UART_CONTROL_HOST_INT_MSB 12
#define UART_CONTROL_HOST_INT_LSB 12
#define UART_CONTROL_HOST_INT_MASK 0x00001000
#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
#define UART_CONTROL_TX_BREAK_MSB 11
#define UART_CONTROL_TX_BREAK_LSB 11
#define UART_CONTROL_TX_BREAK_MASK 0x00000800
#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
#define UART_CONTROL_RX_BREAK_MSB 10
#define UART_CONTROL_RX_BREAK_LSB 10
#define UART_CONTROL_RX_BREAK_MASK 0x00000400
#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
#define UART_CONTROL_SERIAL_TX_READY_MSB 9
#define UART_CONTROL_SERIAL_TX_READY_LSB 9
#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200
#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
#define UART_CONTROL_TX_READY_ORIDE_MSB 8
#define UART_CONTROL_TX_READY_ORIDE_LSB 8
#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100
#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
#define UART_CONTROL_RX_READY_ORIDE_MSB 7
#define UART_CONTROL_RX_READY_ORIDE_LSB 7
#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080
#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
#define UART_CONTROL_DMA_ENABLE_MSB 6
#define UART_CONTROL_DMA_ENABLE_LSB 6
#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040
#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
#define UART_CONTROL_FLOW_ENABLE_MSB 5
#define UART_CONTROL_FLOW_ENABLE_LSB 5
#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020
#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
#define UART_CONTROL_FLOW_INVERT_MSB 4
#define UART_CONTROL_FLOW_INVERT_LSB 4
#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010
#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
#define UART_CONTROL_IFC_ENABLE_MSB 3
#define UART_CONTROL_IFC_ENABLE_LSB 3
#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008
#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
#define UART_CONTROL_IFC_DCE_MSB 2
#define UART_CONTROL_IFC_DCE_LSB 2
#define UART_CONTROL_IFC_DCE_MASK 0x00000004
#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
#define UART_CONTROL_PARITY_ENABLE_MSB 1
#define UART_CONTROL_PARITY_ENABLE_LSB 1
#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002
#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
#define UART_CONTROL_PARITY_EVEN_MSB 0
#define UART_CONTROL_PARITY_EVEN_LSB 0
#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001
#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
#define UART_CLKDIV_ADDRESS 0x00000008
#define UART_CLKDIV_OFFSET 0x00000008
#define UART_CLKDIV_CLK_SCALE_MSB 23
#define UART_CLKDIV_CLK_SCALE_LSB 16
#define UART_CLKDIV_CLK_SCALE_MASK 0x00ff0000
#define UART_CLKDIV_CLK_SCALE_GET(x) (((x) & UART_CLKDIV_CLK_SCALE_MASK) >> UART_CLKDIV_CLK_SCALE_LSB)
#define UART_CLKDIV_CLK_SCALE_SET(x) (((x) << UART_CLKDIV_CLK_SCALE_LSB) & UART_CLKDIV_CLK_SCALE_MASK)
#define UART_CLKDIV_CLK_STEP_MSB 15
#define UART_CLKDIV_CLK_STEP_LSB 0
#define UART_CLKDIV_CLK_STEP_MASK 0x0000ffff
#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
#define UART_INT_ADDRESS 0x0000000c
#define UART_INT_OFFSET 0x0000000c
#define UART_INT_TX_EMPTY_INT_MSB 9
#define UART_INT_TX_EMPTY_INT_LSB 9
#define UART_INT_TX_EMPTY_INT_MASK 0x00000200
#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
#define UART_INT_RX_FULL_INT_MSB 8
#define UART_INT_RX_FULL_INT_LSB 8
#define UART_INT_RX_FULL_INT_MASK 0x00000100
#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
#define UART_INT_RX_BREAK_OFF_INT_MSB 7
#define UART_INT_RX_BREAK_OFF_INT_LSB 7
#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080
#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
#define UART_INT_RX_BREAK_ON_INT_MSB 6
#define UART_INT_RX_BREAK_ON_INT_LSB 6
#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040
#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
#define UART_INT_RX_PARITY_ERR_INT_MSB 5
#define UART_INT_RX_PARITY_ERR_INT_LSB 5
#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020
#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
#define UART_INT_TX_OFLOW_ERR_INT_MSB 4
#define UART_INT_TX_OFLOW_ERR_INT_LSB 4
#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010
#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
#define UART_INT_RX_OFLOW_ERR_INT_MSB 3
#define UART_INT_RX_OFLOW_ERR_INT_LSB 3
#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008
#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
#define UART_INT_RX_FRAMING_ERR_INT_MSB 2
#define UART_INT_RX_FRAMING_ERR_INT_LSB 2
#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004
#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
#define UART_INT_TX_READY_INT_MSB 1
#define UART_INT_TX_READY_INT_LSB 1
#define UART_INT_TX_READY_INT_MASK 0x00000002
#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
#define UART_INT_RX_VALID_INT_MSB 0
#define UART_INT_RX_VALID_INT_LSB 0
#define UART_INT_RX_VALID_INT_MASK 0x00000001
#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
#define UART_INT_EN_ADDRESS 0x00000010
#define UART_INT_EN_OFFSET 0x00000010
#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9
#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9
#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200
#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
#define UART_INT_EN_RX_FULL_INT_EN_MSB 8
#define UART_INT_EN_RX_FULL_INT_EN_LSB 8
#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100
#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6
#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6
#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040
#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
#define UART_INT_EN_TX_READY_INT_EN_MSB 1
#define UART_INT_EN_TX_READY_INT_EN_LSB 1
#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002
#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
#define UART_INT_EN_RX_VALID_INT_EN_MSB 0
#define UART_INT_EN_RX_VALID_INT_EN_LSB 0
#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001
#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
#ifndef __ASSEMBLER__
typedef struct uart_reg_reg_s {
volatile unsigned int uart_data;
volatile unsigned int uart_control;
volatile unsigned int uart_clkdiv;
volatile unsigned int uart_int;
volatile unsigned int uart_int_en;
} uart_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UART_REG_H_ */

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "umbox_wlan_reg.h"
#ifndef BT_HEADERS
#endif
#endif

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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _UMBOX_WLAN_REG_REG_H_
#define _UMBOX_WLAN_REG_REG_H_
#define UMBOX_FIFO_ADDRESS 0x00000000
#define UMBOX_FIFO_OFFSET 0x00000000
#define UMBOX_FIFO_DATA_MSB 8
#define UMBOX_FIFO_DATA_LSB 0
#define UMBOX_FIFO_DATA_MASK 0x000001ff
#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
#define UMBOX_FIFO_STATUS_OFFSET 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
#define UMBOX_DMA_POLICY_OFFSET 0x0000000c
#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_RX_CONTROL_START_MSB 1
#define UMBOX0_DMA_RX_CONTROL_START_LSB 1
#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
#define UMBOX0_DMA_TX_CONTROL_START_MSB 1
#define UMBOX0_DMA_TX_CONTROL_START_LSB 1
#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
#define UMBOX_INT_STATUS_ADDRESS 0x00000024
#define UMBOX_INT_STATUS_OFFSET 0x00000024
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
#define UMBOX_INT_ENABLE_ADDRESS 0x00000028
#define UMBOX_INT_ENABLE_OFFSET 0x00000028
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
#define UMBOX_DEBUG_ADDRESS 0x0000002c
#define UMBOX_DEBUG_OFFSET 0x0000002c
#define UMBOX_DEBUG_SEL_MSB 2
#define UMBOX_DEBUG_SEL_LSB 0
#define UMBOX_DEBUG_SEL_MASK 0x00000007
#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
#define UMBOX_FIFO_RESET_ADDRESS 0x00000030
#define UMBOX_FIFO_RESET_OFFSET 0x00000030
#define UMBOX_FIFO_RESET_INIT_MSB 0
#define UMBOX_FIFO_RESET_INIT_LSB 0
#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
#define UMBOX_HCI_FRAMER_OFFSET 0x00000034
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
#define UMBOX_HCI_FRAMER_ENABLE_MSB 5
#define UMBOX_HCI_FRAMER_ENABLE_LSB 5
#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
#ifndef __ASSEMBLER__
typedef struct umbox_wlan_reg_reg_s {
volatile unsigned int umbox_fifo[2];
volatile unsigned int umbox_fifo_status;
volatile unsigned int umbox_dma_policy;
volatile unsigned int umbox0_dma_rx_descriptor_base;
volatile unsigned int umbox0_dma_rx_control;
volatile unsigned int umbox0_dma_tx_descriptor_base;
volatile unsigned int umbox0_dma_tx_control;
volatile unsigned int umbox_fifo_timeout;
volatile unsigned int umbox_int_status;
volatile unsigned int umbox_int_enable;
volatile unsigned int umbox_debug;
volatile unsigned int umbox_fifo_reset;
volatile unsigned int umbox_hci_framer;
} umbox_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _UMBOX_WLAN_REG_H_ */

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifdef WLAN_HEADERS
#include "vmc_wlan_reg.h"
#ifndef BT_HEADERS
#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
#endif
#endif

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drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h Normal file
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// ------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
// ------------------------------------------------------------------
//===================================================================
// Author(s): ="Atheros"
//===================================================================
#ifndef _VMC_WLAN_REG_REG_H_
#define _VMC_WLAN_REG_REG_H_
#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000
#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000
#define WLAN_MC_BCAM_VALID_BIT_MSB 0
#define WLAN_MC_BCAM_VALID_BIT_LSB 0
#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001
#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200
#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200
#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19
#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2
#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc
#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400
#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400
#define WLAN_MC_BCAM_TARGET_INST_MSB 31
#define WLAN_MC_BCAM_TARGET_INST_LSB 0
#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff
#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600
#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604
#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608
#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c
#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610
#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614
#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614
#define WLAN_CPU_PERF_CNT_EN_MSB 0
#define WLAN_CPU_PERF_CNT_EN_LSB 0
#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001
#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618
#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618
#define WLAN_CPU_INST_FETCH_CNT_MSB 31
#define WLAN_CPU_INST_FETCH_CNT_LSB 0
#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff
#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c
#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c
#define WLAN_CPU_DATA_FETCH_CNT_MSB 31
#define WLAN_CPU_DATA_FETCH_CNT_LSB 0
#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff
#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620
#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620
#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624
#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624
#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628
#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628
#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c
#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c
#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11
#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0
#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff
#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
#ifndef __ASSEMBLER__
typedef struct vmc_wlan_reg_reg_s {
volatile unsigned int wlan_mc_bcam_valid[128];
volatile unsigned int wlan_mc_bcam_compare[128];
volatile unsigned int wlan_mc_bcam_target[128];
volatile unsigned int wlan_apb_addr_error_control;
volatile unsigned int wlan_apb_addr_error_status;
volatile unsigned int wlan_ahb_addr_error_control;
volatile unsigned int wlan_ahb_addr_error_status;
volatile unsigned int wlan_bcam_conflict_error;
volatile unsigned int wlan_cpu_perf_cnt;
volatile unsigned int wlan_cpu_inst_fetch;
volatile unsigned int wlan_cpu_data_fetch;
volatile unsigned int wlan_cpu_ram1_conflict;
volatile unsigned int wlan_cpu_ram2_conflict;
volatile unsigned int wlan_cpu_ram3_conflict;
volatile unsigned int wlan_cpu_ram4_conflict;
} vmc_wlan_reg_reg_t;
#endif /* __ASSEMBLER__ */
#endif /* _VMC_WLAN_REG_H_ */

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//-
// Copyright (c) 2009-2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
//
#ifndef __A_HCI_H__
#define __A_HCI_H__
#define HCI_CMD_OGF_MASK 0x3F
#define HCI_CMD_OGF_SHIFT 10
#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
#define HCI_CMD_OCF_MASK 0x3FF
#define HCI_CMD_OCF_SHIFT 0
#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
(ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
/*======== HCI Opcode groups ===============*/
#define OGF_NOP 0x00
#define OGF_LINK_CONTROL 0x01
#define OGF_LINK_POLICY 0x03
#define OGF_INFO_PARAMS 0x04
#define OGF_STATUS 0x05
#define OGF_TESTING 0x06
#define OGF_BLUETOOTH 0x3E
#define OGF_VENDOR_DEBUG 0x3F
#define OCF_NOP 0x00
/*===== Link Control Commands Opcode===================*/
#define OCF_HCI_Create_Physical_Link 0x35
#define OCF_HCI_Accept_Physical_Link_Req 0x36
#define OCF_HCI_Disconnect_Physical_Link 0x37
#define OCF_HCI_Create_Logical_Link 0x38
#define OCF_HCI_Accept_Logical_Link 0x39
#define OCF_HCI_Disconnect_Logical_Link 0x3A
#define OCF_HCI_Logical_Link_Cancel 0x3B
#define OCF_HCI_Flow_Spec_Modify 0x3C
/*===== Link Policy Commands Opcode====================*/
#define OCF_HCI_Set_Event_Mask 0x01
#define OCF_HCI_Reset 0x03
#define OCF_HCI_Read_Conn_Accept_Timeout 0x15
#define OCF_HCI_Write_Conn_Accept_Timeout 0x16
#define OCF_HCI_Read_Link_Supervision_Timeout 0x36
#define OCF_HCI_Write_Link_Supervision_Timeout 0x37
#define OCF_HCI_Enhanced_Flush 0x5F
#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61
#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62
#define OCF_HCI_Set_Event_Mask_Page_2 0x63
#define OCF_HCI_Read_Location_Data 0x64
#define OCF_HCI_Write_Location_Data 0x65
#define OCF_HCI_Read_Flow_Control_Mode 0x66
#define OCF_HCI_Write_Flow_Control_Mode 0x67
#define OCF_HCI_Read_BE_Flush_Timeout 0x69
#define OCF_HCI_Write_BE_Flush_Timeout 0x6A
#define OCF_HCI_Short_Range_Mode 0x6B
/*======== Info Commands Opcode========================*/
#define OCF_HCI_Read_Local_Ver_Info 0x01
#define OCF_HCI_Read_Local_Supported_Cmds 0x02
#define OCF_HCI_Read_Data_Block_Size 0x0A
/*======== Status Commands Opcode======================*/
#define OCF_HCI_Read_Failed_Contact_Counter 0x01
#define OCF_HCI_Reset_Failed_Contact_Counter 0x02
#define OCF_HCI_Read_Link_Quality 0x03
#define OCF_HCI_Read_RSSI 0x05
#define OCF_HCI_Read_Local_AMP_Info 0x09
#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A
#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B
/*======= AMP_ASSOC Specific TLV tags =================*/
#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1
#define AMP_ASSOC_PREF_CHAN_LIST 0x2
#define AMP_ASSOC_CONNECTED_CHAN 0x3
#define AMP_ASSOC_PAL_CAPABILITIES 0x4
#define AMP_ASSOC_PAL_VERSION 0x5
/*========= PAL Events =================================*/
#define PAL_COMMAND_COMPLETE_EVENT 0x0E
#define PAL_COMMAND_STATUS_EVENT 0x0F
#define PAL_HARDWARE_ERROR_EVENT 0x10
#define PAL_FLUSH_OCCURRED_EVENT 0x11
#define PAL_LOOPBACK_EVENT 0x19
#define PAL_BUFFER_OVERFLOW_EVENT 0x1A
#define PAL_QOS_VIOLATION_EVENT 0x1E
#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39
#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40
#define PAL_CHANNEL_SELECT_EVENT 0x41
#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42
#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43
#define PAL_PHY_LINK_RECOVERY_EVENT 0x44
#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45
#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46
#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47
#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48
#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C
#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D
/*======== End of PAL events definiton =================*/
/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
#define Timer_Conn_Accept_TO 0x01
#define Timer_Link_Supervision_TO 0x02
#define NUM_HCI_COMMAND_PKTS 0x1
/*====== NOP Cmd ============================*/
#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
/*===== Link Control Commands================*/
#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
/*===== Link Policy Commands ================*/
#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)
/*===== Info Commands =====================*/
#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS)
#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
/*===== Status Commands =====================*/
#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
/*====== End of cmd definitions =============*/
/*===== Timeouts(private - can't come from HCI)=================*/
#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
/*----- PAL Constants (Sec 6 of Doc)------------------------*/
#define Max80211_PAL_PDU_Size 1492
#define Max80211_AMP_ASSOC_Len 672
#define MinGUserPrio 4
#define MaxGUserPrio 7
#define BEUserPrio0 0
#define BEUserPrio1 3
#define Max80211BeaconPeriod 2000 /* in millisec */
#define ShortRangeModePowerMax 4 /* dBm */
/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
typedef enum {
ACL_DATA = 0x01,
ACTIVITY_REPORT,
SECURED_FRAMES,
LINK_SUPERVISION_REQ,
LINK_SUPERVISION_RESP,
}PAL_PROTOCOL_IDENTIFIERS;
#define HCI_CMD_HDR_SZ 3
#define HCI_EVENT_HDR_SIZE 2
#define MAX_EVT_PKT_SZ 255
#define AMP_ASSOC_MAX_FRAG_SZ 248
#define AMP_MAX_GUARANTEED_BW 20000
#define DEFAULT_CONN_ACCPT_TO 5000
#define DEFAULT_LL_ACCPT_TO 5000
#define DEFAULT_LSTO 10000
#define PACKET_BASED_FLOW_CONTROL_MODE 0x00
#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01
#define SERVICE_TYPE_BEST_EFFORT 0x01
#define SERVICE_TYPE_GUARANTEED 0x02
#define MAC_ADDR_LEN 6
#define LINK_KEY_LEN 32
typedef enum {
ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
ACL_DATA_PB_COMPLETE_PDU = 0x03,
} ACL_DATA_PB_FLAGS;
#define ACL_DATA_PB_FLAGS_SHIFT 12
typedef enum {
ACL_DATA_BC_POINT_TO_POINT = 0x00,
} ACL_DATA_BC_FLAGS;
#define ACL_DATA_BC_FLAGS_SHIFT 14
/* Command pkt */
typedef struct hci_cmd_pkt_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 params[255];
} POSTPACK HCI_CMD_PKT;
#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */
/* Data pkt */
typedef struct hci_acl_data_pkt_t {
A_UINT16 hdl_and_flags;
A_UINT16 data_len;
A_UINT8 data[Max80211_PAL_PDU_Size];
} POSTPACK HCI_ACL_DATA_PKT;
/* Event pkt */
typedef struct hci_event_pkt_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 params[256];
} POSTPACK HCI_EVENT_PKT;
/*============== HCI Command definitions ======================= */
typedef struct hci_cmd_phy_link_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
A_UINT8 link_key_len;
A_UINT8 link_key_type;
A_UINT8 link_key[LINK_KEY_LEN];
} POSTPACK HCI_CMD_PHY_LINK;
typedef struct hci_cmd_write_rem_amp_assoc_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
A_UINT16 len_so_far;
A_UINT16 amp_assoc_remaining_len;
A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
typedef struct hci_cmd_opcode_hdl_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 hdl;
} POSTPACK HCI_CMD_READ_LINK_QUAL,
HCI_CMD_FLUSH,
HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
typedef struct hci_cmd_read_local_amp_assoc_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
A_UINT16 len_so_far;
A_UINT16 max_rem_amp_assoc_len;
} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
typedef struct hci_cmd_set_event_mask_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT64 mask;
}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
typedef struct hci_cmd_enhanced_flush_t{
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 hdl;
A_UINT8 type;
} POSTPACK HCI_CMD_ENHANCED_FLUSH;
typedef struct hci_cmd_write_timeout_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 timeout;
} POSTPACK HCI_CMD_WRITE_TIMEOUT;
typedef struct hci_cmd_write_link_supervision_timeout_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 hdl;
A_UINT16 timeout;
} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
typedef struct hci_cmd_write_flow_control_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 mode;
} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL;
typedef struct location_data_cfg_t {
A_UINT8 reg_domain_aware;
A_UINT8 reg_domain[3];
A_UINT8 reg_options;
} POSTPACK LOCATION_DATA_CFG;
typedef struct hci_cmd_write_location_data_t {
A_UINT16 opcode;
A_UINT8 param_length;
LOCATION_DATA_CFG cfg;
} POSTPACK HCI_CMD_WRITE_LOCATION_DATA;
typedef struct flow_spec_t {
A_UINT8 id;
A_UINT8 service_type;
A_UINT16 max_sdu;
A_UINT32 sdu_inter_arrival_time;
A_UINT32 access_latency;
A_UINT32 flush_timeout;
} POSTPACK FLOW_SPEC;
typedef struct hci_cmd_create_logical_link_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
FLOW_SPEC tx_flow_spec;
FLOW_SPEC rx_flow_spec;
} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
typedef struct hci_cmd_flow_spec_modify_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 hdl;
FLOW_SPEC tx_flow_spec;
FLOW_SPEC rx_flow_spec;
} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
typedef struct hci_cmd_logical_link_cancel_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
A_UINT8 tx_flow_spec_id;
} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
typedef struct hci_cmd_disconnect_logical_link_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT16 logical_link_hdl;
} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
typedef struct hci_cmd_disconnect_phy_link_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
typedef struct hci_cmd_srm_t {
A_UINT16 opcode;
A_UINT8 param_length;
A_UINT8 phy_link_hdl;
A_UINT8 mode;
} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
/*============== HCI Command definitions end ======================= */
/*============== HCI Event definitions ============================= */
/* Command complete event */
typedef struct hci_event_cmd_complete_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 num_hci_cmd_pkts;
A_UINT16 opcode;
A_UINT8 params[255];
} POSTPACK HCI_EVENT_CMD_COMPLETE;
/* Command status event */
typedef struct hci_event_cmd_status_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT8 num_hci_cmd_pkts;
A_UINT16 opcode;
} POSTPACK HCI_EVENT_CMD_STATUS;
/* Hardware Error event */
typedef struct hci_event_hw_err_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 hw_err_code;
} POSTPACK HCI_EVENT_HW_ERR;
/* Flush occured event */
/* Qos Violation event */
typedef struct hci_event_handle_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT16 handle;
} POSTPACK HCI_EVENT_FLUSH_OCCRD,
HCI_EVENT_QOS_VIOLATION;
/* Loopback command event */
typedef struct hci_loopback_cmd_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 params[252];
} POSTPACK HCI_EVENT_LOOPBACK_CMD;
/* Data buffer overflow event */
typedef struct hci_data_buf_overflow_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 link_type;
} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW;
/* Enhanced Flush complete event */
typedef struct hci_enhanced_flush_complt_t{
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT16 hdl;
} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT;
/* Channel select event */
typedef struct hci_event_chan_select_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 phy_link_hdl;
} POSTPACK HCI_EVENT_CHAN_SELECT;
/* Physical Link Complete event */
typedef struct hci_event_phy_link_complete_event_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT8 phy_link_hdl;
} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
/* Logical Link complete event */
typedef struct hci_event_logical_link_complete_event_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT16 logical_link_hdl;
A_UINT8 phy_hdl;
A_UINT8 tx_flow_id;
} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
/* Disconnect Logical Link complete event */
typedef struct hci_event_disconnect_logical_link_event_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT16 logical_link_hdl;
A_UINT8 reason;
} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
/* Disconnect Physical Link complete event */
typedef struct hci_event_disconnect_phy_link_complete_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT8 phy_link_hdl;
A_UINT8 reason;
} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
typedef struct hci_event_physical_link_loss_early_warning_t{
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 phy_hdl;
A_UINT8 reason;
} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
typedef struct hci_event_physical_link_recovery_t{
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 phy_hdl;
} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
/* Flow spec modify complete event */
/* Flush event */
typedef struct hci_event_status_handle_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT16 handle;
} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
HCI_EVENT_FLUSH;
/* Num of completed data blocks event */
typedef struct hci_event_num_of_compl_data_blks_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT16 num_data_blks;
A_UINT8 num_handles;
A_UINT8 params[255];
} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
/* Short range mode change complete event */
typedef struct hci_srm_cmpl_t {
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT8 phy_link;
A_UINT8 state;
} POSTPACK HCI_EVENT_SRM_COMPL;
typedef struct hci_event_amp_status_change_t{
A_UINT8 event_code;
A_UINT8 param_len;
A_UINT8 status;
A_UINT8 amp_status;
} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
/*============== Event definitions end =========================== */
typedef struct local_amp_info_resp_t {
A_UINT8 status;
A_UINT8 amp_status;
A_UINT32 total_bw; /* kbps */
A_UINT32 max_guranteed_bw; /* kbps */
A_UINT32 min_latency;
A_UINT32 max_pdu_size;
A_UINT8 amp_type;
A_UINT16 pal_capabilities;
A_UINT16 amp_assoc_len;
A_UINT32 max_flush_timeout; /* in ms */
A_UINT32 be_flush_timeout; /* in ms */
} POSTPACK LOCAL_AMP_INFO;
typedef struct amp_assoc_cmd_resp_t{
A_UINT8 status;
A_UINT8 phy_hdl;
A_UINT16 amp_assoc_len;
A_UINT8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
}POSTPACK AMP_ASSOC_CMD_RESP;
enum PAL_HCI_CMD_STATUS {
PAL_HCI_CMD_PROCESSED,
PAL_HCI_CMD_IGNORED
};
/*============= HCI Error Codes =======================*/
#define HCI_SUCCESS 0x00
#define HCI_ERR_UNKNOW_CMD 0x01
#define HCI_ERR_UNKNOWN_CONN_ID 0x02
#define HCI_ERR_HW_FAILURE 0x03
#define HCI_ERR_PAGE_TIMEOUT 0x04
#define HCI_ERR_AUTH_FAILURE 0x05
#define HCI_ERR_KEY_MISSING 0x06
#define HCI_ERR_MEM_CAP_EXECED 0x07
#define HCI_ERR_CON_TIMEOUT 0x08
#define HCI_ERR_CON_LIMIT_EXECED 0x09
#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B
#define HCI_ERR_COMMAND_DISALLOWED 0x0C
#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D
#define HCI_ERR_CONN_REJ_BY_SEC 0x0E
#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F
#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10
#define HCI_ERR_UNSUPPORT_FEATURE 0x11
#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12
#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13
#define HCI_ERR_CON_TERM_BY_HOST 0x16
#define HCI_ERR_UNSPECIFIED_ERROR 0x1F
#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25
#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27
#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C
#define HCI_ERR_QOS_REJECTED 0x2D
#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39
/*============= HCI Error Codes End =======================*/
/* Following are event return parameters.. part of HCI events
*/
typedef struct timeout_read_t {
A_UINT8 status;
A_UINT16 timeout;
}POSTPACK TIMEOUT_INFO;
typedef struct link_supervision_timeout_read_t {
A_UINT8 status;
A_UINT16 hdl;
A_UINT16 timeout;
}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
typedef struct status_hdl_t {
A_UINT8 status;
A_UINT16 hdl;
}POSTPACK INFO_STATUS_HDL;
typedef struct write_remote_amp_assoc_t{
A_UINT8 status;
A_UINT8 hdl;
}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
typedef struct read_loc_info_t {
A_UINT8 status;
LOCATION_DATA_CFG loc;
}POSTPACK READ_LOC_INFO;
typedef struct read_flow_ctrl_mode_t {
A_UINT8 status;
A_UINT8 mode;
}POSTPACK READ_FLWCTRL_INFO;
typedef struct read_data_blk_size_t {
A_UINT8 status;
A_UINT16 max_acl_data_pkt_len;
A_UINT16 data_block_len;
A_UINT16 total_num_data_blks;
}POSTPACK READ_DATA_BLK_SIZE_INFO;
/* Read Link quality info */
typedef struct link_qual_t {
A_UINT8 status;
A_UINT16 hdl;
A_UINT8 link_qual;
} POSTPACK READ_LINK_QUAL_INFO,
READ_RSSI_INFO;
typedef struct ll_cancel_resp_t {
A_UINT8 status;
A_UINT8 phy_link_hdl;
A_UINT8 tx_flow_spec_id;
} POSTPACK LL_CANCEL_RESP;
typedef struct read_local_ver_info_t {
A_UINT8 status;
A_UINT8 hci_version;
A_UINT16 hci_revision;
A_UINT8 pal_version;
A_UINT16 manf_name;
A_UINT16 pal_sub_ver;
} POSTPACK READ_LOCAL_VER_INFO;
#endif /* __A_HCI_H__ */

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//------------------------------------------------------------------------------
// <copyright file="athdefs.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __ATHDEFS_H__
#define __ATHDEFS_H__
/*
* This file contains definitions that may be used across both
* Host and Target software. Nothing here is module-dependent
* or platform-dependent.
*/
/*
* Generic error codes that can be used by hw, sta, ap, sim, dk
* and any other environments. Since these are enums, feel free to
* add any more codes that you need.
*/
typedef enum {
A_ERROR = -1, /* Generic error return */
A_OK = 0, /* success */
/* Following values start at 1 */
A_DEVICE_NOT_FOUND, /* not able to find PCI device */
A_NO_MEMORY, /* not able to allocate memory, not available */
A_MEMORY_NOT_AVAIL, /* memory region is not free for mapping */
A_NO_FREE_DESC, /* no free descriptors available */
A_BAD_ADDRESS, /* address does not match descriptor */
A_WIN_DRIVER_ERROR, /* used in NT_HW version, if problem at init */
A_REGS_NOT_MAPPED, /* registers not correctly mapped */
A_EPERM, /* Not superuser */
A_EACCES, /* Access denied */
A_ENOENT, /* No such entry, search failed, etc. */
A_EEXIST, /* The object already exists (can't create) */
A_EFAULT, /* Bad address fault */
A_EBUSY, /* Object is busy */
A_EINVAL, /* Invalid parameter */
A_EMSGSIZE, /* Inappropriate message buffer length */
A_ECANCELED, /* Operation canceled */
A_ENOTSUP, /* Operation not supported */
A_ECOMM, /* Communication error on send */
A_EPROTO, /* Protocol error */
A_ENODEV, /* No such device */
A_EDEVNOTUP, /* device is not UP */
A_NO_RESOURCE, /* No resources for requested operation */
A_HARDWARE, /* Hardware failure */
A_PENDING, /* Asynchronous routine; will send up results la
ter (typically in callback) */
A_EBADCHANNEL, /* The channel cannot be used */
A_DECRYPT_ERROR, /* Decryption error */
A_PHY_ERROR, /* RX PHY error */
A_CONSUMED /* Object was consumed */
} A_STATUS;
#define A_SUCCESS(x) (x == A_OK)
#define A_FAILED(x) (!A_SUCCESS(x))
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif /* __ATHDEFS_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Bootloader Messaging Interface (BMI)
*
* BMI is a very simple messaging interface used during initialization
* to read memory, write memory, execute code, and to define an
* application entry PC.
*
* It is used to download an application to AR6K, to provide
* patches to code that is already resident on AR6K, and generally
* to examine and modify state. The Host has an opportunity to use
* BMI only once during bootup. Once the Host issues a BMI_DONE
* command, this opportunity ends.
*
* The Host writes BMI requests to mailbox0, and reads BMI responses
* from mailbox0. BMI requests all begin with a command
* (see below for specific commands), and are followed by
* command-specific data.
*
* Flow control:
* The Host can only issue a command once the Target gives it a
* "BMI Command Credit", using AR6K Counter #4. As soon as the
* Target has completed a command, it issues another BMI Command
* Credit (so the Host can issue the next command).
*
* BMI handles all required Target-side cache flushing.
*/
/* Maximum data size used for BMI transfers */
#define BMI_DATASZ_MAX 256
/* BMI Commands */
#define BMI_NO_COMMAND 0
#define BMI_DONE 1
/*
* Semantics: Host is done using BMI
* Request format:
* A_UINT32 command (BMI_DONE)
* Response format: none
*/
#define BMI_READ_MEMORY 2
/*
* Semantics: Host reads AR6K memory
* Request format:
* A_UINT32 command (BMI_READ_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* Response format:
* A_UINT8 data[length]
*/
#define BMI_WRITE_MEMORY 3
/*
* Semantics: Host writes AR6K memory
* Request format:
* A_UINT32 command (BMI_WRITE_MEMORY)
* A_UINT32 address
* A_UINT32 length, at most BMI_DATASZ_MAX
* A_UINT8 data[length]
* Response format: none
*/
#define BMI_EXECUTE 4
/*
* Semantics: Causes AR6K to execute code
* Request format:
* A_UINT32 command (BMI_EXECUTE)
* A_UINT32 address
* A_UINT32 parameter
* Response format:
* A_UINT32 return value
*/
#define BMI_SET_APP_START 5
/*
* Semantics: Set Target application starting address
* Request format:
* A_UINT32 command (BMI_SET_APP_START)
* A_UINT32 address
* Response format: none
*/
#define BMI_READ_SOC_REGISTER 6
/*
* Semantics: Read a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_READ_REGISTER)
* A_UINT32 address
* Response format:
* A_UINT32 value
*/
#define BMI_WRITE_SOC_REGISTER 7
/*
* Semantics: Write a 32-bit Target SOC register.
* Request format:
* A_UINT32 command (BMI_WRITE_REGISTER)
* A_UINT32 address
* A_UINT32 value
*
* Response format: none
*/
#define BMI_GET_TARGET_ID 8
#define BMI_GET_TARGET_INFO 8
/*
* Semantics: Fetch the 4-byte Target information
* Request format:
* A_UINT32 command (BMI_GET_TARGET_ID/INFO)
* Response format1 (old firmware):
* A_UINT32 TargetVersionID
* Response format2 (newer firmware):
* A_UINT32 TARGET_VERSION_SENTINAL
* struct bmi_target_info;
*/
PREPACK struct bmi_target_info {
A_UINT32 target_info_byte_count; /* size of this structure */
A_UINT32 target_ver; /* Target Version ID */
A_UINT32 target_type; /* Target type */
} POSTPACK;
#define TARGET_VERSION_SENTINAL 0xffffffff
#define TARGET_TYPE_AR6001 1
#define TARGET_TYPE_AR6002 2
#define TARGET_TYPE_AR6003 3
#define BMI_ROMPATCH_INSTALL 9
/*
* Semantics: Install a ROM Patch.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_INSTALL)
* A_UINT32 Target ROM Address
* A_UINT32 Target RAM Address or Value (depending on Target Type)
* A_UINT32 Size, in bytes
* A_UINT32 Activate? 1-->activate;
* 0-->install but do not activate
* Response format:
* A_UINT32 PatchID
*/
#define BMI_ROMPATCH_UNINSTALL 10
/*
* Semantics: Uninstall a previously-installed ROM Patch,
* automatically deactivating, if necessary.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_UNINSTALL)
* A_UINT32 PatchID
*
* Response format: none
*/
#define BMI_ROMPATCH_ACTIVATE 11
/*
* Semantics: Activate a list of previously-installed ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_ACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_ROMPATCH_DEACTIVATE 12
/*
* Semantics: Deactivate a list of active ROM Patches.
* Request format:
* A_UINT32 command (BMI_ROMPATCH_DEACTIVATE)
* A_UINT32 rompatch_count
* A_UINT32 PatchID[rompatch_count]
*
* Response format: none
*/
#define BMI_LZ_STREAM_START 13
/*
* Semantics: Begin an LZ-compressed stream of input
* which is to be uncompressed by the Target to an
* output buffer at address. The output buffer must
* be sufficiently large to hold the uncompressed
* output from the compressed input stream. This BMI
* command should be followed by a series of 1 or more
* BMI_LZ_DATA commands.
* A_UINT32 command (BMI_LZ_STREAM_START)
* A_UINT32 address
* Note: Not supported on all versions of ROM firmware.
*/
#define BMI_LZ_DATA 14
/*
* Semantics: Host writes AR6K memory with LZ-compressed
* data which is uncompressed by the Target. This command
* must be preceded by a BMI_LZ_STREAM_START command. A series
* of BMI_LZ_DATA commands are considered part of a single
* input stream until another BMI_LZ_STREAM_START is issued.
* Request format:
* A_UINT32 command (BMI_LZ_DATA)
* A_UINT32 length (of compressed data),
* at most BMI_DATASZ_MAX
* A_UINT8 CompressedData[length]
* Response format: none
* Note: Not supported on all versions of ROM firmware.
*/
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __BMI_MSG_H__ */

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// Copyright (c) 2010 Atheros Communications Inc.
// All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
#ifndef BTCOEX_GPIO_H_
#define BTCOEX_GPIO_H_
#ifdef FPGA
#define GPIO_A (15)
#define GPIO_B (16)
#define GPIO_C (17)
#define GPIO_D (18)
#define GPIO_E (19)
#define GPIO_F (21)
#define GPIO_G (21)
#else
#define GPIO_A (0)
#define GPIO_B (5)
#define GPIO_C (6)
#define GPIO_D (7)
#define GPIO_E (7)
#define GPIO_F (7)
#define GPIO_G (7)
#endif
#define GPIO_DEBUG_WORD_1 (1<<GPIO_A)
#define GPIO_DEBUG_WORD_2 (1<<GPIO_B)
#define GPIO_DEBUG_WORD_3 ((1<<GPIO_B) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_4 (1<<GPIO_C)
#define GPIO_DEBUG_WORD_5 ((1<<GPIO_C) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_6 ((1<<GPIO_C) | (1<<GPIO_B))
#define GPIO_DEBUG_WORD_7 ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
#define GPIO_DEBUG_WORD_8 (1<<GPIO_D)
#define GPIO_DEBUG_WORD_9 ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
#define GPIO_DEBUG_WORD_10 ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
#define GPIO_DEBUG_WORD_11 ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
#define GPIO_DEBUG_WORD_12 ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
#define GPIO_DEBUG_WORD_13 ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
#define GPIO_DEBUG_WORD_14 ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
#define GPIO_DEBUG_WORD_15 ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
#define GPIO_DEBUG_WORD_16 (1<<GPIO_E)
#define GPIO_DEBUG_WORD_17 ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
#define GPIO_DEBUG_WORD_18 ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
#define GPIO_DEBUG_WORD_19 ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
#define GPIO_DEBUG_WORD_20 ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
#define GPIO_DEBUG_WORD_21 ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
#define GPIO_DEBUG_WORD_22 ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
#define GPIO_DEBUG_WORD_23 ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
extern void btcoexDbgPulseWord(A_UINT32 gpioPinMask);
extern void btcoexDbgPulse(A_UINT32 pin);
#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask))
#define BTCOEX_DBG_PULSE(pin) (btcoexDbgPulse(pin))
#else
#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
#define BTCOEX_DBG_PULSE(pin)
#endif
#endif

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//------------------------------------------------------------------------------
// <copyright file="cnxmgmt.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _CNXMGMT_H_
#define _CNXMGMT_H_
typedef enum {
CM_CONNECT_WITHOUT_SCAN = 0x0001,
CM_CONNECT_ASSOC_POLICY_USER = 0x0002,
CM_CONNECT_SEND_REASSOC = 0x0004,
CM_CONNECT_WITHOUT_ROAMTABLE_UPDATE = 0x0008,
CM_CONNECT_DO_WPA_OFFLOAD = 0x0010,
CM_CONNECT_DO_NOT_DEAUTH = 0x0020,
} CM_CONNECT_TYPE;
#endif /* _CNXMGMT_H_ */

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//------------------------------------------------------------------------------
// <copyright file="dbglog.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#define DBGLOG_TIMESTAMP_OFFSET 0
#define DBGLOG_TIMESTAMP_MASK 0x0000FFFF /* Bit 0-15. Contains bit
8-23 of the LF0 timer */
#define DBGLOG_DBGID_OFFSET 16
#define DBGLOG_DBGID_MASK 0x03FF0000 /* Bit 16-25 */
#define DBGLOG_DBGID_NUM_MAX 256 /* Upper limit is width of mask */
#define DBGLOG_MODULEID_OFFSET 26
#define DBGLOG_MODULEID_MASK 0x3C000000 /* Bit 26-29 */
#define DBGLOG_MODULEID_NUM_MAX 16 /* Upper limit is width of mask */
/*
* Please ensure that the definition of any new module intrduced is captured
* between the DBGLOG_MODULEID_START and DBGLOG_MODULEID_END defines. The
* structure is required for the parser to correctly pick up the values for
* different modules.
*/
#define DBGLOG_MODULEID_START
#define DBGLOG_MODULEID_INF 0
#define DBGLOG_MODULEID_WMI 1
#define DBGLOG_MODULEID_MISC 2
#define DBGLOG_MODULEID_PM 3
#define DBGLOG_MODULEID_TXRX_MGMTBUF 4
#define DBGLOG_MODULEID_TXRX_TXBUF 5
#define DBGLOG_MODULEID_TXRX_RXBUF 6
#define DBGLOG_MODULEID_WOW 7
#define DBGLOG_MODULEID_WHAL 8
#define DBGLOG_MODULEID_DC 9
#define DBGLOG_MODULEID_CO 10
#define DBGLOG_MODULEID_RO 11
#define DBGLOG_MODULEID_CM 12
#define DBGLOG_MODULEID_MGMT 13
#define DBGLOG_MODULEID_TMR 14
#define DBGLOG_MODULEID_BTCOEX 15
#define DBGLOG_MODULEID_END
#define DBGLOG_NUM_ARGS_OFFSET 30
#define DBGLOG_NUM_ARGS_MASK 0xC0000000 /* Bit 30-31 */
#define DBGLOG_NUM_ARGS_MAX 2 /* Upper limit is width of mask */
#define DBGLOG_MODULE_LOG_ENABLE_OFFSET 0
#define DBGLOG_MODULE_LOG_ENABLE_MASK 0x0000FFFF
#define DBGLOG_REPORTING_ENABLED_OFFSET 16
#define DBGLOG_REPORTING_ENABLED_MASK 0x00010000
#define DBGLOG_TIMESTAMP_RESOLUTION_OFFSET 17
#define DBGLOG_TIMESTAMP_RESOLUTION_MASK 0x000E0000
#define DBGLOG_REPORT_SIZE_OFFSET 20
#define DBGLOG_REPORT_SIZE_MASK 0x3FF00000
#define DBGLOG_LOG_BUFFER_SIZE 1500
#define DBGLOG_DBGID_DEFINITION_LEN_MAX 90
PREPACK struct dbglog_buf_s {
struct dbglog_buf_s *next;
A_UINT8 *buffer;
A_UINT32 bufsize;
A_UINT32 length;
A_UINT32 count;
A_UINT32 free;
} POSTPACK;
PREPACK struct dbglog_hdr_s {
struct dbglog_buf_s *dbuf;
A_UINT32 dropped;
} POSTPACK;
PREPACK struct dbglog_config_s {
A_UINT32 cfgvalid; /* Mask with valid config bits */
union {
/* TODO: Take care of endianness */
struct {
A_UINT32 mmask:16; /* Mask of modules with logging on */
A_UINT32 rep:1; /* Reporting enabled or not */
A_UINT32 tsr:3; /* Time stamp resolution. Def: 1 ms */
A_UINT32 size:10; /* Report size in number of messages */
A_UINT32 reserved:2;
} dbglog_config;
A_UINT32 value;
} u;
} POSTPACK;
#define cfgmmask u.dbglog_config.mmask
#define cfgrep u.dbglog_config.rep
#define cfgtsr u.dbglog_config.tsr
#define cfgsize u.dbglog_config.size
#define cfgvalue u.value
#ifdef __cplusplus
}
#endif
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* _DBGLOG_H_ */

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//------------------------------------------------------------------------------
// <copyright file="dbglog_id.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DBGLOG_ID_H_
#define _DBGLOG_ID_H_
#ifdef __cplusplus
extern "C" {
#endif
/*
* The nomenclature for the debug identifiers is MODULE_DESCRIPTION.
* Please ensure that the definition of any new debugid introduced is captured
* between the <MODULE>_DBGID_DEFINITION_START and
* <MODULE>_DBGID_DEFINITION_END defines. The structure is required for the
* parser to correctly pick up the values for different debug identifiers.
*/
/* INF debug identifier definitions */
#define INF_DBGID_DEFINITION_START
#define INF_ASSERTION_FAILED 1
#define INF_TARGET_ID 2
#define INF_DBGID_DEFINITION_END
/* WMI debug identifier definitions */
#define WMI_DBGID_DEFINITION_START
#define WMI_CMD_RX_XTND_PKT_TOO_SHORT 1
#define WMI_EXTENDED_CMD_NOT_HANDLED 2
#define WMI_CMD_RX_PKT_TOO_SHORT 3
#define WMI_CALLING_WMI_EXTENSION_FN 4
#define WMI_CMD_NOT_HANDLED 5
#define WMI_IN_SYNC 6
#define WMI_TARGET_WMI_SYNC_CMD 7
#define WMI_SET_SNR_THRESHOLD_PARAMS 8
#define WMI_SET_RSSI_THRESHOLD_PARAMS 9
#define WMI_SET_LQ_TRESHOLD_PARAMS 10
#define WMI_TARGET_CREATE_PSTREAM_CMD 11
#define WMI_WI_DTM_INUSE 12
#define WMI_TARGET_DELETE_PSTREAM_CMD 13
#define WMI_TARGET_IMPLICIT_DELETE_PSTREAM_CMD 14
#define WMI_TARGET_GET_BIT_RATE_CMD 15
#define WMI_GET_RATE_MASK_CMD_FIX_RATE_MASK_IS 16
#define WMI_TARGET_GET_AVAILABLE_CHANNELS_CMD 17
#define WMI_TARGET_GET_TX_PWR_CMD 18
#define WMI_FREE_EVBUF_WMIBUF 19
#define WMI_FREE_EVBUF_DATABUF 20
#define WMI_FREE_EVBUF_BADFLAG 21
#define WMI_HTC_RX_ERROR_DATA_PACKET 22
#define WMI_HTC_RX_SYNC_PAUSING_FOR_MBOX 23
#define WMI_INCORRECT_WMI_DATA_HDR_DROPPING_PKT 24
#define WMI_SENDING_READY_EVENT 25
#define WMI_SETPOWER_MDOE_TO_MAXPERF 26
#define WMI_SETPOWER_MDOE_TO_REC 27
#define WMI_BSSINFO_EVENT_FROM 28
#define WMI_TARGET_GET_STATS_CMD 29
#define WMI_SENDING_SCAN_COMPLETE_EVENT 30
#define WMI_SENDING_RSSI_INDB_THRESHOLD_EVENT 31
#define WMI_SENDING_RSSI_INDBM_THRESHOLD_EVENT 32
#define WMI_SENDING_LINK_QUALITY_THRESHOLD_EVENT 33
#define WMI_SENDING_ERROR_REPORT_EVENT 34
#define WMI_SENDING_CAC_EVENT 35
#define WMI_TARGET_GET_ROAM_TABLE_CMD 36
#define WMI_TARGET_GET_ROAM_DATA_CMD 37
#define WMI_SENDING_GPIO_INTR_EVENT 38
#define WMI_SENDING_GPIO_ACK_EVENT 39
#define WMI_SENDING_GPIO_DATA_EVENT 40
#define WMI_CMD_RX 41
#define WMI_CMD_RX_XTND 42
#define WMI_EVENT_SEND 43
#define WMI_EVENT_SEND_XTND 44
#define WMI_CMD_PARAMS_DUMP_START 45
#define WMI_CMD_PARAMS_DUMP_END 46
#define WMI_CMD_PARAMS 47
#define WMI_DBGID_DEFINITION_END
/* MISC debug identifier definitions */
#define MISC_DBGID_DEFINITION_START
#define MISC_WLAN_SCHEDULER_EVENT_REGISTER_ERROR 1
#define TLPM_INIT 2
#define TLPM_FILTER_POWER_STATE 3
#define TLPM_NOTIFY_NOT_IDLE 4
#define TLPM_TIMEOUT_IDLE_HANDLER 5
#define TLPM_TIMEOUT_WAKEUP_HANDLER 6
#define TLPM_WAKEUP_SIGNAL_HANDLER 7
#define TLPM_UNEXPECTED_GPIO_INTR_ERROR 8
#define TLPM_BREAK_ON_NOT_RECEIVED_ERROR 9
#define TLPM_BREAK_OFF_NOT_RECIVED_ERROR 10
#define TLPM_ACK_GPIO_INTR 11
#define TLPM_ON 12
#define TLPM_OFF 13
#define TLPM_WAKEUP_FROM_HOST 14
#define TLPM_WAKEUP_FROM_BT 15
#define TLPM_TX_BREAK_RECIVED 16
#define TLPM_IDLE_TIMER_NOT_RUNNING 17
#define MISC_DBGID_DEFINITION_END
/* TXRX debug identifier definitions */
#define TXRX_TXBUF_DBGID_DEFINITION_START
#define TXRX_TXBUF_ALLOCATE_BUF 1
#define TXRX_TXBUF_QUEUE_BUF_TO_MBOX 2
#define TXRX_TXBUF_QUEUE_BUF_TO_TXQ 3
#define TXRX_TXBUF_TXQ_DEPTH 4
#define TXRX_TXBUF_IBSS_QUEUE_TO_SFQ 5
#define TXRX_TXBUF_IBSS_QUEUE_TO_TXQ_FRM_SFQ 6
#define TXRX_TXBUF_INITIALIZE_TIMER 7
#define TXRX_TXBUF_ARM_TIMER 8
#define TXRX_TXBUF_DISARM_TIMER 9
#define TXRX_TXBUF_UNINITIALIZE_TIMER 10
#define TXRX_TXBUF_DBGID_DEFINITION_END
#define TXRX_RXBUF_DBGID_DEFINITION_START
#define TXRX_RXBUF_ALLOCATE_BUF 1
#define TXRX_RXBUF_QUEUE_TO_HOST 2
#define TXRX_RXBUF_QUEUE_TO_WLAN 3
#define TXRX_RXBUF_ZERO_LEN_BUF 4
#define TXRX_RXBUF_QUEUE_TO_HOST_LASTBUF_IN_RXCHAIN 5
#define TXRX_RXBUF_LASTBUF_IN_RXCHAIN_ZEROBUF 6
#define TXRX_RXBUF_QUEUE_EMPTY_QUEUE_TO_WLAN 7
#define TXRX_RXBUF_SEND_TO_RECV_MGMT 8
#define TXRX_RXBUF_SEND_TO_IEEE_LAYER 9
#define TXRX_RXBUF_REQUEUE_ERROR 10
#define TXRX_RXBUF_DBGID_DEFINITION_END
#define TXRX_MGMTBUF_DBGID_DEFINITION_START
#define TXRX_MGMTBUF_ALLOCATE_BUF 1
#define TXRX_MGMTBUF_ALLOCATE_SM_BUF 2
#define TXRX_MGMTBUF_ALLOCATE_RMBUF 3
#define TXRX_MGMTBUF_GET_BUF 4
#define TXRX_MGMTBUF_GET_SM_BUF 5
#define TXRX_MGMTBUF_QUEUE_BUF_TO_TXQ 6
#define TXRX_MGMTBUF_REAPED_BUF 7
#define TXRX_MGMTBUF_REAPED_SM_BUF 8
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_DRAIN 9
#define TXRX_MGMTBUF_WAIT_FOR_TXQ_SFQ_DRAIN 10
#define TXRX_MGMTBUF_ENQUEUE_INTO_DATA_SFQ 11
#define TXRX_MGMTBUF_DEQUEUE_FROM_DATA_SFQ 12
#define TXRX_MGMTBUF_PAUSE_DATA_TXQ 13
#define TXRX_MGMTBUF_RESUME_DATA_TXQ 14
#define TXRX_MGMTBUF_WAIT_FORTXQ_DRAIN_TIMEOUT 15
#define TXRX_MGMTBUF_DRAINQ 16
#define TXRX_MGMTBUF_INDICATE_Q_DRAINED 17
#define TXRX_MGMTBUF_ENQUEUE_INTO_HW_SFQ 18
#define TXRX_MGMTBUF_DEQUEUE_FROM_HW_SFQ 19
#define TXRX_MGMTBUF_PAUSE_HW_TXQ 20
#define TXRX_MGMTBUF_RESUME_HW_TXQ 21
#define TXRX_MGMTBUF_TEAR_DOWN_BA 22
#define TXRX_MGMTBUF_PROCESS_ADDBA_REQ 23
#define TXRX_MGMTBUF_PROCESS_DELBA 24
#define TXRX_MGMTBUF_PERFORM_BA 25
#define TXRX_MGMTBUF_WLAN_RESET_ON_ERROR 26
#define TXRX_MGMTBUF_DBGID_DEFINITION_END
/* PM (Power Module) debug identifier definitions */
#define PM_DBGID_DEFINITION_START
#define PM_INIT 1
#define PM_ENABLE 2
#define PM_SET_STATE 3
#define PM_SET_POWERMODE 4
#define PM_CONN_NOTIFY 5
#define PM_REF_COUNT_NEGATIVE 6
#define PM_INFRA_STA_APSD_ENABLE 7
#define PM_INFRA_STA_UPDATE_APSD_STATE 8
#define PM_CHAN_OP_REQ 9
#define PM_SET_MY_BEACON_POLICY 10
#define PM_SET_ALL_BEACON_POLICY 11
#define PM_INFRA_STA_SET_PM_PARAMS1 12
#define PM_INFRA_STA_SET_PM_PARAMS2 13
#define PM_ADHOC_SET_PM_CAPS_FAIL 14
#define PM_ADHOC_UNKNOWN_IBSS_ATTRIB_ID 15
#define PM_ADHOC_SET_PM_PARAMS 16
#define PM_ADHOC_STATE1 18
#define PM_ADHOC_STATE2 19
#define PM_ADHOC_CONN_MAP 20
#define PM_FAKE_SLEEP 21
#define PM_AP_STATE1 22
#define PM_AP_SET_PM_PARAMS 23
#define PM_DBGID_DEFINITION_END
/* Wake on Wireless debug identifier definitions */
#define WOW_DBGID_DEFINITION_START
#define WOW_INIT 1
#define WOW_GET_CONFIG_DSET 2
#define WOW_NO_CONFIG_DSET 3
#define WOW_INVALID_CONFIG_DSET 4
#define WOW_USE_DEFAULT_CONFIG 5
#define WOW_SETUP_GPIO 6
#define WOW_INIT_DONE 7
#define WOW_SET_GPIO_PIN 8
#define WOW_CLEAR_GPIO_PIN 9
#define WOW_SET_WOW_MODE_CMD 10
#define WOW_SET_HOST_MODE_CMD 11
#define WOW_ADD_WOW_PATTERN_CMD 12
#define WOW_NEW_WOW_PATTERN_AT_INDEX 13
#define WOW_DEL_WOW_PATTERN_CMD 14
#define WOW_LIST_CONTAINS_PATTERNS 15
#define WOW_GET_WOW_LIST_CMD 16
#define WOW_INVALID_FILTER_ID 17
#define WOW_INVALID_FILTER_LISTID 18
#define WOW_NO_VALID_FILTER_AT_ID 19
#define WOW_NO_VALID_LIST_AT_ID 20
#define WOW_NUM_PATTERNS_EXCEEDED 21
#define WOW_NUM_LISTS_EXCEEDED 22
#define WOW_GET_WOW_STATS 23
#define WOW_CLEAR_WOW_STATS 24
#define WOW_WAKEUP_HOST 25
#define WOW_EVENT_WAKEUP_HOST 26
#define WOW_EVENT_DISCARD 27
#define WOW_PATTERN_MATCH 28
#define WOW_PATTERN_NOT_MATCH 29
#define WOW_PATTERN_NOT_MATCH_OFFSET 30
#define WOW_DISABLED_HOST_ASLEEP 31
#define WOW_ENABLED_HOST_ASLEEP_NO_PATTERNS 32
#define WOW_ENABLED_HOST_ASLEEP_NO_MATCH_FOUND 33
#define WOW_DBGID_DEFINITION_END
/* WHAL debug identifier definitions */
#define WHAL_DBGID_DEFINITION_START
#define WHAL_ERROR_ANI_CONTROL 1
#define WHAL_ERROR_CHIP_TEST1 2
#define WHAL_ERROR_CHIP_TEST2 3
#define WHAL_ERROR_EEPROM_CHECKSUM 4
#define WHAL_ERROR_EEPROM_MACADDR 5
#define WHAL_ERROR_INTERRUPT_HIU 6
#define WHAL_ERROR_KEYCACHE_RESET 7
#define WHAL_ERROR_KEYCACHE_SET 8
#define WHAL_ERROR_KEYCACHE_TYPE 9
#define WHAL_ERROR_KEYCACHE_TKIPENTRY 10
#define WHAL_ERROR_KEYCACHE_WEPLENGTH 11
#define WHAL_ERROR_PHY_INVALID_CHANNEL 12
#define WHAL_ERROR_POWER_AWAKE 13
#define WHAL_ERROR_POWER_SET 14
#define WHAL_ERROR_RECV_STOPDMA 15
#define WHAL_ERROR_RECV_STOPPCU 16
#define WHAL_ERROR_RESET_CHANNF1 17
#define WHAL_ERROR_RESET_CHANNF2 18
#define WHAL_ERROR_RESET_PM 19
#define WHAL_ERROR_RESET_OFFSETCAL 20
#define WHAL_ERROR_RESET_RFGRANT 21
#define WHAL_ERROR_RESET_RXFRAME 22
#define WHAL_ERROR_RESET_STOPDMA 23
#define WHAL_ERROR_RESET_RECOVER 24
#define WHAL_ERROR_XMIT_COMPUTE 25
#define WHAL_ERROR_XMIT_NOQUEUE 26
#define WHAL_ERROR_XMIT_ACTIVEQUEUE 27
#define WHAL_ERROR_XMIT_BADTYPE 28
#define WHAL_ERROR_XMIT_STOPDMA 29
#define WHAL_ERROR_INTERRUPT_BB_PANIC 30
#define WHAL_ERROR_RESET_TXIQCAL 31
#define WHAL_ERROR_PAPRD_MAXGAIN_ABOVE_WINDOW 32
#define WHAL_DBGID_DEFINITION_END
/* DC debug identifier definitions */
#define DC_DBGID_DEFINITION_START
#define DC_SCAN_CHAN_START 1
#define DC_SCAN_CHAN_FINISH 2
#define DC_BEACON_RECEIVE7 3
#define DC_SSID_PROBE_CB 4
#define DC_SEND_NEXT_SSID_PROBE 5
#define DC_START_SEARCH 6
#define DC_CANCEL_SEARCH_CB 7
#define DC_STOP_SEARCH 8
#define DC_END_SEARCH 9
#define DC_MIN_CHDWELL_TIMEOUT 10
#define DC_START_SEARCH_CANCELED 11
#define DC_SET_POWER_MODE 12
#define DC_INIT 13
#define DC_SEARCH_OPPORTUNITY 14
#define DC_RECEIVED_ANY_BEACON 15
#define DC_RECEIVED_MY_BEACON 16
#define DC_PROFILE_IS_ADHOC_BUT_BSS_IS_INFRA 17
#define DC_PS_ENABLED_BUT_ATHEROS_IE_ABSENT 18
#define DC_BSS_ADHOC_CHANNEL_NOT_ALLOWED 19
#define DC_SET_BEACON_UPDATE 20
#define DC_BEACON_UPDATE_COMPLETE 21
#define DC_END_SEARCH_BEACON_UPDATE_COMP_CB 22
#define DC_BSSINFO_EVENT_DROPPED 23
#define DC_IEEEPS_ENABLED_BUT_ATIM_ABSENT 24
#define DC_DBGID_DEFINITION_END
/* CO debug identifier definitions */
#define CO_DBGID_DEFINITION_START
#define CO_INIT 1
#define CO_ACQUIRE_LOCK 2
#define CO_START_OP1 3
#define CO_START_OP2 4
#define CO_DRAIN_TX_COMPLETE_CB 5
#define CO_CHANGE_CHANNEL_CB 6
#define CO_RETURN_TO_HOME_CHANNEL 7
#define CO_FINISH_OP_TIMEOUT 8
#define CO_OP_END 9
#define CO_CANCEL_OP 10
#define CO_CHANGE_CHANNEL 11
#define CO_RELEASE_LOCK 12
#define CO_CHANGE_STATE 13
#define CO_DBGID_DEFINITION_END
/* RO debug identifier definitions */
#define RO_DBGID_DEFINITION_START
#define RO_REFRESH_ROAM_TABLE 1
#define RO_UPDATE_ROAM_CANDIDATE 2
#define RO_UPDATE_ROAM_CANDIDATE_CB 3
#define RO_UPDATE_ROAM_CANDIDATE_FINISH 4
#define RO_REFRESH_ROAM_TABLE_DONE 5
#define RO_PERIODIC_SEARCH_CB 6
#define RO_PERIODIC_SEARCH_TIMEOUT 7
#define RO_INIT 8
#define RO_BMISS_STATE1 9
#define RO_BMISS_STATE2 10
#define RO_SET_PERIODIC_SEARCH_ENABLE 11
#define RO_SET_PERIODIC_SEARCH_DISABLE 12
#define RO_ENABLE_SQ_THRESHOLD 13
#define RO_DISABLE_SQ_THRESHOLD 14
#define RO_ADD_BSS_TO_ROAM_TABLE 15
#define RO_SET_PERIODIC_SEARCH_MODE 16
#define RO_CONFIGURE_SQ_THRESHOLD1 17
#define RO_CONFIGURE_SQ_THRESHOLD2 18
#define RO_CONFIGURE_SQ_PARAMS 19
#define RO_LOW_SIGNAL_QUALITY_EVENT 20
#define RO_HIGH_SIGNAL_QUALITY_EVENT 21
#define RO_REMOVE_BSS_FROM_ROAM_TABLE 22
#define RO_UPDATE_CONNECTION_STATE_METRIC 23
#define RO_DBGID_DEFINITION_END
/* CM debug identifier definitions */
#define CM_DBGID_DEFINITION_START
#define CM_INITIATE_HANDOFF 1
#define CM_INITIATE_HANDOFF_CB 2
#define CM_CONNECT_EVENT 3
#define CM_DISCONNECT_EVENT 4
#define CM_INIT 5
#define CM_HANDOFF_SOURCE 6
#define CM_SET_HANDOFF_TRIGGERS 7
#define CM_CONNECT_REQUEST 8
#define CM_CONNECT_REQUEST_CB 9
#define CM_CONTINUE_SCAN_CB 10
#define CM_DBGID_DEFINITION_END
/* mgmt debug identifier definitions */
#define MGMT_DBGID_DEFINITION_START
#define KEYMGMT_CONNECTION_INIT 1
#define KEYMGMT_CONNECTION_COMPLETE 2
#define KEYMGMT_CONNECTION_CLOSE 3
#define KEYMGMT_ADD_KEY 4
#define MLME_NEW_STATE 5
#define MLME_CONN_INIT 6
#define MLME_CONN_COMPLETE 7
#define MLME_CONN_CLOSE 8
#define MGMT_DBGID_DEFINITION_END
/* TMR debug identifier definitions */
#define TMR_DBGID_DEFINITION_START
#define TMR_HANG_DETECTED 1
#define TMR_WDT_TRIGGERED 2
#define TMR_WDT_RESET 3
#define TMR_HANDLER_ENTRY 4
#define TMR_HANDLER_EXIT 5
#define TMR_SAVED_START 6
#define TMR_SAVED_END 7
#define TMR_DBGID_DEFINITION_END
/* BTCOEX debug identifier definitions */
#define BTCOEX_DBGID_DEFINITION_START
#define BTCOEX_STATUS_CMD 1
#define BTCOEX_PARAMS_CMD 2
#define BTCOEX_ANT_CONFIG 3
#define BTCOEX_COLOCATED_BT_DEVICE 4
#define BTCOEX_CLOSE_RANGE_SCO_ON 5
#define BTCOEX_CLOSE_RANGE_SCO_OFF 6
#define BTCOEX_CLOSE_RANGE_A2DP_ON 7
#define BTCOEX_CLOSE_RANGE_A2DP_OFF 8
#define BTCOEX_A2DP_PROTECT_ON 9
#define BTCOEX_A2DP_PROTECT_OFF 10
#define BTCOEX_SCO_PROTECT_ON 11
#define BTCOEX_SCO_PROTECT_OFF 12
#define BTCOEX_CLOSE_RANGE_DETECTOR_START 13
#define BTCOEX_CLOSE_RANGE_DETECTOR_STOP 14
#define BTCOEX_CLOSE_RANGE_TOGGLE 15
#define BTCOEX_CLOSE_RANGE_TOGGLE_RSSI_LRCNT 16
#define BTCOEX_CLOSE_RANGE_RSSI_THRESH 17
#define BTCOEX_CLOSE_RANGE_LOW_RATE_THRESH 18
#define BTCOEX_PTA_PRI_INTR_HANDLER 19
#define BTCOEX_PSPOLL_QUEUED 20
#define BTCOEX_PSPOLL_COMPLETE 21
#define BTCOEX_DBG_PM_AWAKE 22
#define BTCOEX_DBG_PM_SLEEP 23
#define BTCOEX_DBG_SCO_COEX_ON 24
#define BTCOEX_SCO_DATARECEIVE 25
#define BTCOEX_INTR_INIT 26
#define BTCOEX_PTA_PRI_DIFF 27
#define BTCOEX_TIM_NOTIFICATION 28
#define BTCOEX_SCO_WAKEUP_ON_DATA 29
#define BTCOEX_SCO_SLEEP 30
#define BTCOEX_SET_WEIGHTS 31
#define BTCOEX_SCO_DATARECEIVE_LATENCY_VAL 32
#define BTCOEX_SCO_MEASURE_TIME_DIFF 33
#define BTCOEX_SET_EOL_VAL 34
#define BTCOEX_OPT_DETECT_HANDLER 35
#define BTCOEX_SCO_TOGGLE_STATE 36
#define BTCOEX_SCO_STOMP 37
#define BTCOEX_NULL_COMP_CALLBACK 38
#define BTCOEX_RX_INCOMING 39
#define BTCOEX_RX_INCOMING_CTL 40
#define BTCOEX_RX_INCOMING_MGMT 41
#define BTCOEX_RX_INCOMING_DATA 42
#define BTCOEX_RTS_RECEPTION 43
#define BTCOEX_FRAME_PRI_LOW_RATE_THRES 44
#define BTCOEX_PM_FAKE_SLEEP 45
#define BTCOEX_ACL_COEX_STATUS 46
#define BTCOEX_ACL_COEX_DETECTION 47
#define BTCOEX_A2DP_COEX_STATUS 48
#define BTCOEX_SCO_STATUS 49
#define BTCOEX_WAKEUP_ON_DATA 50
#define BTCOEX_DATARECEIVE 51
#define BTCOEX_GET_MAX_AGGR_SIZE 53
#define BTCOEX_MAX_AGGR_AVAIL_TIME 54
#define BTCOEX_DBG_WBTIMER_INTR 55
#define BTCOEX_DBG_SCO_SYNC 57
#define BTCOEX_UPLINK_QUEUED_RATE 59
#define BTCOEX_DBG_UPLINK_ENABLE_EOL 60
#define BTCOEX_UPLINK_FRAME_DURATION 61
#define BTCOEX_UPLINK_SET_EOL 62
#define BTCOEX_DBG_EOL_EXPIRED 63
#define BTCOEX_DBG_DATA_COMPLETE 64
#define BTCOEX_UPLINK_QUEUED_TIMESTAMP 65
#define BTCOEX_DBG_DATA_COMPLETE_TIME 66
#define BTCOEX_DBG_A2DP_ROLE_IS_SLAVE 67
#define BTCOEX_DBG_A2DP_ROLE_IS_MASTER 68
#define BTCOEX_DBG_UPLINK_SEQ_NUM 69
#define BTCOEX_UPLINK_AGGR_SEQ 70
#define BTCOEX_DBG_TX_COMP_SEQ_NO 71
#define BTCOEX_DBG_MAX_AGGR_PAUSE_STATE 72
#define BTCOEX_DBG_ACL_TRAFFIC 73
#define BTCOEX_CURR_AGGR_PROP 74
#define BTCOEX_DBG_SCO_GET_PER_TIME_DIFF 75
#define BTCOEX_PSPOLL_PROCESS 76
#define BTCOEX_RETURN_FROM_MAC 77
#define BTCOEX_FREED_REQUEUED_CNT 78
#define BTCOEX_DBG_TOGGLE_LOW_RATES 79
#define BTCOEX_MAC_GOES_TO_SLEEP 80
#define BTCOEX_DBG_A2DP_NO_SYNC 81
#define BTCOEX_RETURN_FROM_MAC_HOLD_Q_INFO 82
#define BTCOEX_RETURN_FROM_MAC_AC 83
#define BTCOEX_DBG_DTIM_RECV 84
#define BTCOEX_IS_PRE_UPDATE 86
#define BTCOEX_ENQUEUED_BIT_MAP 87
#define BTCOEX_TX_COMPLETE_FIRST_DESC_STATS 88
#define BTCOEX_UPLINK_DESC 89
#define BTCOEX_SCO_GET_PER_FIRST_FRM_TIMESTAMP 90
#define BTCOEX_DBG_RECV_ACK 94
#define BTCOEX_DBG_ADDBA_INDICATION 95
#define BTCOEX_TX_COMPLETE_EOL_FAILED 96
#define BTCOEX_DBG_A2DP_USAGE_COMPLETE 97
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_HANDLER 98
#define BTCOEX_DBG_A2DP_SYNC_INTR 99
#define BTCOEX_DBG_A2DP_STOMP_FOR_BCN_RECEPTION 100
#define BTCOEX_FORM_AGGR_CURR_AGGR 101
#define BTCOEX_DBG_TOGGLE_A2DP_BURST_CNT 102
#define BTCOEX_DBG_BT_TRAFFIC 103
#define BTCOEX_DBG_STOMP_BT_TRAFFIC 104
#define BTCOEX_RECV_NULL 105
#define BTCOEX_DBG_A2DP_MASTER_BT_END 106
#define BTCOEX_DBG_A2DP_BT_START 107
#define BTCOEX_DBG_A2DP_SLAVE_BT_END 108
#define BTCOEX_DBG_A2DP_STOMP_BT 109
#define BTCOEX_DBG_GO_TO_SLEEP 110
#define BTCOEX_DBG_A2DP_PKT 111
#define BTCOEX_DBG_A2DP_PSPOLL_DATA_RECV 112
#define BTCOEX_DBG_A2DP_NULL 113
#define BTCOEX_DBG_UPLINK_DATA 114
#define BTCOEX_DBG_A2DP_STOMP_LOW_PRIO_NULL 115
#define BTCOEX_DBG_ADD_BA_RESP_TIMEOUT 116
#define BTCOEX_DBG_TXQ_STATE 117
#define BTCOEX_DBG_ALLOW_SCAN 118
#define BTCOEX_DBG_SCAN_REQUEST 119
#define BTCOEX_A2DP_SLEEP 127
#define BTCOEX_DBG_DATA_ACTIV_TIMEOUT 128
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_ON_MODE 129
#define BTCOEX_DBG_SWITCH_TO_PSPOLL_OFF_MODE 130
#define BTCOEX_DATARECEIVE_AGGR 131
#define BTCOEX_DBG_DATA_RECV_SLEEPING_PENDING 132
#define BTCOEX_DBG_DATARESP_TIMEOUT 133
#define BTCOEX_BDG_BMISS 134
#define BTCOEX_DBG_DATA_RECV_WAKEUP_TIM 135
#define BTCOEX_DBG_SECOND_BMISS 136
#define BTCOEX_DBG_SET_WLAN_STATE 138
#define BTCOEX_BDG_FIRST_BMISS 139
#define BTCOEX_DBG_A2DP_CHAN_OP 140
#define BTCOEX_DBG_A2DP_INTR 141
#define BTCOEX_DBG_BT_INQUIRY 142
#define BTCOEX_DBG_BT_INQUIRY_DATA_FETCH 143
#define BTCOEX_DBG_POST_INQUIRY_FINISH 144
#define BTCOEX_DBG_SCO_OPT_MODE_TIMER_HANDLER 145
#define BTCOEX_DBG_NULL_FRAME_SLEEP 146
#define BTCOEX_DBG_NULL_FRAME_AWAKE 147
#define BTCOEX_DBG_SET_AGGR_SIZE 152
#define BTCOEX_DBG_TEAR_BA_TIMEOUT 153
#define BTCOEX_DBG_MGMT_FRAME_SEQ_NO 154
#define BTCOEX_DBG_SCO_STOMP_HIGH_PRI 155
#define BTCOEX_DBG_COLOCATED_BT_DEV 156
#define BTCOEX_DBG_FE_ANT_TYPE 157
#define BTCOEX_DBG_BT_INQUIRY_CMD 158
#define BTCOEX_DBG_SCO_CONFIG 159
#define BTCOEX_DBG_SCO_PSPOLL_CONFIG 160
#define BTCOEX_DBG_SCO_OPTMODE_CONFIG 161
#define BTCOEX_DBG_A2DP_CONFIG 162
#define BTCOEX_DBG_A2DP_PSPOLL_CONFIG 163
#define BTCOEX_DBG_A2DP_OPTMODE_CONFIG 164
#define BTCOEX_DBG_ACLCOEX_CONFIG 165
#define BTCOEX_DBG_ACLCOEX_PSPOLL_CONFIG 166
#define BTCOEX_DBG_ACLCOEX_OPTMODE_CONFIG 167
#define BTCOEX_DBG_DEBUG_CMD 168
#define BTCOEX_DBG_SET_BT_OPERATING_STATUS 169
#define BTCOEX_DBG_GET_CONFIG 170
#define BTCOEX_DBG_GET_STATS 171
#define BTCOEX_DBG_BT_OPERATING_STATUS 172
#define BTCOEX_DBG_PERFORM_RECONNECT 173
#define BTCOEX_DBG_ACL_WLAN_MED 175
#define BTCOEX_DBG_ACL_BT_MED 176
#define BTCOEX_DBG_WLAN_CONNECT 177
#define BTCOEX_DBG_A2DP_DUAL_START 178
#define BTCOEX_DBG_PMAWAKE_NOTIFY 179
#define BTCOEX_DBG_BEACON_SCAN_ENABLE 180
#define BTCOEX_DBG_BEACON_SCAN_DISABLE 181
#define BTCOEX_DBG_RX_NOTIFY 182
#define BTCOEX_SCO_GET_PER_SECOND_FRM_TIMESTAMP 183
#define BTCOEX_DBG_TXQ_DETAILS 184
#define BTCOEX_DBG_SCO_STOMP_LOW_PRI 185
#define BTCOEX_DBG_A2DP_FORCE_SCAN 186
#define BTCOEX_DBG_DTIM_STOMP_COMP 187
#define BTCOEX_ACL_PRESENCE_TIMER 188
#define BTCOEX_DBGID_DEFINITION_END
#ifdef __cplusplus
}
#endif
#endif /* _DBGLOG_ID_H_ */

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//------------------------------------------------------------------------------
// <copyright file="discovery.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _DISCOVERY_H_
#define _DISCOVERY_H_
/*
* DC_SCAN_PRIORITY is an 8-bit bitmap of the scan priority of a channel
*/
typedef enum {
DEFAULT_SCPRI = 0x01,
POPULAR_SCPRI = 0x02,
SSIDS_SCPRI = 0x04,
PROF_SCPRI = 0x08,
} DC_SCAN_PRIORITY;
/* The following search type construct can be used to manipulate the behavior of the search module based on different bits set */
typedef enum {
SCAN_RESET = 0,
SCAN_ALL = (DEFAULT_SCPRI | POPULAR_SCPRI | \
SSIDS_SCPRI | PROF_SCPRI),
SCAN_POPULAR = (POPULAR_SCPRI | SSIDS_SCPRI | PROF_SCPRI),
SCAN_SSIDS = (SSIDS_SCPRI | PROF_SCPRI),
SCAN_PROF_MASK = (PROF_SCPRI),
SCAN_MULTI_CHANNEL = 0x000100,
SCAN_DETERMINISTIC = 0x000200,
SCAN_PROFILE_MATCH_TERMINATED = 0x000400,
SCAN_HOME_CHANNEL_SKIP = 0x000800,
SCAN_CHANNEL_LIST_CONTINUE = 0x001000,
SCAN_CURRENT_SSID_SKIP = 0x002000,
SCAN_ACTIVE_PROBE_DISABLE = 0x004000,
SCAN_CHANNEL_HINT_ONLY = 0x008000,
SCAN_ACTIVE_CHANNELS_ONLY = 0x010000,
SCAN_UNUSED1 = 0x020000, /* unused */
SCAN_PERIODIC = 0x040000,
SCAN_FIXED_DURATION = 0x080000,
SCAN_AP_ASSISTED = 0x100000,
} DC_SCAN_TYPE;
typedef enum {
BSS_REPORTING_DEFAULT = 0x0,
EXCLUDE_NON_SCAN_RESULTS = 0x1, /* Exclude results outside of scan */
} DC_BSS_REPORTING_POLICY;
typedef enum {
DC_IGNORE_WPAx_GROUP_CIPHER = 0x01,
DC_PROFILE_MATCH_DONE = 0x02,
DC_IGNORE_AAC_BEACON = 0x04,
DC_CSA_FOLLOW_BSS = 0x08,
} DC_PROFILE_FILTER;
#define DEFAULT_DC_PROFILE_FILTER (DC_CSA_FOLLOW_BSS)
#endif /* _DISCOVERY_H_ */

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//------------------------------------------------------------------------------
// <copyright file="dset_internal.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSET_INTERNAL_H__
#define __DSET_INTERNAL_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/*
* Internal dset definitions, common for DataSet layer.
*/
#define DSET_TYPE_STANDARD 0
#define DSET_TYPE_BPATCHED 1
#define DSET_TYPE_COMPRESSED 2
/* Dataset descriptor */
typedef PREPACK struct dset_descriptor_s {
struct dset_descriptor_s *next; /* List link. NULL only at the last
descriptor */
A_UINT16 id; /* Dset ID */
A_UINT16 size; /* Dset size. */
void *DataPtr; /* Pointer to raw data for standard
DataSet or pointer to original
dset_descriptor for patched
DataSet */
A_UINT32 data_type; /* DSET_TYPE_*, above */
void *AuxPtr; /* Additional data that might
needed for data_type. For
example, pointer to patch
Dataset descriptor for BPatch. */
} POSTPACK dset_descriptor_t;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSET_INTERNAL_H__ */

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//------------------------------------------------------------------------------
// <copyright file="dsetid.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __DSETID_H__
#define __DSETID_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* Well-known DataSet IDs */
#define DSETID_UNUSED 0x00000000
#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
#define DSETID_REGDB 0x00000002 /* Regulatory Database */
#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
/*
* Get DSETID for various reference clock speeds.
* For each speed there are three DataSets that correspond
* to the three columns of bank6 data (addr, 11a, 11b/g).
* This macro returns the dsetid of the first of those
* three DataSets.
*/
#define ANALOG_CONTROL_DATA_DSETID(refclk) \
(DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
/*
* There are TWO STARTUP_PATCH DataSets.
* DSETID_STARTUP_PATCH is historical, and was applied before BMI on
* earlier systems. On AR6002, it is applied after BMI, just like
* DSETID_STARTUP_PATCH2.
*/
#define DSETID_STARTUP_PATCH 0x00000026
#define DSETID_GPIO_CONFIG_PATCH 0x00000027
#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
#define DSETID_STARTUP_PATCH2 0x00000029
#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
#define DSETID_INI_DATA 0x00000100
/* Reserved for WHAL INI Tables: 0x100..0x11f */
#define DSETID_INI_DATA_END 0x0000011f
#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
end of a memory-based
DataSet Index */
#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
/*
* PATCH DataSet format:
* A list of patches, terminated by a patch with
* address=PATCH_END.
*
* This allows for patches to be stored in flash.
*/
PREPACK struct patch_s {
A_UINT32 *address;
A_UINT32 data;
} POSTPACK ;
/*
* Skip some patches. Can be used to erase a single patch in a
* patch DataSet without having to re-write the DataSet. May
* also be used to embed information for use by subsequent
* patch code. The "data" in a PATCH_SKIP tells how many
* bytes of length "patch_s" to skip.
*/
#define PATCH_SKIP ((A_UINT32 *)0x00000000)
/*
* Execute code at the address specified by "data".
* The address of the patch structure is passed as
* the one parameter.
*/
#define PATCH_CODE_ABS ((A_UINT32 *)0x00000001)
/*
* Same as PATCH_CODE_ABS, but treat "data" as an
* offset from the start of the patch word.
*/
#define PATCH_CODE_REL ((A_UINT32 *)0x00000002)
/* Mark the end of this patch DataSet. */
#define PATCH_END ((A_UINT32 *)0xffffffff)
/*
* A DataSet which contains a Binary Patch to some other DataSet
* uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
* Such a BPatch DataSet consists of BPatch metadata followed by
* the bdiff bytes. BPatch metadata consists of a single 32-bit
* word that contains the size of the BPatched final image.
*
* To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
* to create "diffs":
* bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
* Then add BPatch metadata to the start of "diffs".
*
* NB: There are some implementation-induced restrictions
* on which DataSets can be BPatched.
*/
#define DSETID_BPATCH_FLAG 0x80000000
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __DSETID_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//
/* This file contains shared definitions for the host/target endpoint ping test */
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(HTC_FRAME_HDR) + 3) & (~0x3)) - sizeof(HTC_FRAME_HDR))
#ifndef A_OFFSETOF
#define A_OFFSETOF(type,field) (int)(&(((type *)NULL)->field))
#endif
#define EPPING_RSVD_FILL 0xCC
#define HCI_RSVD_EXPECTED_PKT_TYPE_RECV_OFFSET 7
typedef PREPACK struct {
A_UINT8 _HCIRsvd[8]; /* reserved for HCI packet header (GMBOX) testing */
A_UINT8 StreamEcho_h; /* stream no. to echo this packet on (filled by host) */
A_UINT8 StreamEchoSent_t; /* stream no. packet was echoed to (filled by target)
When echoed: StreamEchoSent_t == StreamEcho_h */
A_UINT8 StreamRecv_t; /* stream no. that target received this packet on (filled by target) */
A_UINT8 StreamNo_h; /* stream number to send on (filled by host) */
A_UINT8 Magic_h[4]; /* magic number to filter for this packet on the host*/
A_UINT8 _rsvd[6]; /* reserved fields that must be set to a "reserved" value
since this packet maps to a 14-byte ethernet frame we want
to make sure ethertype field is set to something unknown */
A_UINT8 _pad[2]; /* padding for alignment */
A_UINT8 TimeStamp[8]; /* timestamp of packet (host or target) */
A_UINT32 HostContext_h; /* 4 byte host context, target echos this back */
A_UINT32 SeqNo; /* sequence number (set by host or target) */
A_UINT16 Cmd_h; /* ping command (filled by host) */
A_UINT16 CmdFlags_h; /* optional flags */
A_UINT8 CmdBuffer_h[8]; /* buffer for command (host -> target) */
A_UINT8 CmdBuffer_t[8]; /* buffer for command (target -> host) */
A_UINT16 DataLength; /* length of data */
A_UINT16 DataCRC; /* 16 bit CRC of data */
A_UINT16 HeaderCRC; /* header CRC (fields : StreamNo_h to end, minus HeaderCRC) */
} POSTPACK EPPING_HEADER;
#define EPPING_PING_MAGIC_0 0xAA
#define EPPING_PING_MAGIC_1 0x55
#define EPPING_PING_MAGIC_2 0xCE
#define EPPING_PING_MAGIC_3 0xEC
#define IS_EPPING_PACKET(pPkt) (((pPkt)->Magic_h[0] == EPPING_PING_MAGIC_0) && \
((pPkt)->Magic_h[1] == EPPING_PING_MAGIC_1) && \
((pPkt)->Magic_h[2] == EPPING_PING_MAGIC_2) && \
((pPkt)->Magic_h[3] == EPPING_PING_MAGIC_3))
#define SET_EPPING_PACKET_MAGIC(pPkt) { (pPkt)->Magic_h[0] = EPPING_PING_MAGIC_0; \
(pPkt)->Magic_h[1] = EPPING_PING_MAGIC_1; \
(pPkt)->Magic_h[2] = EPPING_PING_MAGIC_2; \
(pPkt)->Magic_h[3] = EPPING_PING_MAGIC_3;}
#define CMD_FLAGS_DATA_CRC (1 << 0) /* DataCRC field is valid */
#define CMD_FLAGS_DELAY_ECHO (1 << 1) /* delay the echo of the packet */
#define CMD_FLAGS_NO_DROP (1 << 2) /* do not drop at HTC layer no matter what the stream is */
#define IS_EPING_PACKET_NO_DROP(pPkt) ((pPkt)->CmdFlags_h & CMD_FLAGS_NO_DROP)
#define EPPING_CMD_ECHO_PACKET 1 /* echo packet test */
#define EPPING_CMD_RESET_RECV_CNT 2 /* reset recv count */
#define EPPING_CMD_CAPTURE_RECV_CNT 3 /* fetch recv count, 4-byte count returned in CmdBuffer_t */
#define EPPING_CMD_NO_ECHO 4 /* non-echo packet test (tx-only) */
#define EPPING_CMD_CONT_RX_START 5 /* continous RX packets, parameters are in CmdBuffer_h */
#define EPPING_CMD_CONT_RX_STOP 6 /* stop continuous RX packet transmission */
/* test command parameters may be no more than 8 bytes */
typedef PREPACK struct {
A_UINT16 BurstCnt; /* number of packets to burst together (for HTC 2.1 testing) */
A_UINT16 PacketLength; /* length of packet to generate including header */
A_UINT16 Flags; /* flags */
#define EPPING_CONT_RX_DATA_CRC (1 << 0) /* Add CRC to all data */
#define EPPING_CONT_RX_RANDOM_DATA (1 << 1) /* randomize the data pattern */
#define EPPING_CONT_RX_RANDOM_LEN (1 << 2) /* randomize the packet lengths */
} POSTPACK EPPING_CONT_RX_PARAMS;
#define EPPING_HDR_CRC_OFFSET A_OFFSETOF(EPPING_HEADER,StreamNo_h)
#define EPPING_HDR_BYTES_CRC (sizeof(EPPING_HEADER) - EPPING_HDR_CRC_OFFSET - (sizeof(A_UINT16)))
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /*EPPING_TEST_H_*/

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//------------------------------------------------------------------------------
// Copyright (c) 2009-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __GMBOXIF_H__
#define __GMBOXIF_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
/* GMBOX interface definitions */
#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
#define AR6K_GMBOX_CREDIT_SIZE_COUNTER 2 /* credit counter 2 is used to pass the size of each credit */
/* HCI UART transport definitions when used over GMBOX interface */
#define HCI_UART_COMMAND_PKT 0x01
#define HCI_UART_ACL_PKT 0x02
#define HCI_UART_SCO_PKT 0x03
#define HCI_UART_EVENT_PKT 0x04
/* definitions for BT HCI packets */
typedef PREPACK struct {
A_UINT16 Flags_ConnHandle;
A_UINT16 Length;
} POSTPACK BT_HCI_ACL_HEADER;
typedef PREPACK struct {
A_UINT16 Flags_ConnHandle;
A_UINT8 Length;
} POSTPACK BT_HCI_SCO_HEADER;
typedef PREPACK struct {
A_UINT16 OpCode;
A_UINT8 ParamLength;
} POSTPACK BT_HCI_COMMAND_HEADER;
typedef PREPACK struct {
A_UINT8 EventCode;
A_UINT8 ParamLength;
} POSTPACK BT_HCI_EVENT_HEADER;
/* MBOX host interrupt signal assignments */
#define MBOX_SIG_HCI_BRIDGE_MAX 8
#define MBOX_SIG_HCI_BRIDGE_BT_ON 0
#define MBOX_SIG_HCI_BRIDGE_BT_OFF 1
#define MBOX_SIG_HCI_BRIDGE_BAUD_SET 2
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_ON 3
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __GMBOXIF_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#define AR6001_GPIO_PIN_COUNT 18
#define AR6002_GPIO_PIN_COUNT 18
#define AR6003_GPIO_PIN_COUNT 28
/*
* Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
* NB: These match hardware order, so that addresses can
* easily be computed.
*/
#define GPIO_ID_OUT 0x00000000
#define GPIO_ID_OUT_W1TS 0x00000001
#define GPIO_ID_OUT_W1TC 0x00000002
#define GPIO_ID_ENABLE 0x00000003
#define GPIO_ID_ENABLE_W1TS 0x00000004
#define GPIO_ID_ENABLE_W1TC 0x00000005
#define GPIO_ID_IN 0x00000006
#define GPIO_ID_STATUS 0x00000007
#define GPIO_ID_STATUS_W1TS 0x00000008
#define GPIO_ID_STATUS_W1TC 0x00000009
#define GPIO_ID_PIN0 0x0000000a
#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
#define GPIO_ID_NONE 0xffffffff

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//------------------------------------------------------------------------------
// <copyright file="htc.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __HTC_H__
#define __HTC_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
(((A_UINT16)(((A_UINT8 *)(p))[(highbyte)])) << 8 | (A_UINT16)(((A_UINT8 *)(p))[(lowbyte)]))
/* alignment independent macros (little-endian) to fetch UINT16s or UINT8s from a
* structure using only the type and field name.
* Use these macros if there is the potential for unaligned buffer accesses. */
#define A_GET_UINT16_FIELD(p,type,field) \
ASSEMBLE_UNALIGNED_UINT16(p,\
A_OFFSETOF(type,field) + 1, \
A_OFFSETOF(type,field))
#define A_SET_UINT16_FIELD(p,type,field,value) \
{ \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (A_UINT8)(value); \
((A_UINT8 *)(p))[A_OFFSETOF(type,field) + 1] = (A_UINT8)((value) >> 8); \
}
#define A_GET_UINT8_FIELD(p,type,field) \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)]
#define A_SET_UINT8_FIELD(p,type,field,value) \
((A_UINT8 *)(p))[A_OFFSETOF(type,field)] = (value)
/****** DANGER DANGER ***************
*
* The frame header length and message formats defined herein were
* selected to accommodate optimal alignment for target processing. This reduces code
* size and improves performance.
*
* Any changes to the header length may alter the alignment and cause exceptions
* on the target. When adding to the message structures insure that fields are
* properly aligned.
*
*/
/* HTC frame header */
typedef PREPACK struct _HTC_FRAME_HDR{
/* do not remove or re-arrange these fields, these are minimally required
* to take advantage of 4-byte lookaheads in some hardware implementations */
A_UINT8 EndpointID;
A_UINT8 Flags;
A_UINT16 PayloadLen; /* length of data (including trailer) that follows the header */
/***** end of 4-byte lookahead ****/
A_UINT8 ControlBytes[2];
/* message payload starts after the header */
} POSTPACK HTC_FRAME_HDR;
/* frame header flags */
/* send direction */
#define HTC_FLAGS_NEED_CREDIT_UPDATE (1 << 0)
#define HTC_FLAGS_SEND_BUNDLE (1 << 1) /* start or part of bundle */
/* receive direction */
#define HTC_FLAGS_RECV_UNUSED_0 (1 << 0) /* bit 0 unused */
#define HTC_FLAGS_RECV_TRAILER (1 << 1) /* bit 1 trailer data present */
#define HTC_FLAGS_RECV_UNUSED_2 (1 << 0) /* bit 2 unused */
#define HTC_FLAGS_RECV_UNUSED_3 (1 << 0) /* bit 3 unused */
#define HTC_FLAGS_RECV_BUNDLE_CNT_MASK (0xF0) /* bits 7..4 */
#define HTC_FLAGS_RECV_BUNDLE_CNT_SHIFT 4
#define HTC_HDR_LENGTH (sizeof(HTC_FRAME_HDR))
#define HTC_MAX_TRAILER_LENGTH 255
#define HTC_MAX_PAYLOAD_LENGTH (4096 - sizeof(HTC_FRAME_HDR))
/* HTC control message IDs */
#define HTC_MSG_READY_ID 1
#define HTC_MSG_CONNECT_SERVICE_ID 2
#define HTC_MSG_CONNECT_SERVICE_RESPONSE_ID 3
#define HTC_MSG_SETUP_COMPLETE_ID 4
#define HTC_MSG_SETUP_COMPLETE_EX_ID 5
#define HTC_MAX_CONTROL_MESSAGE_LENGTH 256
/* base message ID header */
typedef PREPACK struct {
A_UINT16 MessageID;
} POSTPACK HTC_UNKNOWN_MSG;
/* HTC ready message
* direction : target-to-host */
typedef PREPACK struct {
A_UINT16 MessageID; /* ID */
A_UINT16 CreditCount; /* number of credits the target can offer */
A_UINT16 CreditSize; /* size of each credit */
A_UINT8 MaxEndpoints; /* maximum number of endpoints the target has resources for */
A_UINT8 _Pad1;
} POSTPACK HTC_READY_MSG;
/* extended HTC ready message */
typedef PREPACK struct {
HTC_READY_MSG Version2_0_Info; /* legacy version 2.0 information at the front... */
/* extended information */
A_UINT8 HTCVersion;
A_UINT8 MaxMsgsPerHTCBundle;
} POSTPACK HTC_READY_EX_MSG;
#define HTC_VERSION_2P0 0x00
#define HTC_VERSION_2P1 0x01 /* HTC 2.1 */
#define HTC_SERVICE_META_DATA_MAX_LENGTH 128
/* connect service
* direction : host-to-target */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT16 ServiceID; /* service ID of the service to connect to */
A_UINT16 ConnectionFlags; /* connection flags */
#define HTC_CONNECT_FLAGS_REDUCE_CREDIT_DRIBBLE (1 << 2) /* reduce credit dribbling when
the host needs credits */
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_MASK (0x3)
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_FOURTH 0x0
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_ONE_HALF 0x1
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_THREE_FOURTHS 0x2
#define HTC_CONNECT_FLAGS_THRESHOLD_LEVEL_UNITY 0x3
A_UINT8 ServiceMetaLength; /* length of meta data that follows */
A_UINT8 _Pad1;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_MSG;
/* connect response
* direction : target-to-host */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT16 ServiceID; /* service ID that the connection request was made */
A_UINT8 Status; /* service connection status */
A_UINT8 EndpointID; /* assigned endpoint ID */
A_UINT16 MaxMsgSize; /* maximum expected message size on this endpoint */
A_UINT8 ServiceMetaLength; /* length of meta data that follows */
A_UINT8 _Pad1;
/* service-specific meta data starts after the header */
} POSTPACK HTC_CONNECT_SERVICE_RESPONSE_MSG;
typedef PREPACK struct {
A_UINT16 MessageID;
/* currently, no other fields */
} POSTPACK HTC_SETUP_COMPLETE_MSG;
/* extended setup completion message */
typedef PREPACK struct {
A_UINT16 MessageID;
A_UINT32 SetupFlags;
A_UINT8 MaxMsgsPerBundledRecv;
A_UINT8 Rsvd[3];
} POSTPACK HTC_SETUP_COMPLETE_EX_MSG;
#define HTC_SETUP_COMPLETE_FLAGS_ENABLE_BUNDLE_RECV (1 << 0)
/* connect response status codes */
#define HTC_SERVICE_SUCCESS 0 /* success */
#define HTC_SERVICE_NOT_FOUND 1 /* service could not be found */
#define HTC_SERVICE_FAILED 2 /* specific service failed the connect */
#define HTC_SERVICE_NO_RESOURCES 3 /* no resources (i.e. no more endpoints) */
#define HTC_SERVICE_NO_MORE_EP 4 /* specific service is not allowing any more
endpoints */
/* report record IDs */
#define HTC_RECORD_NULL 0
#define HTC_RECORD_CREDITS 1
#define HTC_RECORD_LOOKAHEAD 2
#define HTC_RECORD_LOOKAHEAD_BUNDLE 3
typedef PREPACK struct {
A_UINT8 RecordID; /* Record ID */
A_UINT8 Length; /* Length of record */
} POSTPACK HTC_RECORD_HDR;
typedef PREPACK struct {
A_UINT8 EndpointID; /* Endpoint that owns these credits */
A_UINT8 Credits; /* credits to report since last report */
} POSTPACK HTC_CREDIT_REPORT;
typedef PREPACK struct {
A_UINT8 PreValid; /* pre valid guard */
A_UINT8 LookAhead[4]; /* 4 byte lookahead */
A_UINT8 PostValid; /* post valid guard */
/* NOTE: the LookAhead array is guarded by a PreValid and Post Valid guard bytes.
* The PreValid bytes must equal the inverse of the PostValid byte */
} POSTPACK HTC_LOOKAHEAD_REPORT;
typedef PREPACK struct {
A_UINT8 LookAhead[4]; /* 4 byte lookahead */
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __HTC_H__ */

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//------------------------------------------------------------------------------
// <copyright file="htc_services.h" company="Atheros">
// Copyright (c) 2007 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __HTC_SERVICES_H__
#define __HTC_SERVICES_H__
/* Current service IDs */
typedef enum {
RSVD_SERVICE_GROUP = 0,
WMI_SERVICE_GROUP = 1,
HTC_TEST_GROUP = 254,
HTC_SERVICE_GROUP_LAST = 255
}HTC_SERVICE_GROUP_IDS;
#define MAKE_SERVICE_ID(group,index) \
(int)(((int)group << 8) | (int)(index))
/* NOTE: service ID of 0x0000 is reserved and should never be used */
#define HTC_CTRL_RSVD_SVC MAKE_SERVICE_ID(RSVD_SERVICE_GROUP,1)
#define WMI_CONTROL_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,0)
#define WMI_DATA_BE_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,1)
#define WMI_DATA_BK_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,2)
#define WMI_DATA_VI_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,3)
#define WMI_DATA_VO_SVC MAKE_SERVICE_ID(WMI_SERVICE_GROUP,4)
#define WMI_MAX_SERVICES 5
/* raw stream service (i.e. flash, tcmd, calibration apps) */
#define HTC_RAW_STREAMS_SVC MAKE_SERVICE_ID(HTC_TEST_GROUP,0)
#endif /*HTC_SERVICES_H_*/

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//------------------------------------------------------------------------------
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#ifndef _INI_DSET_H_
#define _INI_DSET_H_
/*
* Each of these represents a WHAL INI table, which consists
* of an "address column" followed by 1 or more "value columns".
*
* Software uses the base WHAL_INI_DATA_ID+column to access a
* DataSet that holds a particular column of data.
*/
typedef enum {
#if defined(AR6002_REV4) || defined(AR6003)
/* Add these definitions for compatability */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */
WHAL_INI_DATA_ID_COMMON =6, /* 7 */
WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */
#ifdef FPGA
WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */
WHAL_INI_DATA_ID_ADDAC =25, /* 26 */
#else
WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
#endif /* FPGA */
#else
WHAL_INI_DATA_ID_NULL =0,
WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
WHAL_INI_DATA_ID_COMMON =4, /* 5 */
WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */
#endif
WHAL_INI_DATA_ID_MAX =31
} WHAL_INI_DATA_ID;
typedef PREPACK struct {
A_UINT16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
A_UINT16 offset;
A_UINT32 newValue;
} POSTPACK INI_DSET_REG_OVERRIDE;
#endif

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//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __PKT_LOG_H__
#define __PKT_LOG_H__
#ifdef __cplusplus
extern "C" {
#endif
/* Pkt log info */
typedef PREPACK struct pkt_log_t {
struct info_t {
A_UINT16 st;
A_UINT16 end;
A_UINT16 cur;
}info[4096];
A_UINT16 last_idx;
}POSTPACK PACKET_LOG;
#ifdef __cplusplus
}
#endif
#endif /* __PKT_LOG_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DB_H__
#define __REG_DB_H__
#include "./regulatory/reg_dbschema.h"
#include "./regulatory/reg_dbvalues.h"
#endif /* __REG_DB_H__ */

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//------------------------------------------------------------------------------
// <copyright file="regdump.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REGDUMP_H__
#define __REGDUMP_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6001)
#include "AR6001/AR6001_regdump.h"
#endif
#if defined(AR6002)
#include "AR6002/AR6002_regdump.h"
#endif
#if !defined(__ASSEMBLER__)
/*
* Target CPU state at the time of failure is reflected
* in a register dump, which the Host can fetch through
* the diagnostic window.
*/
PREPACK struct register_dump_s {
A_UINT32 target_id; /* Target ID */
A_UINT32 assline; /* Line number (if assertion failure) */
A_UINT32 pc; /* Program Counter at time of exception */
A_UINT32 badvaddr; /* Virtual address causing exception */
CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
/* Could copy top of stack here, too.... */
} POSTPACK;
#endif /* __ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __REGDUMP_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBSCHEMA_H__
#define __REG_DBSCHEMA_H__
/*
* This file describes the regulatory DB schema, which is common between the
* 'generator' and 'parser'. The 'generator' runs on a host(typically a x86
* Linux) and spits outs two binary files, which follow the DB file
* format(described below). The resultant output "regulatoryData_AG.bin"
* is binary file which has information regarding A and G regulatory
* information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory
* information. This binary file is parsed in the target for extracting
* regulatory information.
*
* The DB values used to populate the regulatory DB are defined in
* reg_dbvalues.h
*
*/
/* Binary data file - Representation of Regulatory DB*/
#define REG_DATA_FILE_AG "./regulatoryData_AG.bin"
#define REG_DATA_FILE_G "./regulatoryData_G.bin"
/* Table tags used to encode different tables in the database */
enum data_tags_t{
REG_DMN_PAIR_MAPPING_TAG = 0,
REG_COUNTRY_CODE_TO_ENUM_RD_TAG,
REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG,
REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG,
REG_DOMAIN_TAG,
MAX_DB_TABLE_TAGS
};
/*
****************************************************************************
* Regulatory DB file format :
* 4-bytes : "RGDB" (Magic Key)
* 4-bytes : version (Default is 5379(my extn))
* 4-bytes : length of file
* dbType(4)
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* TAG(4)
* Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
* ...
* ...
****************************************************************************
*
*/
/*
* Length of the file would be filled in when the file is created and
* it would include the header size.
*/
#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */
#define REG_DB_VER 7802 /* Between 0-9999 */
/* REG_DB_VER history in reverse chronological order:
* 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09
* 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes)
* 1178: '11N' = 11 + ASCII code of N(78)
* 5379: initial version, no 11N support
*/
#define MAGIC_KEY_OFFSET 0
#define VERSION_OFFSET 4
#define FILE_SZ_OFFSET 8
#define DB_TYPE_OFFSET 12
#define MAGIC_KEY_SZ 4
#define VERSION_SZ 4
#define FILE_SZ_SZ 4
#define DB_TYPE_SZ 4
#define DB_TAG_SZ 4
#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET)
#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET)
#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET))
#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET)
#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_)
#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) )
/* A Table can be search based on key as a parameter or accessed directly
* by giving its index in to the table.
*/
enum searchType {
KEY_BASED_TABLE_SEARCH = 1,
INDEX_BASED_TABLE_ACCESS
};
/* Data is organised as different tables. There is a Master table, which
* holds information regarding all the tables. It does not have any
* knowledge about the attributes of the table it is holding
* but has external view of the same(for ex, how many entries, record size,
* how to search the table, total table size and reference to the data
* instance of table).
*/
typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */
A_UCHAR numOfEntries;
A_CHAR entrySize; /* Entry size per table row */
A_CHAR searchType; /* Index based access or key based */
A_CHAR reserved[3]; /* for alignment */
A_UINT16 tableSize; /* Size of this table */
A_CHAR *dataPtr; /* Ptr to the actual Table */
} POSTPACK dbMasterTable; /* Master table - table of tables */
/* used to get the number of rows in a table */
#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0]))
/*
* Used to set the RegDomain bitmask which chooses which frequency
* band specs are used.
*/
#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */
#define BMZERO {0,0} /* BMLEN zeros */
#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
{((((_fa >= 0) && (_fa < 32)) ? (((A_UINT32) 1) << _fa) : 0) | \
(((_fb >= 0) && (_fb < 32)) ? (((A_UINT32) 1) << _fb) : 0) | \
(((_fc >= 0) && (_fc < 32)) ? (((A_UINT32) 1) << _fc) : 0) | \
(((_fd >= 0) && (_fd < 32)) ? (((A_UINT32) 1) << _fd) : 0) | \
(((_fe >= 0) && (_fe < 32)) ? (((A_UINT32) 1) << _fe) : 0) | \
(((_ff >= 0) && (_ff < 32)) ? (((A_UINT32) 1) << _ff) : 0) | \
(((_fg >= 0) && (_fg < 32)) ? (((A_UINT32) 1) << _fg) : 0) | \
(((_fh >= 0) && (_fh < 32)) ? (((A_UINT32) 1) << _fh) : 0)), \
((((_fa > 31) && (_fa < 64)) ? (((A_UINT32) 1) << (_fa - 32)) : 0) | \
(((_fb > 31) && (_fb < 64)) ? (((A_UINT32) 1) << (_fb - 32)) : 0) | \
(((_fc > 31) && (_fc < 64)) ? (((A_UINT32) 1) << (_fc - 32)) : 0) | \
(((_fd > 31) && (_fd < 64)) ? (((A_UINT32) 1) << (_fd - 32)) : 0) | \
(((_fe > 31) && (_fe < 64)) ? (((A_UINT32) 1) << (_fe - 32)) : 0) | \
(((_ff > 31) && (_ff < 64)) ? (((A_UINT32) 1) << (_ff - 32)) : 0) | \
(((_fg > 31) && (_fg < 64)) ? (((A_UINT32) 1) << (_fg - 32)) : 0) | \
(((_fh > 31) && (_fh < 64)) ? (((A_UINT32) 1) << (_fh - 32)) : 0))}
/*
* THE following table is the mapping of regdomain pairs specified by
* a regdomain value to the individual unitary reg domains
*/
typedef PREPACK struct reg_dmn_pair_mapping {
A_UINT16 regDmnEnum; /* 16 bit reg domain pair */
A_UINT16 regDmn5GHz; /* 5GHz reg domain */
A_UINT16 regDmn2GHz; /* 2GHz reg domain */
A_UINT8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */
A_UINT8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */
A_UINT32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
flags. This value is used as a mask on the unitary flags*/
} POSTPACK REG_DMN_PAIR_MAPPING;
#define OFDM_YES (1 << 0)
#define OFDM_NO (0 << 0)
#define MCS_HT20_YES (1 << 1)
#define MCS_HT20_NO (0 << 1)
#define MCS_HT40_A_YES (1 << 2)
#define MCS_HT40_A_NO (0 << 2)
#define MCS_HT40_G_YES (1 << 3)
#define MCS_HT40_G_NO (0 << 3)
typedef PREPACK struct {
A_UINT16 countryCode;
A_UINT16 regDmnEnum;
A_CHAR isoName[3];
A_CHAR allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */
} POSTPACK COUNTRY_CODE_TO_ENUM_RD;
/* lower 16 bits of ht40ChanMask */
#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */
#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */
#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */
#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */
#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */
#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */
#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */
#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */
/* upper 16 bits of ht40ChanMask */
#define FREQ_HALF_RATE 0x10000
#define FREQ_QUARTER_RATE 0x20000
typedef PREPACK struct RegDmnFreqBand {
A_UINT16 lowChannel; /* Low channel center in MHz */
A_UINT16 highChannel; /* High Channel center in MHz */
A_UINT8 power; /* Max power (dBm) for channel range */
A_UINT8 channelSep; /* Channel separation within the band */
A_UINT8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */
A_UINT8 mode; /* Mode of operation */
A_UINT32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
A_UINT32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
upper 16 bits: what rate (half/quarter) the channel is */
} POSTPACK REG_DMN_FREQ_BAND;
typedef PREPACK struct regDomain {
A_UINT16 regDmnEnum; /* value from EnumRd table */
A_UINT8 rdCTL;
A_UINT8 maxAntGain;
A_UINT8 dfsMask; /* DFS bitmask for 5Ghz tables */
A_UINT8 flags; /* Requirement flags (AdHoc disallow etc) */
A_UINT16 reserved; /* for alignment */
A_UINT32 pscan; /* Bitmask for passive scan */
A_UINT32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
A_UINT32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
} POSTPACK REG_DOMAIN;
#endif /* __REG_DBSCHEMA_H__ */

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//------------------------------------------------------------------------------
// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __REG_DBVALUE_H__
#define __REG_DBVALUE_H__
/*
* Numbering from ISO 3166
*/
enum CountryCode {
CTRY_ALBANIA = 8, /* Albania */
CTRY_ALGERIA = 12, /* Algeria */
CTRY_ARGENTINA = 32, /* Argentina */
CTRY_ARMENIA = 51, /* Armenia */
CTRY_ARUBA = 533, /* Aruba */
CTRY_AUSTRALIA = 36, /* Australia (for STA) */
CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */
CTRY_AUSTRIA = 40, /* Austria */
CTRY_AZERBAIJAN = 31, /* Azerbaijan */
CTRY_BAHRAIN = 48, /* Bahrain */
CTRY_BANGLADESH = 50, /* Bangladesh */
CTRY_BARBADOS = 52, /* Barbados */
CTRY_BELARUS = 112, /* Belarus */
CTRY_BELGIUM = 56, /* Belgium */
CTRY_BELIZE = 84, /* Belize */
CTRY_BOLIVIA = 68, /* Bolivia */
CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */
CTRY_BRAZIL = 76, /* Brazil */
CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
CTRY_BULGARIA = 100, /* Bulgaria */
CTRY_CAMBODIA = 116, /* Cambodia */
CTRY_CANADA = 124, /* Canada (for STA) */
CTRY_CANADA_AP = 5001, /* Canada (for AP) */
CTRY_CHILE = 152, /* Chile */
CTRY_CHINA = 156, /* People's Republic of China */
CTRY_COLOMBIA = 170, /* Colombia */
CTRY_COSTA_RICA = 188, /* Costa Rica */
CTRY_CROATIA = 191, /* Croatia */
CTRY_CYPRUS = 196,
CTRY_CZECH = 203, /* Czech Republic */
CTRY_DENMARK = 208, /* Denmark */
CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
CTRY_ECUADOR = 218, /* Ecuador */
CTRY_EGYPT = 818, /* Egypt */
CTRY_EL_SALVADOR = 222, /* El Salvador */
CTRY_ESTONIA = 233, /* Estonia */
CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
CTRY_FINLAND = 246, /* Finland */
CTRY_FRANCE = 250, /* France */
CTRY_FRANCE2 = 255, /* France2 */
CTRY_GEORGIA = 268, /* Georgia */
CTRY_GERMANY = 276, /* Germany */
CTRY_GREECE = 300, /* Greece */
CTRY_GREENLAND = 304, /* Greenland */
CTRY_GRENADA = 308, /* Grenada */
CTRY_GUAM = 316, /* Guam */
CTRY_GUATEMALA = 320, /* Guatemala */
CTRY_HAITI = 332, /* Haiti */
CTRY_HONDURAS = 340, /* Honduras */
CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
CTRY_HUNGARY = 348, /* Hungary */
CTRY_ICELAND = 352, /* Iceland */
CTRY_INDIA = 356, /* India */
CTRY_INDONESIA = 360, /* Indonesia */
CTRY_IRAN = 364, /* Iran */
CTRY_IRAQ = 368, /* Iraq */
CTRY_IRELAND = 372, /* Ireland */
CTRY_ISRAEL = 376, /* Israel */
CTRY_ITALY = 380, /* Italy */
CTRY_JAMAICA = 388, /* Jamaica */
CTRY_JAPAN = 392, /* Japan */
CTRY_JAPAN1 = 393, /* Japan (JP1) */
CTRY_JAPAN2 = 394, /* Japan (JP0) */
CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
CTRY_JAPAN4 = 396, /* Japan (JE1) */
CTRY_JAPAN5 = 397, /* Japan (JE2) */
CTRY_JAPAN6 = 399, /* Japan (JP6) */
CTRY_JORDAN = 400, /* Jordan */
CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
CTRY_KENYA = 404, /* Kenya */
CTRY_KOREA_NORTH = 408, /* North Korea */
CTRY_KOREA_ROC = 410, /* South Korea (for STA) */
CTRY_KOREA_ROC2 = 411, /* South Korea */
CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */
CTRY_KUWAIT = 414, /* Kuwait */
CTRY_LATVIA = 428, /* Latvia */
CTRY_LEBANON = 422, /* Lebanon */
CTRY_LIBYA = 434, /* Libya */
CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
CTRY_LITHUANIA = 440, /* Lithuania */
CTRY_LUXEMBOURG = 442, /* Luxembourg */
CTRY_MACAU = 446, /* Macau */
CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */
CTRY_MALAYSIA = 458, /* Malaysia */
CTRY_MALTA = 470, /* Malta */
CTRY_MEXICO = 484, /* Mexico */
CTRY_MONACO = 492, /* Principality of Monaco */
CTRY_MOROCCO = 504, /* Morocco */
CTRY_NEPAL = 524, /* Nepal */
CTRY_NETHERLANDS = 528, /* Netherlands */
CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */
CTRY_NEW_ZEALAND = 554, /* New Zealand */
CTRY_NICARAGUA = 558, /* Nicaragua */
CTRY_NORWAY = 578, /* Norway */
CTRY_OMAN = 512, /* Oman */
CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
CTRY_PANAMA = 591, /* Panama */
CTRY_PARAGUAY = 600, /* Paraguay */
CTRY_PERU = 604, /* Peru */
CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
CTRY_POLAND = 616, /* Poland */
CTRY_PORTUGAL = 620, /* Portugal */
CTRY_PUERTO_RICO = 630, /* Puerto Rico */
CTRY_QATAR = 634, /* Qatar */
CTRY_ROMANIA = 642, /* Romania */
CTRY_RUSSIA = 643, /* Russia */
CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
CTRY_MONTENEGRO = 891, /* Montenegro */
CTRY_SINGAPORE = 702, /* Singapore */
CTRY_SLOVAKIA = 703, /* Slovak Republic */
CTRY_SLOVENIA = 705, /* Slovenia */
CTRY_SOUTH_AFRICA = 710, /* South Africa */
CTRY_SPAIN = 724, /* Spain */
CTRY_SRILANKA = 144, /* Sri Lanka */
CTRY_SWEDEN = 752, /* Sweden */
CTRY_SWITZERLAND = 756, /* Switzerland */
CTRY_SYRIA = 760, /* Syria */
CTRY_TAIWAN = 158, /* Taiwan */
CTRY_THAILAND = 764, /* Thailand */
CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
CTRY_TUNISIA = 788, /* Tunisia */
CTRY_TURKEY = 792, /* Turkey */
CTRY_UAE = 784, /* U.A.E. */
CTRY_UKRAINE = 804, /* Ukraine */
CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
CTRY_UNITED_STATES = 840, /* United States (for STA) */
CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */
CTRY_UNITED_STATES_PS = 842, /* United States - public safety */
CTRY_URUGUAY = 858, /* Uruguay */
CTRY_UZBEKISTAN = 860, /* Uzbekistan */
CTRY_VENEZUELA = 862, /* Venezuela */
CTRY_VIET_NAM = 704, /* Viet Nam */
CTRY_YEMEN = 887, /* Yemen */
CTRY_ZIMBABWE = 716 /* Zimbabwe */
};
#define CTRY_DEBUG 0
#define CTRY_DEFAULT 0x1ff
/*
* The following regulatory domain definitions are
* found in the EEPROM. Each regulatory domain
* can operate in either a 5GHz or 2.4GHz wireless mode or
* both 5GHz and 2.4GHz wireless modes.
* In general, the value holds no special
* meaning and is used to decode into either specific
* 2.4GHz or 5GHz wireless mode for that particular
* regulatory domain.
*
* Enumerated Regulatory Domain Information 8 bit values indicate that
* the regdomain is really a pair of unitary regdomains. 12 bit values
* are the real unitary regdomains and are the only ones which have the
* frequency bitmasks and flags set.
*/
enum EnumRd {
NO_ENUMRD = 0x00,
NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */
NULL1_ETSIB = 0x07, /* Israel */
NULL1_ETSIC = 0x08,
FCC1_FCCA = 0x10, /* USA */
FCC1_WORLD = 0x11, /* Hong Kong */
FCC2_FCCA = 0x20, /* Canada */
FCC2_WORLD = 0x21, /* Australia & HK */
FCC2_ETSIC = 0x22,
FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */
FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */
FCC5_FCCA = 0x13, /* US with no DFS */
FCC5_WORLD = 0x16, /* US with no DFS */
FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */
FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */
ETSI1_WORLD = 0x37,
ETSI2_WORLD = 0x35, /* Hungary & others */
ETSI3_WORLD = 0x36, /* France & others */
ETSI4_WORLD = 0x30,
ETSI4_ETSIC = 0x38,
ETSI5_WORLD = 0x39,
ETSI6_WORLD = 0x34, /* Bulgaria */
ETSI_RESERVED = 0x33, /* Reserved (Do not used) */
FRANCE_RES = 0x31, /* Legacy France for OEM */
APL6_WORLD = 0x5B, /* Singapore */
APL4_WORLD = 0x42, /* Singapore */
APL3_FCCA = 0x50,
APL_RESERVED = 0x44, /* Reserved (Do not used) */
APL2_WORLD = 0x45, /* Korea */
APL2_APLC = 0x46,
APL3_WORLD = 0x47,
APL2_APLD = 0x49, /* Korea with 2.3G channels */
APL2_FCCA = 0x4D, /* Specific Mobile Customer */
APL1_WORLD = 0x52, /* Latin America */
APL1_FCCA = 0x53,
APL1_ETSIC = 0x55,
APL2_ETSIC = 0x56, /* Venezuela */
APL5_WORLD = 0x58, /* Chile */
APL7_FCCA = 0x5C,
APL8_WORLD = 0x5D,
APL9_WORLD = 0x5E,
APL10_WORLD = 0x5F, /* Korea 5GHz for STA */
MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */
MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */
MKK5_MKKC = 0x88,
MKK11_MKKA = 0xD4,
MKK11_FCCA = 0xD5,
MKK11_MKKC = 0xD7,
/*
* World mode SKUs
*/
WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */
WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */
WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */
WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */
WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */
WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */
WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */
WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */
EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */
WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */
/*
* Regulator domains ending in a number (e.g. APL1,
* MK1, ETSI4, etc) apply to 5GHz channel and power
* information. Regulator domains ending in a letter
* (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
* power information.
*/
APL1 = 0x0150, /* LAT & Asia */
APL2 = 0x0250, /* LAT & Asia */
APL3 = 0x0350, /* Taiwan */
APL4 = 0x0450, /* Jordan */
APL5 = 0x0550, /* Chile */
APL6 = 0x0650, /* Singapore */
APL7 = 0x0750, /* Taiwan */
APL8 = 0x0850, /* Malaysia */
APL9 = 0x0950, /* Korea */
APL10 = 0x1050, /* Korea 5GHz */
ETSI1 = 0x0130, /* Europe & others */
ETSI2 = 0x0230, /* Europe & others */
ETSI3 = 0x0330, /* Europe & others */
ETSI4 = 0x0430, /* Europe & others */
ETSI5 = 0x0530, /* Europe & others */
ETSI6 = 0x0630, /* Europe & others */
ETSIB = 0x0B30, /* Israel */
ETSIC = 0x0C30, /* Latin America */
FCC1 = 0x0110, /* US & others */
FCC2 = 0x0120, /* Canada, Australia & New Zealand */
FCC3 = 0x0160, /* US w/new middle band & DFS */
FCC4 = 0x0165,
FCC5 = 0x0180,
FCC6 = 0x0610,
FCCA = 0x0A10,
APLD = 0x0D50, /* South Korea */
MKK1 = 0x0140, /* Japan */
MKK2 = 0x0240, /* Japan Extended */
MKK3 = 0x0340, /* Japan new 5GHz */
MKK4 = 0x0440, /* Japan new 5GHz */
MKK5 = 0x0540, /* Japan new 5GHz */
MKK6 = 0x0640, /* Japan new 5GHz */
MKK7 = 0x0740, /* Japan new 5GHz */
MKK8 = 0x0840, /* Japan new 5GHz */
MKK9 = 0x0940, /* Japan new 5GHz */
MKK10 = 0x1040, /* Japan new 5GHz */
MKK11 = 0x1140, /* Japan new 5GHz */
MKK12 = 0x1240, /* Japan new 5GHz */
MKKA = 0x0A40, /* Japan */
MKKC = 0x0A50,
NULL1 = 0x0198,
WORLD = 0x0199,
DEBUG_REG_DMN = 0x01ff,
UNINIT_REG_DMN = 0x0fff,
};
enum { /* conformance test limits */
FCC = 0x10,
MKK = 0x40,
ETSI = 0x30,
NO_CTL = 0xff,
CTL_11B = 1,
CTL_11G = 2
};
/*
* The following are flags for different requirements per reg domain.
* These requirements are either inhereted from the reg domain pair or
* from the unitary reg domain if the reg domain pair flags value is
* 0
*/
enum {
NO_REQ = 0x00,
DISALLOW_ADHOC_11A = 0x01,
ADHOC_PER_11D = 0x02,
ADHOC_NO_11A = 0x04,
DISALLOW_ADHOC_11G = 0x08
};
/*
* The following describe the bit masks for different passive scan
* capability/requirements per regdomain.
*/
#define NO_PSCAN 0x00000000
#define PSCAN_FCC 0x00000001
#define PSCAN_ETSI 0x00000002
#define PSCAN_MKK 0x00000004
#define PSCAN_ETSIB 0x00000008
#define PSCAN_ETSIC 0x00000010
#define PSCAN_WWR 0x00000020
#define PSCAN_DEFER 0xFFFFFFFF
/* Bit masks for DFS per regdomain */
enum {
NO_DFS = 0x00,
DFS_FCC3 = 0x01,
DFS_ETSI = 0x02,
DFS_MKK = 0x04
};
#define DEF_REGDMN FCC1_FCCA
/*
* The following table is the master list for all different freqeuncy
* bands with the complete matrix of all possible flags and settings
* for each band if it is used in ANY reg domain.
*
* The table of frequency bands is indexed by a bitmask. The ordering
* must be consistent with the enum below. When adding a new
* frequency band, be sure to match the location in the enum with the
* comments
*/
/*
* These frequency values are as per channel tags and regulatory domain
* info. Please update them as database is updated.
*/
#define A_FREQ_MIN 4920
#define A_FREQ_MAX 5825
#define A_CHAN0_FREQ 5000
#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5)
#define BG_FREQ_MIN 2412
#define BG_FREQ_MAX 2484
#define BG_CHAN0_FREQ 2407
#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5)
#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */
#define A_20MHZ_BAND_FREQ_MAX 5000
/*
* 5GHz 11A channel tags
*/
enum {
F1_4920_4980,
F1_5040_5080,
F1_5120_5240,
F1_5180_5240,
F2_5180_5240,
F3_5180_5240,
F4_5180_5240,
F5_5180_5240,
F6_5180_5240,
F7_5180_5240,
F1_5260_5280,
F1_5260_5320,
F2_5260_5320,
F3_5260_5320,
F4_5260_5320,
F5_5260_5320,
F6_5260_5320,
F1_5260_5700,
F1_5280_5320,
F1_5500_5620,
F1_5500_5700,
F2_5500_5700,
F3_5500_5700,
F4_5500_5700,
F5_5500_5700,
F6_5500_5700,
F7_5500_5700,
F1_5745_5805,
F2_5745_5805,
F1_5745_5825,
F2_5745_5825,
F3_5745_5825,
F4_5745_5825,
F5_5745_5825,
F6_5745_5825,
W1_4920_4980,
W1_5040_5080,
W1_5170_5230,
W1_5180_5240,
W1_5260_5320,
W1_5745_5825,
W1_5500_5700,
};
/* 2.4 GHz table - for 11b and 11g info */
enum {
BG1_2312_2372,
BG2_2312_2372,
BG1_2412_2472,
BG2_2412_2472,
BG3_2412_2472,
BG4_2412_2472,
BG1_2412_2462,
BG2_2412_2462,
BG1_2432_2442,
BG1_2457_2472,
BG1_2467_2472,
BG1_2484_2484, /* No G */
BG2_2484_2484, /* No G */
BG1_2512_2732,
WBG1_2312_2372,
WBG1_2412_2412,
WBG1_2417_2432,
WBG1_2437_2442,
WBG1_2447_2457,
WBG1_2462_2462,
WBG1_2467_2467,
WBG2_2467_2467,
WBG1_2472_2472,
WBG2_2472_2472,
WBG1_2484_2484, /* No G */
WBG2_2484_2484, /* No G */
};
#endif /* __REG_DBVALUE_H__ */

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//------------------------------------------------------------------------------
// <copyright file="roaming.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef _ROAMING_H_
#define _ROAMING_H_
/*
* The signal quality could be in terms of either snr or rssi. We should
* have an enum for both of them. For the time being, we are going to move
* it to wmi.h that is shared by both host and the target, since we are
* repartitioning the code to the host
*/
#define SIGNAL_QUALITY_NOISE_FLOOR -96
#define SIGNAL_QUALITY_METRICS_NUM_MAX 2
typedef enum {
SIGNAL_QUALITY_METRICS_SNR = 0,
SIGNAL_QUALITY_METRICS_RSSI,
SIGNAL_QUALITY_METRICS_ALL,
} SIGNAL_QUALITY_METRICS_TYPE;
#endif /* _ROAMING_H_ */

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//------------------------------------------------------------------------------
// Copyright (c) 2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//
// Author(s): ="Atheros"
//------------------------------------------------------------------------------
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
#ifndef ATH_TARGET
#include "athstartpack.h"
#endif
#if defined(AR6002)
#include "AR6002/addrs.h"
#endif
/*
* AR6K option bits, to enable/disable various features.
* By default, all option bits are 0.
* These bits can be set in LOCAL_SCRATCH register 0.
*/
#define AR6K_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
#define AR6K_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
#define AR6K_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
#define AR6K_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
#define AR6K_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
#define AR6K_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
#define AR6K_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
#define AR6K_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
/*
* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
* host_interest structure. It must match the address of the _host_interest
* symbol (see linker script).
*
* Host Interest is shared between Host and Target in order to coordinate
* between the two, and is intended to remain constant (with additions only
* at the end) across software releases.
*
* All addresses are available here so that it's possible to
* write a single binary that works with all Target Types.
* May be used in assembler code as well as C.
*/
#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
#define HOST_INTEREST_MAX_SIZE 0x100
#if !defined(__ASSEMBLER__)
struct register_dump_s;
struct dbglog_hdr_s;
/*
* These are items that the Host may need to access
* via BMI or via the Diagnostic Window. The position
* of items in this structure must remain constant
* across firmware revisions!
*
* Types for each item must be fixed size across
* target and host platforms.
*
* More items may be added at the end.
*/
PREPACK struct host_interest_s {
/*
* Pointer to application-defined area, if any.
* Set by Target application during startup.
*/
A_UINT32 hi_app_host_interest; /* 0x00 */
/* Pointer to register dump area, valid after Target crash. */
A_UINT32 hi_failure_state; /* 0x04 */
/* Pointer to debug logging header */
A_UINT32 hi_dbglog_hdr; /* 0x08 */
/* Indicates whether or not flash is present on Target.
* NB: flash_is_present indicator is here not just
* because it might be of interest to the Host; but
* also because it's set early on by Target's startup
* asm code and we need it to have a special RAM address
* so that it doesn't get reinitialized with the rest
* of data.
*/
A_UINT32 hi_flash_is_present; /* 0x0c */
/*
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
* Can be used by application rather than by OS.
*/
A_UINT32 hi_option_flag; /* 0x10 */
/*
* Boolean that determines whether or not to
* display messages on the serial port.
*/
A_UINT32 hi_serial_enable; /* 0x14 */
/* Start address of Flash DataSet index, if any */
A_UINT32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
A_UINT32 hi_app_start; /* 0x1c */
/* Clock and voltage tuning */
A_UINT32 hi_skip_clock_init; /* 0x20 */
A_UINT32 hi_core_clock_setting; /* 0x24 */
A_UINT32 hi_cpu_clock_setting; /* 0x28 */
A_UINT32 hi_system_sleep_setting; /* 0x2c */
A_UINT32 hi_xtal_control_setting; /* 0x30 */
A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
A_UINT32 hi_clock_info; /* 0x40 */
/*
* Flash configuration overrides, used only
* when firmware is not executing from flash.
* (When using flash, modify the global variables
* with equivalent names.)
*/
A_UINT32 hi_bank0_addr_value; /* 0x44 */
A_UINT32 hi_bank0_read_value; /* 0x48 */
A_UINT32 hi_bank0_write_value; /* 0x4c */
A_UINT32 hi_bank0_config_value; /* 0x50 */
/* Pointer to Board Data */
A_UINT32 hi_board_data; /* 0x54 */
A_UINT32 hi_board_data_initialized; /* 0x58 */
A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
A_UINT32 hi_desired_baud_rate; /* 0x60 */
A_UINT32 hi_dbglog_config; /* 0x64 */
A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
A_UINT32 hi_refclk_hz; /* 0x78 */
A_UINT32 hi_ext_clk_detected; /* 0x7c */
A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
A_UINT32 hi_hci_uart_baud; /* 0x88 */
A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
A_UINT32 hi_allocram_start; /* 0x98 */
A_UINT32 hi_allocram_sz; /* 0x9c */
A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
/* 0xa8 - [0]: 1 = enable, 0 = disable
* [1]: 0 = UART FC active low, 1 = UART FC active high
* 0xa9 - [7:0]: wakeup timeout in ms
* 0xaa, 0xab - [15:0]: idle timeout in ms
*/
/* Pointer to extended board Data */
A_UINT32 hi_board_ext_data; /* 0xac */
A_UINT32 hi_board_ext_data_initialized; /* 0xb0 */
} POSTPACK;
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */
#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */
#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
/* Fw Mode Mask */
#define HI_OPTION_FW_MODE_MASK 0x3
#define HI_OPTION_FW_MODE_SHIFT 0x3
/*
* Intended for use by Host software, this macro returns the Target RAM
* address of any item in the host_interest structure.
* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
*/
#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(A_UINT32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
/* override REV2 ROM's app start address */
#define AR6002_REV2_APP_START_OVERRIDE 0x911A00
#define AR6003_REV1_APP_START_OVERRIDE 0x944c00
#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800
#define AR6003_REV2_APP_START_OVERRIDE 0x945000
#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800
#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
#ifndef ATH_TARGET
#include "athendpack.h"
#endif
#endif /* __TARGADDRS_H__ */

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//------------------------------------------------------------------------------
// <copyright file="testcmd.h" company="Atheros">
// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef TESTCMD_H_
#define TESTCMD_H_
#ifdef __cplusplus
extern "C" {
#endif
#ifdef AR6002_REV2
#define TCMD_MAX_RATES 12
#else
#define TCMD_MAX_RATES 28
#endif
typedef enum {
ZEROES_PATTERN = 0,
ONES_PATTERN,
REPEATING_10,
PN7_PATTERN,
PN9_PATTERN,
PN15_PATTERN
}TX_DATA_PATTERN;
/* Continous tx
mode : TCMD_CONT_TX_OFF - Disabling continous tx
TCMD_CONT_TX_SINE - Enable continuous unmodulated tx
TCMD_CONT_TX_FRAME- Enable continuous modulated tx
freq : Channel freq in Mhz. (e.g 2412 for channel 1 in 11 g)
dataRate: 0 - 1 Mbps
1 - 2 Mbps
2 - 5.5 Mbps
3 - 11 Mbps
4 - 6 Mbps
5 - 9 Mbps
6 - 12 Mbps
7 - 18 Mbps
8 - 24 Mbps
9 - 36 Mbps
10 - 28 Mbps
11 - 54 Mbps
txPwr: Tx power in dBm[5 -11] for unmod Tx, [5-14] for mod Tx
antenna: 1 - one antenna
2 - two antenna
Note : Enable/disable continuous tx test cmd works only when target is awake.
*/
typedef enum {
TCMD_CONT_TX_OFF = 0,
TCMD_CONT_TX_SINE,
TCMD_CONT_TX_FRAME,
TCMD_CONT_TX_TX99,
TCMD_CONT_TX_TX100
} TCMD_CONT_TX_MODE;
typedef enum {
TCMD_WLAN_MODE_NOHT = 0,
TCMD_WLAN_MODE_HT20 = 1,
TCMD_WLAN_MODE_HT40PLUS = 2,
TCMD_WLAN_MODE_HT40MINUS = 3,
} TCMD_WLAN_MODE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
A_UINT32 freq;
A_UINT32 dataRate;
A_INT32 txPwr;
A_UINT32 antenna;
A_UINT32 enANI;
A_UINT32 scramblerOff;
A_UINT32 aifsn;
A_UINT16 pktSz;
A_UINT16 txPattern;
A_UINT32 shortGuard;
A_UINT32 numPackets;
A_UINT32 wlanMode;
} POSTPACK TCMD_CONT_TX;
#define TCMD_TXPATTERN_ZERONE 0x1
#define TCMD_TXPATTERN_ZERONE_DIS_SCRAMBLE 0x2
/* Continuous Rx
act: TCMD_CONT_RX_PROMIS - promiscuous mode (accept all incoming frames)
TCMD_CONT_RX_FILTER - filter mode (accept only frames with dest
address equal specified
mac address (set via act =3)
TCMD_CONT_RX_REPORT off mode (disable cont rx mode and get the
report from the last cont
Rx test)
TCMD_CONT_RX_SETMAC - set MacAddr mode (sets the MAC address for the
target. This Overrides
the default MAC address.)
*/
typedef enum {
TCMD_CONT_RX_PROMIS =0,
TCMD_CONT_RX_FILTER,
TCMD_CONT_RX_REPORT,
TCMD_CONT_RX_SETMAC,
TCMD_CONT_RX_SET_ANT_SWITCH_TABLE
} TCMD_CONT_RX_ACT;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 act;
A_UINT32 enANI;
PREPACK union {
struct PREPACK TCMD_CONT_RX_PARA {
A_UINT32 freq;
A_UINT32 antenna;
A_UINT32 wlanMode;
} POSTPACK para;
struct PREPACK TCMD_CONT_RX_REPORT {
A_UINT32 totalPkt;
A_INT32 rssiInDBm;
A_UINT32 crcErrPkt;
A_UINT32 secErrPkt;
A_UINT16 rateCnt[TCMD_MAX_RATES];
A_UINT16 rateCntShortGuard[TCMD_MAX_RATES];
} POSTPACK report;
struct PREPACK TCMD_CONT_RX_MAC {
A_UCHAR addr[ATH_MAC_LEN];
} POSTPACK mac;
struct PREPACK TCMD_CONT_RX_ANT_SWITCH_TABLE {
A_UINT32 antswitch1;
A_UINT32 antswitch2;
}POSTPACK antswitchtable;
} POSTPACK u;
} POSTPACK TCMD_CONT_RX;
/* Force sleep/wake test cmd
mode: TCMD_PM_WAKEUP - Wakeup the target
TCMD_PM_SLEEP - Force the target to sleep.
*/
typedef enum {
TCMD_PM_WAKEUP = 1, /* be consistent with target */
TCMD_PM_SLEEP,
TCMD_PM_DEEPSLEEP
} TCMD_PM_MODE;
typedef PREPACK struct {
A_UINT32 testCmdId;
A_UINT32 mode;
} POSTPACK TCMD_PM;
typedef enum {
TCMD_CONT_TX_ID,
TCMD_CONT_RX_ID,
TCMD_PM_ID
} TCMD_ID;
typedef PREPACK union {
TCMD_CONT_TX contTx;
TCMD_CONT_RX contRx;
TCMD_PM pm;
} POSTPACK TEST_CMD;
#ifdef __cplusplus
}
#endif
#endif /* TESTCMD_H_ */

38
drivers/staging/ath6kl/include/common/tlpm.h Normal file
View file

@ -0,0 +1,38 @@
//------------------------------------------------------------------------------
// Copyright (c) 2010 Atheros Corporation. All rights reserved.
//
//
// Permission to use, copy, modify, and/or distribute this software for any
// purpose with or without fee is hereby granted, provided that the above
// copyright notice and this permission notice appear in all copies.
//
// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
//
//
//------------------------------------------------------------------------------
//==============================================================================
// Author(s): ="Atheros"
//==============================================================================
#ifndef __TLPM_H__
#define __TLPM_H__
/* idle timeout in 16-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
#define TLPM_DEFAULT_IDLE_TIMEOUT_MS 1000
/* hex in LSB and MSB for HCI command */
#define TLPM_DEFAULT_IDLE_TIMEOUT_LSB 0xE8
#define TLPM_DEFAULT_IDLE_TIMEOUT_MSB 0x3
/* wakeup timeout in 8-bit value as in HOST_INTEREST hi_hci_uart_pwr_mgmt_params */
#define TLPM_DEFAULT_WAKEUP_TIMEOUT_MS 10
/* default UART FC polarity is low */
#define TLPM_DEFAULT_UART_FC_POLARITY 0
#endif

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