tg3: Set tx bug flags for more devices
It has been recently discovered that all tg3 devices have a 4Gb boundary DMA problem, and that all 5755 and newer devices can't handle fragments less than or equal to 8 bytes in size. This patch adjusts the flags and removes tg3_start_xmit(). tg3_start_xmit_dma_bug() has been renamed to tg3_start_xmit(). Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
parent
5b5ed8afe4
commit
2ffcc981d8
1 changed files with 33 additions and 229 deletions
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@ -5735,7 +5735,28 @@ static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
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#endif
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}
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static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
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static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
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dma_addr_t mapping, int len, u32 flags,
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u32 mss_and_is_end)
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{
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struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
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int is_end = (mss_and_is_end & 0x1);
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u32 mss = (mss_and_is_end >> 1);
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u32 vlan_tag = 0;
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if (is_end)
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flags |= TXD_FLAG_END;
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if (flags & TXD_FLAG_VLAN) {
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vlan_tag = flags >> 16;
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flags &= 0xffff;
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}
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vlan_tag |= (mss << TXD_MSS_SHIFT);
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txd->addr_hi = ((u64) mapping >> 32);
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txd->addr_lo = ((u64) mapping & 0xffffffff);
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txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
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txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
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}
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/* Workaround 4GB and 40-bit hardware DMA bugs. */
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static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
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@ -5818,202 +5839,7 @@ static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
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return ret;
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}
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static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
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dma_addr_t mapping, int len, u32 flags,
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u32 mss_and_is_end)
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{
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struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
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int is_end = (mss_and_is_end & 0x1);
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u32 mss = (mss_and_is_end >> 1);
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u32 vlan_tag = 0;
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if (is_end)
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flags |= TXD_FLAG_END;
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if (flags & TXD_FLAG_VLAN) {
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vlan_tag = flags >> 16;
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flags &= 0xffff;
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}
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vlan_tag |= (mss << TXD_MSS_SHIFT);
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txd->addr_hi = ((u64) mapping >> 32);
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txd->addr_lo = ((u64) mapping & 0xffffffff);
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txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
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txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
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}
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/* hard_start_xmit for devices that don't have any bugs and
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* support TG3_FLAG_HW_TSO_2 and TG3_FLAG_HW_TSO_3 only.
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*/
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static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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u32 len, entry, base_flags, mss;
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dma_addr_t mapping;
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struct tg3_napi *tnapi;
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struct netdev_queue *txq;
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unsigned int i, last;
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txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
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tnapi = &tp->napi[skb_get_queue_mapping(skb)];
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if (tg3_flag(tp, ENABLE_TSS))
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tnapi++;
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/* We are running in BH disabled context with netif_tx_lock
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* and TX reclaim runs via tp->napi.poll inside of a software
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* interrupt. Furthermore, IRQ processing runs lockless so we have
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* no IRQ context deadlocks to worry about either. Rejoice!
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*/
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if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
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if (!netif_tx_queue_stopped(txq)) {
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netif_tx_stop_queue(txq);
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/* This is a hard error, log it. */
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netdev_err(dev,
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"BUG! Tx Ring full when queue awake!\n");
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}
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return NETDEV_TX_BUSY;
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}
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entry = tnapi->tx_prod;
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base_flags = 0;
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mss = skb_shinfo(skb)->gso_size;
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if (mss) {
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int tcp_opt_len, ip_tcp_len;
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u32 hdrlen;
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if (skb_header_cloned(skb) &&
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pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
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dev_kfree_skb(skb);
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goto out_unlock;
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}
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if (skb_is_gso_v6(skb)) {
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hdrlen = skb_headlen(skb) - ETH_HLEN;
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} else {
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struct iphdr *iph = ip_hdr(skb);
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tcp_opt_len = tcp_optlen(skb);
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ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
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iph->check = 0;
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iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
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hdrlen = ip_tcp_len + tcp_opt_len;
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}
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if (tg3_flag(tp, HW_TSO_3)) {
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mss |= (hdrlen & 0xc) << 12;
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if (hdrlen & 0x10)
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base_flags |= 0x00000010;
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base_flags |= (hdrlen & 0x3e0) << 5;
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} else
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mss |= hdrlen << 9;
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base_flags |= (TXD_FLAG_CPU_PRE_DMA |
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TXD_FLAG_CPU_POST_DMA);
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tcp_hdr(skb)->check = 0;
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} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
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base_flags |= TXD_FLAG_TCPUDP_CSUM;
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}
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if (vlan_tx_tag_present(skb))
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base_flags |= (TXD_FLAG_VLAN |
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(vlan_tx_tag_get(skb) << 16));
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len = skb_headlen(skb);
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/* Queue skb data, a.k.a. the main skb fragment. */
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mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
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if (pci_dma_mapping_error(tp->pdev, mapping)) {
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dev_kfree_skb(skb);
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goto out_unlock;
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}
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tnapi->tx_buffers[entry].skb = skb;
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dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
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if (tg3_flag(tp, USE_JUMBO_BDFLAG) &&
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!mss && skb->len > VLAN_ETH_FRAME_LEN)
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base_flags |= TXD_FLAG_JMB_PKT;
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tg3_set_txd(tnapi, entry, mapping, len, base_flags,
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(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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entry = NEXT_TX(entry);
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/* Now loop through additional data fragments, and queue them. */
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if (skb_shinfo(skb)->nr_frags > 0) {
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last = skb_shinfo(skb)->nr_frags - 1;
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for (i = 0; i <= last; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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len = frag->size;
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mapping = pci_map_page(tp->pdev,
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frag->page,
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frag->page_offset,
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len, PCI_DMA_TODEVICE);
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if (pci_dma_mapping_error(tp->pdev, mapping))
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goto dma_error;
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tnapi->tx_buffers[entry].skb = NULL;
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dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
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mapping);
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tg3_set_txd(tnapi, entry, mapping, len,
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base_flags, (i == last) | (mss << 1));
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entry = NEXT_TX(entry);
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}
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}
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/* Packets are ready, update Tx producer idx local and on card. */
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tw32_tx_mbox(tnapi->prodmbox, entry);
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tnapi->tx_prod = entry;
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if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
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netif_tx_stop_queue(txq);
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/* netif_tx_stop_queue() must be done before checking
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* checking tx index in tg3_tx_avail() below, because in
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* tg3_tx(), we update tx index before checking for
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* netif_tx_queue_stopped().
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*/
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smp_mb();
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if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
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netif_tx_wake_queue(txq);
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}
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out_unlock:
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mmiowb();
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return NETDEV_TX_OK;
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dma_error:
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last = i;
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entry = tnapi->tx_prod;
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tnapi->tx_buffers[entry].skb = NULL;
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pci_unmap_single(tp->pdev,
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dma_unmap_addr(&tnapi->tx_buffers[entry], mapping),
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skb_headlen(skb),
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PCI_DMA_TODEVICE);
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for (i = 0; i <= last; i++) {
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skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
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entry = NEXT_TX(entry);
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pci_unmap_page(tp->pdev,
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dma_unmap_addr(&tnapi->tx_buffers[entry],
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mapping),
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frag->size, PCI_DMA_TODEVICE);
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}
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dev_kfree_skb(skb);
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return NETDEV_TX_OK;
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}
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static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
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struct net_device *);
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static netdev_tx_t tg3_start_xmit(struct sk_buff *, struct net_device *);
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/* Use GSO to workaround a rare TSO bug that may be triggered when the
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* TSO header is greater than 80 bytes.
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@ -6047,7 +5873,7 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
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nskb = segs;
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segs = segs->next;
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nskb->next = NULL;
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tg3_start_xmit_dma_bug(nskb, tp->dev);
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tg3_start_xmit(nskb, tp->dev);
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} while (segs);
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tg3_tso_bug_end:
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@ -6059,8 +5885,7 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
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/* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
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* support TG3_FLAG_HW_TSO_1 or firmware TSO only.
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*/
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static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
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struct net_device *dev)
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static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
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{
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struct tg3 *tp = netdev_priv(dev);
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u32 len, entry, base_flags, mss;
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@ -13857,14 +13682,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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}
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
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tg3_flag_set(tp, SHORT_DMA_BUG);
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else if (!tg3_flag(tp, 5755_PLUS)) {
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/* All chips can get confused if TX buffers
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* straddle the 4GB address boundary.
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*/
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tg3_flag_set(tp, 4G_DMA_BNDRY_BUG);
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if (tg3_flag(tp, 5755_PLUS))
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tg3_flag_set(tp, SHORT_DMA_BUG);
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else
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tg3_flag_set(tp, 40BIT_DMA_LIMIT_BUG);
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}
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if (tg3_flag(tp, 5717_PLUS))
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tg3_flag_set(tp, LRG_PROD_RING_CAP);
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@ -15092,23 +14918,6 @@ static const struct net_device_ops tg3_netdev_ops = {
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#endif
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};
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static const struct net_device_ops tg3_netdev_ops_dma_bug = {
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.ndo_open = tg3_open,
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.ndo_stop = tg3_close,
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.ndo_start_xmit = tg3_start_xmit_dma_bug,
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.ndo_get_stats64 = tg3_get_stats64,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_set_multicast_list = tg3_set_rx_mode,
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.ndo_set_mac_address = tg3_set_mac_addr,
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.ndo_do_ioctl = tg3_ioctl,
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.ndo_tx_timeout = tg3_tx_timeout,
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.ndo_change_mtu = tg3_change_mtu,
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.ndo_set_features = tg3_set_features,
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#ifdef CONFIG_NET_POLL_CONTROLLER
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.ndo_poll_controller = tg3_poll_controller,
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#endif
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};
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static int __devinit tg3_init_one(struct pci_dev *pdev,
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const struct pci_device_id *ent)
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{
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@ -15205,6 +15014,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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dev->ethtool_ops = &tg3_ethtool_ops;
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dev->watchdog_timeo = TG3_TX_TIMEOUT;
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dev->netdev_ops = &tg3_netdev_ops;
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dev->irq = pdev->irq;
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err = tg3_get_invariants(tp);
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@ -15214,12 +15024,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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goto err_out_iounmap;
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}
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if (tg3_flag(tp, 5755_PLUS) && !tg3_flag(tp, 5717_PLUS))
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dev->netdev_ops = &tg3_netdev_ops;
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else
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dev->netdev_ops = &tg3_netdev_ops_dma_bug;
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/* The EPB bridge inside 5714, 5715, and 5780 and any
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* device behind the EPB cannot support DMA addresses > 40-bit.
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* On 64-bit systems with IOMMU, use 40-bit dma_mask.
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