[PARISC] Further work for multiple page sizes
More work towards supporing multiple page sizes on 64-bit. Convert some assumptions that 64bit uses 3 level page tables into testing PT_NLEVELS. Also some BUG() to BUG_ON() conversions and some cleanups to assembler. Signed-off-by: Helge Deller <deller@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
This commit is contained in:
Helge Deller
Kyle McMartin
parent
d668da80d6
commit
2fd8303816
11 changed files with 198 additions and 102 deletions
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@ -138,6 +138,37 @@ config 64BIT
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enable this option otherwise. The 64bit kernel is significantly bigger
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and slower than the 32bit one.
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choice
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prompt "Kernel page size"
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default PARISC_PAGE_SIZE_4KB if !64BIT
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default PARISC_PAGE_SIZE_4KB if 64BIT
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# default PARISC_PAGE_SIZE_16KB if 64BIT
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config PARISC_PAGE_SIZE_4KB
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bool "4KB"
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help
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This lets you select the page size of the kernel. For best
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performance, a page size of 16KB is recommended. For best
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compatibility with 32bit applications, a page size of 4KB should be
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selected (the vast majority of 32bit binaries work perfectly fine
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with a larger page size).
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4KB For best 32bit compatibility
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16KB For best performance
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64KB For best performance, might give more overhead.
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If you don't know what to do, choose 4KB.
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config PARISC_PAGE_SIZE_16KB
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bool "16KB (EXPERIMENTAL)"
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depends on PA8X00 && EXPERIMENTAL
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config PARISC_PAGE_SIZE_64KB
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bool "64KB (EXPERIMENTAL)"
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depends on PA8X00 && EXPERIMENTAL
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endchoice
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config SMP
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bool "Symmetric multi-processing support"
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---help---
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@ -288,8 +288,11 @@ int main(void)
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DEFINE(ASM_PGD_ENTRY_SIZE, PGD_ENTRY_SIZE);
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DEFINE(ASM_PMD_ENTRY_SIZE, PMD_ENTRY_SIZE);
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DEFINE(ASM_PTE_ENTRY_SIZE, PTE_ENTRY_SIZE);
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DEFINE(ASM_PFN_PTE_SHIFT, PFN_PTE_SHIFT);
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DEFINE(ASM_PT_INITIAL, PT_INITIAL);
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DEFINE(ASM_PAGE_SIZE, PAGE_SIZE);
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DEFINE(ASM_PAGE_SIZE_DIV64, PAGE_SIZE/64);
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DEFINE(ASM_PAGE_SIZE_DIV128, PAGE_SIZE/128);
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BLANK();
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DEFINE(EXCDATA_IP, offsetof(struct exception_data, fault_ip));
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DEFINE(EXCDATA_SPACE, offsetof(struct exception_data, fault_space));
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@ -502,18 +502,20 @@
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* all ILP32 processes and all the kernel for machines with
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* under 4GB of memory) */
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.macro L3_ptep pgd,pte,index,va,fault
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#if PT_NLEVELS == 3 /* we might have a 2-Level scheme, e.g. with 16kb page size */
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extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
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copy %r0,\pte
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extrd,u,*= \va,31,32,%r0
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extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
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ldw,s \index(\pgd),\pgd
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extrd,u,*= \va,31,32,%r0
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extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
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bb,>=,n \pgd,_PxD_PRESENT_BIT,\fault
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extrd,u,*= \va,31,32,%r0
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extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
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shld \pgd,PxD_VALUE_SHIFT,\index
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extrd,u,*= \va,31,32,%r0
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extrd,u,*= \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
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copy \index,\pgd
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extrd,u,*<> \va,31,32,%r0
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extrd,u,*<> \va,63-ASM_PGDIR_SHIFT,64-ASM_PGDIR_SHIFT,%r0
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ldo ASM_PGD_PMD_OFFSET(\pgd),\pgd
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#endif
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L2_ptep \pgd,\pte,\index,\va,\fault
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.endm
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@ -563,10 +565,18 @@
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extrd,u,*= \pte,_PAGE_GATEWAY_BIT+32,1,%r0
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depd %r0,11,2,\prot /* If Gateway, Set PL2 to 0 */
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/* Get rid of prot bits and convert to page addr for iitlbt and idtlbt */
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/* Enforce uncacheable pages.
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* This should ONLY be use for MMIO on PA 2.0 machines.
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* Memory/DMA is cache coherent on all PA2.0 machines we support
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* (that means T-class is NOT supported) and the memory controllers
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* on most of those machines only handles cache transactions.
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*/
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extrd,u,*= \pte,_PAGE_NO_CACHE_BIT+32,1,%r0
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depi 1,12,1,\prot
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depd %r0,63,PAGE_SHIFT,\pte
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extrd,s \pte,(63-PAGE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
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/* Drop prot bits and convert to page addr for iitlbt and idtlbt */
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extrd,u \pte,(63-ASM_PFN_PTE_SHIFT)+(63-58),64-PAGE_SHIFT,\pte
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depdi _PAGE_SIZE_ENCODING_DEFAULT,63,63-58,\pte
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.endm
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/* Identical macro to make_insert_tlb above, except it
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@ -584,9 +594,8 @@
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/* Get rid of prot bits and convert to page addr for iitlba */
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depi 0,31,PAGE_SHIFT,\pte
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depi _PAGE_SIZE_ENCODING_DEFAULT,31,ASM_PFN_PTE_SHIFT,\pte
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extru \pte,24,25,\pte
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.endm
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/* This is for ILP32 PA2.0 only. The TLB insertion needs
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@ -1201,10 +1210,9 @@ intr_save:
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*/
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/* adjust isr/ior. */
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extrd,u %r16,63,7,%r1 /* get high bits from isr for ior */
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depd %r1,31,7,%r17 /* deposit them into ior */
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depdi 0,63,7,%r16 /* clear them from isr */
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extrd,u %r16,63,SPACEID_SHIFT,%r1 /* get high bits from isr for ior */
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depd %r1,31,SPACEID_SHIFT,%r17 /* deposit them into ior */
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depdi 0,63,SPACEID_SHIFT,%r16 /* clear them from isr */
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#endif
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STREG %r16, PT_ISR(%r29)
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STREG %r17, PT_IOR(%r29)
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@ -76,7 +76,7 @@ $bss_loop:
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mtctl %r4,%cr24 /* Initialize kernel root pointer */
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mtctl %r4,%cr25 /* Initialize user root pointer */
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#ifdef CONFIG_64BIT
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#if PT_NLEVELS == 3
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/* Set pmd in pgd */
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load32 PA(pmd0),%r5
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shrd %r5,PxD_VALUE_SHIFT,%r3
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@ -99,7 +99,7 @@ $bss_loop:
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stw %r3,0(%r4)
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ldo (ASM_PAGE_SIZE >> PxD_VALUE_SHIFT)(%r3),%r3
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addib,> -1,%r1,1b
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#ifdef CONFIG_64BIT
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#if PT_NLEVELS == 3
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ldo ASM_PMD_ENTRY_SIZE(%r4),%r4
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#else
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ldo ASM_PGD_ENTRY_SIZE(%r4),%r4
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@ -107,13 +107,14 @@ $bss_loop:
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/* Now initialize the PTEs themselves */
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ldo _PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */
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ldo 0+_PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */
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ldi (1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */
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load32 PA(pg0),%r1
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$pgt_fill_loop:
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STREGM %r3,ASM_PTE_ENTRY_SIZE(%r1)
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ldo ASM_PAGE_SIZE(%r3),%r3
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bb,>= %r3,31-KERNEL_INITIAL_ORDER,$pgt_fill_loop
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ldo (1<<PFN_PTE_SHIFT)(%r3),%r3 /* add one PFN */
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addib,> -1,%r11,$pgt_fill_loop
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nop
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/* Load the return address...er...crash 'n burn */
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@ -53,17 +53,17 @@ union thread_union init_thread_union
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__attribute__((aligned(128))) __attribute__((__section__(".data.init_task"))) =
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{ INIT_THREAD_INFO(init_task) };
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#ifdef __LP64__
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#if PT_NLEVELS == 3
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/* NOTE: This layout exactly conforms to the hybrid L2/L3 page table layout
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* with the first pmd adjacent to the pgd and below it. gcc doesn't actually
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* guarantee that global objects will be laid out in memory in the same order
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* as the order of declaration, so put these in different sections and use
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* the linker script to order them. */
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pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((aligned(PAGE_SIZE))) __attribute__ ((__section__ (".data.vm0.pmd"))) = { {0}, };
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pmd_t pmd0[PTRS_PER_PMD] __attribute__ ((__section__ (".data.vm0.pmd"), aligned(PAGE_SIZE)));
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#endif
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pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((aligned(PAGE_SIZE))) __attribute__ ((__section__ (".data.vm0.pgd"))) = { {0}, };
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pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((aligned(PAGE_SIZE))) __attribute__ ((__section__ (".data.vm0.pte"))) = { {0}, };
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pgd_t swapper_pg_dir[PTRS_PER_PGD] __attribute__ ((__section__ (".data.vm0.pgd"), aligned(PAGE_SIZE)));
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pte_t pg0[PT_INITIAL * PTRS_PER_PTE] __attribute__ ((__section__ (".data.vm0.pte"), aligned(PAGE_SIZE)));
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/*
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* Initial task structure.
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@ -84,8 +84,7 @@ flush_tlb_all_local:
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rfi
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nop
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1: ldil L%PA(cache_info), %r1
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ldo R%PA(cache_info)(%r1), %r1
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1: load32 PA(cache_info), %r1
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/* Flush Instruction Tlb */
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@ -212,8 +211,7 @@ flush_instruction_cache_local:
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.entry
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mtsp %r0, %sr1
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ldil L%cache_info, %r1
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ldo R%cache_info(%r1), %r1
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load32 cache_info, %r1
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/* Flush Instruction Cache */
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@ -254,8 +252,7 @@ flush_data_cache_local:
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.entry
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mtsp %r0, %sr1
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ldil L%cache_info, %r1
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ldo R%cache_info(%r1), %r1
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load32 cache_info, %r1
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/* Flush Data Cache */
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@ -303,7 +300,8 @@ copy_user_page_asm:
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*/
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ldd 0(%r25), %r19
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ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
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ldi ASM_PAGE_SIZE_DIV128, %r1
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ldw 64(%r25), %r0 /* prefetch 1 cacheline ahead */
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ldw 128(%r25), %r0 /* prefetch 2 */
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@ -368,7 +366,7 @@ copy_user_page_asm:
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* use ldd/std on a 32 bit kernel.
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*/
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ldw 0(%r25), %r19
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ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
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ldi ASM_PAGE_SIZE_DIV64, %r1
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1:
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ldw 4(%r25), %r20
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@ -461,6 +459,7 @@ copy_user_page_asm:
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sub %r25, %r1, %r23 /* move physical addr into non shadowed reg */
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ldil L%(TMPALIAS_MAP_START), %r28
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/* FIXME for different page sizes != 4k */
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#ifdef CONFIG_64BIT
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extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
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extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
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@ -551,6 +550,7 @@ __clear_user_page_asm:
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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/* FIXME: page size dependend */
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#endif
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extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
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depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
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@ -566,10 +566,10 @@ __clear_user_page_asm:
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pdtlb 0(%r28)
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#ifdef CONFIG_64BIT
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ldi 32, %r1 /* PAGE_SIZE/128 == 32 */
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ldi ASM_PAGE_SIZE_DIV128, %r1
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/* PREFETCH (Write) has not (yet) been proven to help here */
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/* #define PREFETCHW_OP ldd 256(%0), %r0 */
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/* #define PREFETCHW_OP ldd 256(%0), %r0 */
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1: std %r0, 0(%r28)
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std %r0, 8(%r28)
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@ -591,8 +591,7 @@ __clear_user_page_asm:
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ldo 128(%r28), %r28
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#else /* ! CONFIG_64BIT */
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ldi 64, %r1 /* PAGE_SIZE/64 == 64 */
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ldi ASM_PAGE_SIZE_DIV64, %r1
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1:
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stw %r0, 0(%r28)
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@ -55,7 +55,7 @@
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* pointers.
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*/
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.align 4096
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.align ASM_PAGE_SIZE
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linux_gateway_page:
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/* ADDRESS 0x00 to 0xb0 = 176 bytes / 4 bytes per insn = 44 insns */
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@ -632,7 +632,7 @@ cas_action:
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end_compare_and_swap:
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/* Make sure nothing else is placed on this page */
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.align 4096
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.align ASM_PAGE_SIZE
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.export end_linux_gateway_page
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end_linux_gateway_page:
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@ -652,7 +652,7 @@ end_linux_gateway_page:
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.section .rodata,"a"
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.align 4096
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.align ASM_PAGE_SIZE
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/* Light-weight-syscall table */
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/* Start of lws table. */
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.export lws_table
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@ -662,14 +662,14 @@ lws_table:
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LWS_ENTRY(compare_and_swap64) /* 1 - ELF64 Atomic compare and swap */
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/* End of lws table */
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.align 4096
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.align ASM_PAGE_SIZE
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.export sys_call_table
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.Lsys_call_table:
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sys_call_table:
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#include "syscall_table.S"
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#ifdef CONFIG_64BIT
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.align 4096
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.align ASM_PAGE_SIZE
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.export sys_call_table64
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.Lsys_call_table64:
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sys_call_table64:
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@ -6,6 +6,7 @@
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* Copyright (C) 2000 Michael Ang <mang with subcarrier.org>
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* Copyright (C) 2002 Randolph Chung <tausq with parisc-linux.org>
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* Copyright (C) 2003 James Bottomley <jejb with parisc-linux.org>
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* Copyright (C) 2006 Helge Deller <deller@gmx.de>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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@ -27,6 +28,7 @@
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/* needed for the processor specific cache alignment size */
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/asm-offsets.h>
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/* ld script to make hppa Linux kernel */
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#ifndef CONFIG_64BIT
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@ -68,7 +70,7 @@ SECTIONS
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RODATA
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/* writeable */
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. = ALIGN(4096); /* Make sure this is page aligned so
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. = ALIGN(ASM_PAGE_SIZE); /* Make sure this is page aligned so
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that we can properly leave these
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as writable */
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data_start = .;
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@ -82,22 +84,16 @@ SECTIONS
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.PARISC.unwind : { *(.PARISC.unwind) }
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__stop___unwind = .;
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/* rarely changed data like cpu maps */
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. = ALIGN(16);
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.data.read_mostly : { *(.data.read_mostly) }
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. = ALIGN(L1_CACHE_BYTES);
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.data : { /* Data */
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*(.data)
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*(.data.vm0.pmd)
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*(.data.vm0.pgd)
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*(.data.vm0.pte)
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CONSTRUCTORS
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}
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. = ALIGN(4096);
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/* nosave data is really only used for software suspend...it's here
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* just in case we ever implement it */
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__nosave_begin = .;
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.data_nosave : { *(.data.nosave) }
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. = ALIGN(4096);
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__nosave_end = .;
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. = ALIGN(L1_CACHE_BYTES);
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.data.cacheline_aligned : { *(.data.cacheline_aligned) }
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@ -105,12 +101,29 @@ SECTIONS
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. = ALIGN(16);
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.data.lock_aligned : { *(.data.lock_aligned) }
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/* rarely changed data like cpu maps */
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. = ALIGN(16);
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.data.read_mostly : { *(.data.read_mostly) }
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. = ALIGN(ASM_PAGE_SIZE);
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/* nosave data is really only used for software suspend...it's here
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* just in case we ever implement it */
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__nosave_begin = .;
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.data_nosave : { *(.data.nosave) }
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. = ALIGN(ASM_PAGE_SIZE);
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__nosave_end = .;
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_edata = .; /* End of data section */
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__bss_start = .; /* BSS */
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/* page table entries need to be PAGE_SIZE aligned */
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. = ALIGN(ASM_PAGE_SIZE);
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.data.vmpages : {
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*(.data.vm0.pmd)
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*(.data.vm0.pgd)
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*(.data.vm0.pte)
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}
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.bss : { *(.bss) *(COMMON) }
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__bss_stop = .;
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/* assembler code expects init_task to be 16k aligned */
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. = ALIGN(16384); /* init_task */
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.data.init_task : { *(.data.init_task) }
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@ -126,6 +139,7 @@ SECTIONS
|
|||
.dlt : { *(.dlt) }
|
||||
#endif
|
||||
|
||||
/* reserve space for interrupt stack by aligning __init* to 16k */
|
||||
. = ALIGN(16384);
|
||||
__init_begin = .;
|
||||
.init.text : {
|
||||
|
|
@ -166,7 +180,7 @@ SECTIONS
|
|||
from .altinstructions and .eh_frame */
|
||||
.exit.text : { *(.exit.text) }
|
||||
.exit.data : { *(.exit.data) }
|
||||
. = ALIGN(4096);
|
||||
. = ALIGN(ASM_PAGE_SIZE);
|
||||
__initramfs_start = .;
|
||||
.init.ramfs : { *(.init.ramfs) }
|
||||
__initramfs_end = .;
|
||||
|
|
@ -174,14 +188,10 @@ SECTIONS
|
|||
__per_cpu_start = .;
|
||||
.data.percpu : { *(.data.percpu) }
|
||||
__per_cpu_end = .;
|
||||
. = ALIGN(4096);
|
||||
. = ALIGN(ASM_PAGE_SIZE);
|
||||
__init_end = .;
|
||||
/* freed after init ends here */
|
||||
|
||||
__bss_start = .; /* BSS */
|
||||
.bss : { *(.bss) *(COMMON) }
|
||||
__bss_stop = .;
|
||||
|
||||
_end = . ;
|
||||
|
||||
/* Sections to be discarded */
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
* changed by Philipp Rumpf
|
||||
* Copyright 1999 Philipp Rumpf (prumpf@tux.org)
|
||||
* Copyright 2004 Randolph Chung (tausq@debian.org)
|
||||
* Copyright 2006 Helge Deller (deller@gmx.de)
|
||||
*
|
||||
*/
|
||||
|
||||
|
|
@ -371,7 +372,7 @@ static void __init setup_bootmem(void)
|
|||
|
||||
void free_initmem(void)
|
||||
{
|
||||
unsigned long addr;
|
||||
unsigned long addr, init_begin, init_end;
|
||||
|
||||
printk(KERN_INFO "Freeing unused kernel memory: ");
|
||||
|
||||
|
|
@ -395,8 +396,11 @@ void free_initmem(void)
|
|||
local_irq_enable();
|
||||
#endif
|
||||
|
||||
addr = (unsigned long)(&__init_begin);
|
||||
for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
|
||||
/* align __init_begin and __init_end to page size,
|
||||
ignoring linker script where we might have tried to save RAM */
|
||||
init_begin = PAGE_ALIGN((unsigned long)(&__init_begin));
|
||||
init_end = PAGE_ALIGN((unsigned long)(&__init_end));
|
||||
for (addr = init_begin; addr < init_end; addr += PAGE_SIZE) {
|
||||
ClearPageReserved(virt_to_page(addr));
|
||||
init_page_count(virt_to_page(addr));
|
||||
free_page(addr);
|
||||
|
|
@ -407,7 +411,7 @@ void free_initmem(void)
|
|||
/* set up a new led state on systems shipped LED State panel */
|
||||
pdc_chassis_send_status(PDC_CHASSIS_DIRECT_BCOMPLETE);
|
||||
|
||||
printk("%luk freed\n", (unsigned long)(&__init_end - &__init_begin) >> 10);
|
||||
printk("%luk freed\n", (init_end - init_begin) >> 10);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -639,11 +643,13 @@ static void __init map_pages(unsigned long start_vaddr, unsigned long start_padd
|
|||
* Map the fault vector writable so we can
|
||||
* write the HPMC checksum.
|
||||
*/
|
||||
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
|
||||
if (address >= ro_start && address < ro_end
|
||||
&& address != fv_addr
|
||||
&& address != gw_addr)
|
||||
pte = __mk_pte(address, PAGE_KERNEL_RO);
|
||||
else
|
||||
#endif
|
||||
pte = __mk_pte(address, pgprot);
|
||||
|
||||
if (address >= end_paddr)
|
||||
|
|
@ -874,8 +880,7 @@ unsigned long alloc_sid(void)
|
|||
flush_tlb_all(); /* flush_tlb_all() calls recycle_sids() */
|
||||
spin_lock(&sid_lock);
|
||||
}
|
||||
if (free_space_ids == 0)
|
||||
BUG();
|
||||
BUG_ON(free_space_ids == 0);
|
||||
}
|
||||
|
||||
free_space_ids--;
|
||||
|
|
@ -899,8 +904,7 @@ void free_sid(unsigned long spaceid)
|
|||
|
||||
spin_lock(&sid_lock);
|
||||
|
||||
if (*dirty_space_offset & (1L << index))
|
||||
BUG(); /* attempt to free space id twice */
|
||||
BUG_ON(*dirty_space_offset & (1L << index)); /* attempt to free space id twice */
|
||||
|
||||
*dirty_space_offset |= (1L << index);
|
||||
dirty_space_ids++;
|
||||
|
|
@ -975,7 +979,7 @@ static void recycle_sids(void)
|
|||
|
||||
static unsigned long recycle_ndirty;
|
||||
static unsigned long recycle_dirty_array[SID_ARRAY_SIZE];
|
||||
static unsigned int recycle_inuse = 0;
|
||||
static unsigned int recycle_inuse;
|
||||
|
||||
void flush_tlb_all(void)
|
||||
{
|
||||
|
|
@ -984,9 +988,7 @@ void flush_tlb_all(void)
|
|||
do_recycle = 0;
|
||||
spin_lock(&sid_lock);
|
||||
if (dirty_space_ids > RECYCLE_THRESHOLD) {
|
||||
if (recycle_inuse) {
|
||||
BUG(); /* FIXME: Use a semaphore/wait queue here */
|
||||
}
|
||||
BUG_ON(recycle_inuse); /* FIXME: Use a semaphore/wait queue here */
|
||||
get_dirty_sids(&recycle_ndirty,recycle_dirty_array);
|
||||
recycle_inuse++;
|
||||
do_recycle++;
|
||||
|
|
|
|||
|
|
@ -1,13 +1,30 @@
|
|||
#ifndef _PARISC_PAGE_H
|
||||
#define _PARISC_PAGE_H
|
||||
|
||||
/* PAGE_SHIFT determines the page size */
|
||||
#define PAGE_SHIFT 12
|
||||
#define PAGE_SIZE (1UL << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
#if !defined(__KERNEL__)
|
||||
/* this is for userspace applications (4k page size) */
|
||||
# define PAGE_SHIFT 12 /* 4k */
|
||||
# define PAGE_SIZE (1UL << PAGE_SHIFT)
|
||||
# define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __KERNEL__
|
||||
#include <linux/config.h>
|
||||
|
||||
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
|
||||
# define PAGE_SHIFT 12 /* 4k */
|
||||
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
|
||||
# define PAGE_SHIFT 14 /* 16k */
|
||||
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
|
||||
# define PAGE_SHIFT 16 /* 64k */
|
||||
#else
|
||||
# error "unknown default kernel page size"
|
||||
#endif
|
||||
#define PAGE_SIZE (1UL << PAGE_SHIFT)
|
||||
#define PAGE_MASK (~(PAGE_SIZE-1))
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <asm/types.h>
|
||||
|
|
|
|||
|
|
@ -59,16 +59,15 @@
|
|||
#define ISTACK_SIZE 32768 /* Interrupt Stack Size */
|
||||
#define ISTACK_ORDER 3
|
||||
|
||||
/* This is the size of the initially mapped kernel memory (i.e. currently
|
||||
* 0 to 1<<23 == 8MB */
|
||||
/* This is the size of the initially mapped kernel memory */
|
||||
#ifdef CONFIG_64BIT
|
||||
#define KERNEL_INITIAL_ORDER 24
|
||||
#define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */
|
||||
#else
|
||||
#define KERNEL_INITIAL_ORDER 23
|
||||
#define KERNEL_INITIAL_ORDER 23 /* 0 to 1<<23 = 8MB */
|
||||
#endif
|
||||
#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
|
||||
#define PT_NLEVELS 3
|
||||
#define PGD_ORDER 1 /* Number of pages per pgd */
|
||||
#define PMD_ORDER 1 /* Number of pages per pmd */
|
||||
|
|
@ -115,7 +114,11 @@
|
|||
|
||||
/* This calculates the number of initial pages we need for the initial
|
||||
* page tables */
|
||||
#define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
|
||||
#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
|
||||
# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
|
||||
#else
|
||||
# define PT_INITIAL (1) /* all initial PTEs fit into one page */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* pgd entries used up by user/kernel:
|
||||
|
|
@ -160,6 +163,10 @@ extern void *vmalloc_start;
|
|||
* to zero */
|
||||
#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
|
||||
|
||||
/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
|
||||
#define PFN_PTE_SHIFT 12
|
||||
|
||||
|
||||
/* this is how many bits may be used by the file functions */
|
||||
#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
|
||||
|
||||
|
|
@ -188,7 +195,8 @@ extern void *vmalloc_start;
|
|||
/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
|
||||
* are page-aligned, we don't care about the PAGE_OFFSET bits, except
|
||||
* for a few meta-information bits, so we shift the address to be
|
||||
* able to effectively address 40-bits of physical address space. */
|
||||
* able to effectively address 40/42/44-bits of physical address space
|
||||
* depending on 4k/16k/64k PAGE_SIZE */
|
||||
#define _PxD_PRESENT_BIT 31
|
||||
#define _PxD_ATTACHED_BIT 30
|
||||
#define _PxD_VALID_BIT 29
|
||||
|
|
@ -198,7 +206,7 @@ extern void *vmalloc_start;
|
|||
#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
|
||||
#define PxD_FLAG_MASK (0xf)
|
||||
#define PxD_FLAG_SHIFT (4)
|
||||
#define PxD_VALUE_SHIFT (8)
|
||||
#define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
|
@ -246,6 +254,7 @@ extern void *vmalloc_start;
|
|||
#define __S110 PAGE_RWX
|
||||
#define __S111 PAGE_RWX
|
||||
|
||||
|
||||
extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
|
||||
|
||||
/* initial page tables for 0-8MB for kernel */
|
||||
|
|
@ -272,7 +281,7 @@ extern unsigned long *empty_zero_page;
|
|||
#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
|
||||
#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
|
||||
|
||||
#ifdef CONFIG_64BIT
|
||||
#if PT_NLEVELS == 3
|
||||
/* The first entry of the permanent pmd is not there if it contains
|
||||
* the gateway marker */
|
||||
#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
|
||||
|
|
@ -282,7 +291,7 @@ extern unsigned long *empty_zero_page;
|
|||
#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
|
||||
#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
|
||||
static inline void pmd_clear(pmd_t *pmd) {
|
||||
#ifdef CONFIG_64BIT
|
||||
#if PT_NLEVELS == 3
|
||||
if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
|
||||
/* This is the entry pointing to the permanent pmd
|
||||
* attached to the pgd; cannot clear it */
|
||||
|
|
@ -303,7 +312,7 @@ static inline void pmd_clear(pmd_t *pmd) {
|
|||
#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
|
||||
#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
|
||||
static inline void pgd_clear(pgd_t *pgd) {
|
||||
#ifdef CONFIG_64BIT
|
||||
#if PT_NLEVELS == 3
|
||||
if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
|
||||
/* This is the permanent pmd attached to the pgd; cannot
|
||||
* free it */
|
||||
|
|
@ -351,7 +360,7 @@ extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return
|
|||
({ \
|
||||
pte_t __pte; \
|
||||
\
|
||||
pte_val(__pte) = ((addr)+pgprot_val(pgprot)); \
|
||||
pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
|
||||
\
|
||||
__pte; \
|
||||
})
|
||||
|
|
@ -361,20 +370,16 @@ extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return
|
|||
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
|
||||
{
|
||||
pte_t pte;
|
||||
pte_val(pte) = (pfn << PAGE_SHIFT) | pgprot_val(pgprot);
|
||||
pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
|
||||
return pte;
|
||||
}
|
||||
|
||||
/* This takes a physical page address that is used by the remapping functions */
|
||||
#define mk_pte_phys(physpage, pgprot) \
|
||||
({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
|
||||
|
||||
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
|
||||
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
|
||||
|
||||
/* Permanent address of a page. On parisc we don't have highmem. */
|
||||
|
||||
#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
|
||||
#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
|
||||
|
||||
#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
|
||||
|
||||
|
|
@ -499,6 +504,26 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
|
|||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
|
||||
/* TLB page size encoding - see table 3-1 in parisc20.pdf */
|
||||
#define _PAGE_SIZE_ENCODING_4K 0
|
||||
#define _PAGE_SIZE_ENCODING_16K 1
|
||||
#define _PAGE_SIZE_ENCODING_64K 2
|
||||
#define _PAGE_SIZE_ENCODING_256K 3
|
||||
#define _PAGE_SIZE_ENCODING_1M 4
|
||||
#define _PAGE_SIZE_ENCODING_4M 5
|
||||
#define _PAGE_SIZE_ENCODING_16M 6
|
||||
#define _PAGE_SIZE_ENCODING_64M 7
|
||||
|
||||
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
|
||||
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
|
||||
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
|
||||
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
|
||||
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
|
||||
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
|
||||
#endif
|
||||
|
||||
|
||||
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
|
||||
remap_pfn_range(vma, vaddr, pfn, size, prot)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue