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Documentation/devicetree: Add PCIe max-link-speed property

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Some of the host drivers have the requirement of knowing whether the EP
would never train at some link speed at all.  For instance, on some boards,
the link won't train at 5 GT/s but the host driver still sacrifice some
cycles to wait for the result of training at 5 GT/s as the host could
actually support 5 GT/s.  So we could parse this new property and make the
host drivers be aware of these cases.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Shawn Lin 2016-11-14 15:20:57 -06:00 committed by Bjorn Helgaas
parent 1001354ca3
commit 2fa39159b6
1 changed files with 6 additions and 0 deletions
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Documentation/devicetree/bindings/pci/pci.txt
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@ -18,3 +18,9 @@ driver implementation may support the following properties:
host bridges in the system, otherwise potentially conflicting domain numbers host bridges in the system, otherwise potentially conflicting domain numbers
may be assigned to root buses behind different host bridges. The domain may be assigned to root buses behind different host bridges. The domain
number for each host bridge in the system must be unique. number for each host bridge in the system must be unique.
- max-link-speed:
If present this property specifies PCI gen for link capability. Host
drivers could add this as a strategy to avoid unnecessary operation for
unsupported link speed, for instance, trying to do training for
unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2'
for gen2, and '1' for gen1. Any other values are invalid.