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e1000: add mmiowb() for IA64 to sync tail writes

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IA64 SMP systems were seeing TX issues with multiple cpu's attempting
to write tail registers unordered. This mmiowb() fixes the issue.

Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com>
This commit is contained in:
Jesse Brandeburg 2006-11-01 08:47:42 -08:00 committed by Jeff Garzik
parent 21c4d5e078
commit 2ce9047f5d
1 changed files with 3 additions and 0 deletions
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3
drivers/net/e1000/e1000_main.c
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@ -2867,6 +2867,9 @@ e1000_tx_queue(struct e1000_adapter *adapter, struct e1000_tx_ring *tx_ring,
tx_ring->next_to_use = i;
writel(i, adapter->hw.hw_addr + tx_ring->tdt);
/* we need this if more than one processor can write to our tail
* at a time, it syncronizes IO on IA64/Altix systems */
mmiowb();
}
/**