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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300

Browse source 
* 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300:
  MN10300: Clear ASB2364 peripheral interrupt masks before enabling interrupts
  MN10300: Fix the ASB2364 gdbport UART register defs
  MN10300: Fix ASB2364 FPGA register defs
  MN10300: Select GENERIC_HARDIRQS_NO_DEPRECATED
  MN10300: Select HAVE_GENERIC_HARDIRQS rather than GENERIC_HARDIRQS
  MN10300: Convert ASB2364 FPGA irq_chip to new functions
  MN10300: Convert ipi irq_chip to new functions
  MN10300: Convert serial irq_chip to new functions
  MN10300: Convert cpu irq_chips to new functions
  MN10300: Remove unused mn10300_intc_* functions
  MN10300: Remove stale irq_chip.end - V2
  MN10300: Use clockevents_calc_mult_shift()
  MN10300: Use clocksource_register_hz()
  MN10300: Remove stale code
This commit is contained in:
Linus Torvalds 2011-03-18 22:31:05 -07:00
commit 2c1d2470c0
14 changed files with 159 additions and 219 deletions
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18
arch/mn10300/Kconfig
View file

@ -1,7 +1,8 @@
config MN10300
def_bool y
select HAVE_OPROFILE
select GENERIC_HARDIRQS
select HAVE_GENERIC_HARDIRQS
select GENERIC_HARDIRQS_NO_DEPRECATED
config AM33_2
def_bool n
@ -53,21 +54,6 @@ config GENERIC_TIME
config GENERIC_CLOCKEVENTS
def_bool y
config GENERIC_CLOCKEVENTS_BUILD
def_bool y
depends on GENERIC_CLOCKEVENTS
config GENERIC_CLOCKEVENTS_BROADCAST
bool
config CEVT_MN10300
def_bool y
depends on GENERIC_CLOCKEVENTS
config CSRC_MN10300
def_bool y
depends on GENERIC_TIME
config GENERIC_BUG
def_bool y

5
arch/mn10300/include/asm/intctl-regs.h
View file

@ -60,11 +60,6 @@
#ifndef __ASSEMBLY__
extern void set_intr_level(int irq, u16 level);
extern void mn10300_intc_set_level(unsigned int irq, unsigned int level);
extern void mn10300_intc_clear(unsigned int irq);
extern void mn10300_intc_set(unsigned int irq);
extern void mn10300_intc_enable(unsigned int irq);
extern void mn10300_intc_disable(unsigned int irq);
extern void mn10300_set_lateack_irq_type(int irq);
#endif

5
arch/mn10300/kernel/Makefile
View file

@ -8,7 +8,8 @@ fpu-obj-$(CONFIG_FPU) := fpu.o fpu-low.o
obj-y := process.o signal.o entry.o traps.o irq.o \
ptrace.o setup.o time.o sys_mn10300.o io.o kthread.o \
switch_to.o mn10300_ksyms.o kernel_execve.o $(fpu-obj-y)
switch_to.o mn10300_ksyms.o kernel_execve.o $(fpu-obj-y) \
csrc-mn10300.o cevt-mn10300.o
obj-$(CONFIG_SMP) += smp.o smp-low.o
@ -28,5 +29,3 @@ obj-$(CONFIG_MN10300_RTC) += rtc.o
obj-$(CONFIG_PROFILE) += profile.o profile-low.o
obj-$(CONFIG_MODULES) += module.o
obj-$(CONFIG_KPROBES) += kprobes.o
obj-$(CONFIG_CSRC_MN10300) += csrc-mn10300.o
obj-$(CONFIG_CEVT_MN10300) += cevt-mn10300.o

11
arch/mn10300/kernel/cevt-mn10300.c
View file

@ -89,9 +89,10 @@ int __init init_clockevents(void)
cd->name = "Timestamp";
cd->features = CLOCK_EVT_FEAT_ONESHOT;
/* Calculate the min / max delta */
clockevent_set_clock(cd, MN10300_JCCLK);
/* Calculate shift/mult. We want to spawn at least 1 second */
clockevents_calc_mult_shift(cd, MN10300_JCCLK, 1);
/* Calculate the min / max delta */
cd->max_delta_ns = clockevent_delta2ns(TMJCBR_MAX, cd);
cd->min_delta_ns = clockevent_delta2ns(100, cd);
@ -110,9 +111,9 @@ int __init init_clockevents(void)
#if defined(CONFIG_SMP) && !defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
/* setup timer irq affinity so it only runs on this cpu */
{
struct irq_desc *desc;
desc = irq_to_desc(cd->irq);
cpumask_copy(desc->affinity, cpumask_of(cpu));
struct irq_data *data;
data = irq_get_irq_data(cd->irq);
cpumask_copy(data->affinity, cpumask_of(cpu));
iact->flags |= IRQF_NOBALANCING;
}
#endif

3
arch/mn10300/kernel/csrc-mn10300.c
View file

@ -29,7 +29,6 @@ static struct clocksource clocksource_mn10300 = {
int __init init_clocksource(void)
{
startup_timestamp_counter();
clocksource_set_clock(&clocksource_mn10300, MN10300_TSCCLK);
clocksource_register(&clocksource_mn10300);
clocksource_register_hz(&clocksource_mn10300, MN10300_TSCCLK);
return 0;
}

10
arch/mn10300/kernel/internal.h
View file

@ -33,13 +33,3 @@ extern void mn10300_low_ipi_handler(void);
* time.c
*/
extern irqreturn_t local_timer_interrupt(void);
/*
* time.c
*/
#ifdef CONFIG_CEVT_MN10300
extern void clockevent_set_clock(struct clock_event_device *, unsigned int);
#endif
#ifdef CONFIG_CSRC_MN10300
extern void clocksource_set_clock(struct clocksource *, unsigned int);
#endif

91
arch/mn10300/kernel/irq.c
View file

@ -37,8 +37,9 @@ atomic_t irq_err_count;
/*
* MN10300 interrupt controller operations
*/
static void mn10300_cpupic_ack(unsigned int irq)
static void mn10300_cpupic_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long flags;
u16 tmp;
@ -61,13 +62,14 @@ static void __mask_and_set_icr(unsigned int irq,
arch_local_irq_restore(flags);
}
static void mn10300_cpupic_mask(unsigned int irq)
static void mn10300_cpupic_mask(struct irq_data *d)
{
__mask_and_set_icr(irq, GxICR_LEVEL, 0);
__mask_and_set_icr(d->irq, GxICR_LEVEL, 0);
}
static void mn10300_cpupic_mask_ack(unsigned int irq)
static void mn10300_cpupic_mask_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
#ifdef CONFIG_SMP
unsigned long flags;
u16 tmp;
@ -85,7 +87,7 @@ static void mn10300_cpupic_mask_ack(unsigned int irq)
tmp2 = GxICR(irq);
irq_affinity_online[irq] =
any_online_cpu(*irq_desc[irq].affinity);
any_online_cpu(*d->affinity);
CROSS_GxICR(irq, irq_affinity_online[irq]) =
(tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
@ -97,13 +99,14 @@ static void mn10300_cpupic_mask_ack(unsigned int irq)
#endif /* CONFIG_SMP */
}
static void mn10300_cpupic_unmask(unsigned int irq)
static void mn10300_cpupic_unmask(struct irq_data *d)
{
__mask_and_set_icr(irq, GxICR_LEVEL, GxICR_ENABLE);
__mask_and_set_icr(d->irq, GxICR_LEVEL, GxICR_ENABLE);
}
static void mn10300_cpupic_unmask_clear(unsigned int irq)
static void mn10300_cpupic_unmask_clear(struct irq_data *d)
{
unsigned int irq = d->irq;
/* the MN10300 PIC latches its interrupt request bit, even after the
* device has ceased to assert its interrupt line and the interrupt
* channel has been disabled in the PIC, so for level-triggered
@ -121,7 +124,7 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq)
} else {
tmp = GxICR(irq);
irq_affinity_online[irq] = any_online_cpu(*irq_desc[irq].affinity);
irq_affinity_online[irq] = any_online_cpu(*d->affinity);
CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
}
@ -134,7 +137,8 @@ static void mn10300_cpupic_unmask_clear(unsigned int irq)
#ifdef CONFIG_SMP
static int
mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
mn10300_cpupic_setaffinity(struct irq_data *d, const struct cpumask *mask,
bool force)
{
unsigned long flags;
int err;
@ -142,7 +146,7 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
flags = arch_local_cli_save();
/* check irq no */
switch (irq) {
switch (d->irq) {
case TMJCIRQ:
case RESCHEDULE_IPI:
case CALL_FUNC_SINGLE_IPI:
@ -181,7 +185,7 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
break;
default:
set_bit(irq, irq_affinity_request);
set_bit(d->irq, irq_affinity_request);
err = 0;
break;
}
@ -202,15 +206,15 @@ mn10300_cpupic_setaffinity(unsigned int irq, const struct cpumask *mask)
* mask_ack() is provided), and mask_ack() just masks.
*/
static struct irq_chip mn10300_cpu_pic_level = {
.name = "cpu_l",
.disable = mn10300_cpupic_mask,
.enable = mn10300_cpupic_unmask_clear,
.ack = NULL,
.mask = mn10300_cpupic_mask,
.mask_ack = mn10300_cpupic_mask,
.unmask = mn10300_cpupic_unmask_clear,
.name = "cpu_l",
.irq_disable = mn10300_cpupic_mask,
.irq_enable = mn10300_cpupic_unmask_clear,
.irq_ack = NULL,
.irq_mask = mn10300_cpupic_mask,
.irq_mask_ack = mn10300_cpupic_mask,
.irq_unmask = mn10300_cpupic_unmask_clear,
#ifdef CONFIG_SMP
.set_affinity = mn10300_cpupic_setaffinity,
.irq_set_affinity = mn10300_cpupic_setaffinity,
#endif
};
@ -220,15 +224,15 @@ static struct irq_chip mn10300_cpu_pic_level = {
* We use the latch clearing function of the PIC as the 'ACK' function.
*/
static struct irq_chip mn10300_cpu_pic_edge = {
.name = "cpu_e",
.disable = mn10300_cpupic_mask,
.enable = mn10300_cpupic_unmask,
.ack = mn10300_cpupic_ack,
.mask = mn10300_cpupic_mask,
.mask_ack = mn10300_cpupic_mask_ack,
.unmask = mn10300_cpupic_unmask,
.name = "cpu_e",
.irq_disable = mn10300_cpupic_mask,
.irq_enable = mn10300_cpupic_unmask,
.irq_ack = mn10300_cpupic_ack,
.irq_mask = mn10300_cpupic_mask,
.irq_mask_ack = mn10300_cpupic_mask_ack,
.irq_unmask = mn10300_cpupic_unmask,
#ifdef CONFIG_SMP
.set_affinity = mn10300_cpupic_setaffinity,
.irq_set_affinity = mn10300_cpupic_setaffinity,
#endif
};
@ -252,31 +256,6 @@ void set_intr_level(int irq, u16 level)
__mask_and_set_icr(irq, GxICR_ENABLE, level);
}
void mn10300_intc_set_level(unsigned int irq, unsigned int level)
{
set_intr_level(irq, NUM2GxICR_LEVEL(level) & GxICR_LEVEL);
}
void mn10300_intc_clear(unsigned int irq)
{
__mask_and_set_icr(irq, GxICR_LEVEL | GxICR_ENABLE, GxICR_DETECT);
}
void mn10300_intc_set(unsigned int irq)
{
__mask_and_set_icr(irq, 0, GxICR_REQUEST | GxICR_DETECT);
}
void mn10300_intc_enable(unsigned int irq)
{
mn10300_cpupic_unmask(irq);
}
void mn10300_intc_disable(unsigned int irq)
{
mn10300_cpupic_mask(irq);
}
/*
* mark an interrupt to be ACK'd after interrupt handlers have been run rather
* than before
@ -296,7 +275,7 @@ void __init init_IRQ(void)
int irq;
for (irq = 0; irq < NR_IRQS; irq++)
if (irq_desc[irq].chip == &no_irq_chip)
if (get_irq_chip(irq) == &no_irq_chip)
/* due to the PIC latching interrupt requests, even
* when the IRQ is disabled, IRQ_PENDING is superfluous
* and we can use handle_level_irq() for edge-triggered
@ -384,12 +363,12 @@ int show_interrupts(struct seq_file *p, void *v)
if (i < NR_CPU_IRQS)
seq_printf(p, " %14s.%u",
irq_desc[i].chip->name,
irq_desc[i].irq_data.chip->name,
(GxICR(i) & GxICR_LEVEL) >>
GxICR_LEVEL_SHIFT);
else
seq_printf(p, " %14s",
irq_desc[i].chip->name);
irq_desc[i].irq_data.chip->name);
seq_printf(p, " %s", action->name);

16
arch/mn10300/kernel/mn10300-serial.c
View file

@ -384,17 +384,21 @@ static void mn10300_serial_mask_ack(unsigned int irq)
arch_local_irq_restore(flags);
}
static void mn10300_serial_nop(unsigned int irq)
static void mn10300_serial_chip_mask_ack(struct irq_data *d)
{
mn10300_serial_mask_ack(d->irq);
}
static void mn10300_serial_nop(struct irq_data *d)
{
}
static struct irq_chip mn10300_serial_pic = {
.name = "mnserial",
.ack = mn10300_serial_mask_ack,
.mask = mn10300_serial_mask_ack,
.mask_ack = mn10300_serial_mask_ack,
.unmask = mn10300_serial_nop,
.end = mn10300_serial_nop,
.irq_ack = mn10300_serial_chip_mask_ack,
.irq_mask = mn10300_serial_chip_mask_ack,
.irq_mask_ack = mn10300_serial_chip_mask_ack,
.irq_unmask = mn10300_serial_nop,
};

30
arch/mn10300/kernel/smp.c
View file

@ -113,15 +113,17 @@ static void init_ipi(void);
*/
static void mn10300_ipi_disable(unsigned int irq);
static void mn10300_ipi_enable(unsigned int irq);
static void mn10300_ipi_ack(unsigned int irq);
static void mn10300_ipi_nop(unsigned int irq);
static void mn10300_ipi_chip_disable(struct irq_data *d);
static void mn10300_ipi_chip_enable(struct irq_data *d);
static void mn10300_ipi_ack(struct irq_data *d);
static void mn10300_ipi_nop(struct irq_data *d);
static struct irq_chip mn10300_ipi_type = {
.name = "cpu_ipi",
.disable = mn10300_ipi_disable,
.enable = mn10300_ipi_enable,
.ack = mn10300_ipi_ack,
.eoi = mn10300_ipi_nop
.irq_disable = mn10300_ipi_chip_disable,
.irq_enable = mn10300_ipi_chip_enable,
.irq_ack = mn10300_ipi_ack,
.irq_eoi = mn10300_ipi_nop
};
static irqreturn_t smp_reschedule_interrupt(int irq, void *dev_id);
@ -236,6 +238,11 @@ static void mn10300_ipi_enable(unsigned int irq)
arch_local_irq_restore(flags);
}
static void mn10300_ipi_chip_enable(struct irq_data *d)
{
mn10300_ipi_enable(d->irq);
}
/**
* mn10300_ipi_disable - Disable an IPI
* @irq: The IPI to be disabled.
@ -254,6 +261,12 @@ static void mn10300_ipi_disable(unsigned int irq)
arch_local_irq_restore(flags);
}
static void mn10300_ipi_chip_disable(struct irq_data *d)
{
mn10300_ipi_disable(d->irq);
}
/**
* mn10300_ipi_ack - Acknowledge an IPI interrupt in the PIC
* @irq: The IPI to be acknowledged.
@ -261,8 +274,9 @@ static void mn10300_ipi_disable(unsigned int irq)
* Clear the interrupt detection flag for the IPI on the appropriate interrupt
* channel in the PIC.
*/
static void mn10300_ipi_ack(unsigned int irq)
static void mn10300_ipi_ack(struct irq_data *d)
{
unsigned int irq = d->irq;
unsigned long flags;
u16 tmp;
@ -276,7 +290,7 @@ static void mn10300_ipi_ack(unsigned int irq)
* mn10300_ipi_nop - Dummy IPI action
* @irq: The IPI to be acted upon.
*/
static void mn10300_ipi_nop(unsigned int irq)
static void mn10300_ipi_nop(struct irq_data *d)
{
}

82
arch/mn10300/kernel/time.c
View file

@ -93,79 +93,6 @@ irqreturn_t local_timer_interrupt(void)
return IRQ_HANDLED;
}
#ifndef CONFIG_GENERIC_TIME
/*
* advance the kernel's time keeping clocks (xtime and jiffies)
* - we use Timer 0 & 1 cascaded as a clock to nudge us the next time
* there's a need to update
*/
static irqreturn_t timer_interrupt(int irq, void *dev_id)
{
unsigned tsc, elapse;
irqreturn_t ret;
while (tsc = get_cycles(),
elapse = tsc - mn10300_last_tsc, /* time elapsed since last
* tick */
elapse > MN10300_TSC_PER_HZ
) {
mn10300_last_tsc += MN10300_TSC_PER_HZ;
/* advance the kernel's time tracking system */
xtime_update(1);
}
ret = local_timer_interrupt();
#ifdef CONFIG_SMP
send_IPI_allbutself(LOCAL_TIMER_IPI);
#endif
return ret;
}
static struct irqaction timer_irq = {
.handler = timer_interrupt,
.flags = IRQF_DISABLED | IRQF_SHARED | IRQF_TIMER,
.name = "timer",
};
#endif /* CONFIG_GENERIC_TIME */
#ifdef CONFIG_CSRC_MN10300
void __init clocksource_set_clock(struct clocksource *cs, unsigned int clock)
{
u64 temp;
u32 shift;
/* Find a shift value */
for (shift = 32; shift > 0; shift--) {
temp = (u64) NSEC_PER_SEC << shift;
do_div(temp, clock);
if ((temp >> 32) == 0)
break;
}
cs->shift = shift;
cs->mult = (u32) temp;
}
#endif
#if CONFIG_CEVT_MN10300
void __cpuinit clockevent_set_clock(struct clock_event_device *cd,
unsigned int clock)
{
u64 temp;
u32 shift;
/* Find a shift value */
for (shift = 32; shift > 0; shift--) {
temp = (u64) clock << shift;
do_div(temp, NSEC_PER_SEC);
if ((temp >> 32) == 0)
break;
}
cd->shift = shift;
cd->mult = (u32) temp;
}
#endif
/*
* initialise the various timers used by the main part of the kernel
*/
@ -177,11 +104,7 @@ void __init time_init(void)
*/
TMPSCNT |= TMPSCNT_ENABLE;
#ifdef CONFIG_GENERIC_TIME
init_clocksource();
#else
startup_timestamp_counter();
#endif
printk(KERN_INFO
"timestamp counter I/O clock running at %lu.%02lu"
@ -190,12 +113,7 @@ void __init time_init(void)
mn10300_last_tsc = read_timestamp_counter();
#ifdef CONFIG_GENERIC_CLOCKEVENTS
init_clockevents();
#else
reload_jiffies_counter(MN10300_JC_PER_HZ - 1);
setup_jiffies_interrupt(TMJCIRQ, &timer_irq, CONFIG_TIMER_IRQ_LEVEL);
#endif
#ifdef CONFIG_MN10300_WD_TIMER
/* start the watchdog timer */

2
arch/mn10300/unit-asb2364/include/unit/fpga-regs.h
View file

@ -14,7 +14,7 @@
#define ASB2364_FPGA_REG_RESET_USB __SYSREG(0xa900130c, u16)
#define ASB2364_FPGA_REG_RESET_AV __SYSREG(0xa9001310, u16)
#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001590+((X)*4), u16)
#define ASB2364_FPGA_REG_IRQ(X) __SYSREG(0xa9001510+((X)*4), u16)
#define ASB2364_FPGA_REG_IRQ_LAN ASB2364_FPGA_REG_IRQ(0)
#define ASB2364_FPGA_REG_IRQ_UART ASB2364_FPGA_REG_IRQ(1)
#define ASB2364_FPGA_REG_IRQ_I2C ASB2364_FPGA_REG_IRQ(2)

24
arch/mn10300/unit-asb2364/include/unit/serial.h
View file

@ -59,18 +59,18 @@ static inline void __debug_to_serial(const char *p, int n)
#define SERIAL_PORT_DFNS /* stolen by gdb-stub */
#if defined(CONFIG_GDBSTUB_ON_TTYS0)
#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
#define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 2, u8)
#define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 2, u8)
#define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 2, u8)
#define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 2, u8)
#define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
#define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 2, u8)
#define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 2, u8)
#define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 2, u8)
#define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 2, u8)
#define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 2, u8)
#define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 2, u8)
#define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 2, u8)
#define GDBPORT_SERIAL_IRQ SERIAL_IRQ
#elif defined(CONFIG_GDBSTUB_ON_TTYS1)

37
arch/mn10300/unit-asb2364/irq-fpga.c
View file

@ -17,38 +17,38 @@
/*
* FPGA PIC operations
*/
static void asb2364_fpga_mask(unsigned int irq)
static void asb2364_fpga_mask(struct irq_data *d)
{
ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0001;
ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001;
SyncExBus();
}
static void asb2364_fpga_ack(unsigned int irq)
static void asb2364_fpga_ack(struct irq_data *d)
{
ASB2364_FPGA_REG_IRQ(irq - NR_CPU_IRQS) = 0x0001;
ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001;
SyncExBus();
}
static void asb2364_fpga_mask_ack(unsigned int irq)
static void asb2364_fpga_mask_ack(struct irq_data *d)
{
ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0001;
ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_IRQ(irq - NR_CPU_IRQS) = 0x0001;
ASB2364_FPGA_REG_IRQ(d->irq - NR_CPU_IRQS) = 0x0001;
SyncExBus();
}
static void asb2364_fpga_unmask(unsigned int irq)
static void asb2364_fpga_unmask(struct irq_data *d)
{
ASB2364_FPGA_REG_MASK(irq - NR_CPU_IRQS) = 0x0000;
ASB2364_FPGA_REG_MASK(d->irq - NR_CPU_IRQS) = 0x0000;
SyncExBus();
}
static struct irq_chip asb2364_fpga_pic = {
.name = "fpga",
.ack = asb2364_fpga_ack,
.mask = asb2364_fpga_mask,
.mask_ack = asb2364_fpga_mask_ack,
.unmask = asb2364_fpga_unmask,
.irq_ack = asb2364_fpga_ack,
.irq_mask = asb2364_fpga_mask,
.irq_mask_ack = asb2364_fpga_mask_ack,
.irq_unmask = asb2364_fpga_unmask,
};
/*
@ -88,6 +88,17 @@ void __init irq_fpga_init(void)
{
int irq;
ASB2364_FPGA_REG_MASK_LAN = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_MASK_UART = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_MASK_I2C = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_MASK_USB = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_MASK_FPGA = 0x0001;
SyncExBus();
for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++)
set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq);

44
arch/mn10300/unit-asb2364/unit-init.c
View file

@ -20,13 +20,41 @@
#include <asm/processor.h>
#include <asm/irq.h>
#include <asm/intctl-regs.h>
#include <asm/serial-regs.h>
#include <unit/fpga-regs.h>
#include <unit/serial.h>
#include <unit/smsc911x.h>
#define TTYS0_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 2, u8)
#define LAN_IRQ_CFG __SYSREG(SMSC911X_BASE + 0x54, u32)
#define LAN_INT_EN __SYSREG(SMSC911X_BASE + 0x5c, u32)
/*
* initialise some of the unit hardware before gdbstub is set up
*/
asmlinkage void __init unit_init(void)
{
/* Make sure we aren't going to get unexpected interrupts */
TTYS0_SERIAL_IER = 0;
SC0RXICR = 0;
SC0TXICR = 0;
SC1RXICR = 0;
SC1TXICR = 0;
SC2RXICR = 0;
SC2TXICR = 0;
/* Attempt to reset the FPGA attached peripherals */
ASB2364_FPGA_REG_RESET_LAN = 0x0000;
SyncExBus();
ASB2364_FPGA_REG_RESET_UART = 0x0000;
SyncExBus();
ASB2364_FPGA_REG_RESET_I2C = 0x0000;
SyncExBus();
ASB2364_FPGA_REG_RESET_USB = 0x0000;
SyncExBus();
ASB2364_FPGA_REG_RESET_AV = 0x0000;
SyncExBus();
/* set up the external interrupts */
/* XIRQ[0]: NAND RXBY */
@ -56,7 +84,23 @@ asmlinkage void __init unit_init(void)
*/
asmlinkage void __init unit_setup(void)
{
/* Release the reset on the SMSC911X so that it is ready by the time we
* need it */
ASB2364_FPGA_REG_RESET_LAN = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_RESET_UART = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_RESET_I2C = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_RESET_USB = 0x0001;
SyncExBus();
ASB2364_FPGA_REG_RESET_AV = 0x0001;
SyncExBus();
/* Make sure the ethernet chipset isn't going to give us an interrupt
* storm from stuff it was doing pre-reset */
LAN_IRQ_CFG = 0;
LAN_INT_EN = 0;
}
/*