[ALSA] sparc dbri: simplifed linking time slot function
A simplified routines to link and unlink time slots. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Krzysztof Helt
Jaroslav Kysela
parent
d1fdf07e22
commit
294a30dc8c
1 changed files with 43 additions and 86 deletions
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@ -274,7 +274,6 @@ enum in_or_out { PIPEinput, PIPEoutput };
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struct dbri_pipe {
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u32 sdp; /* SDP command word */
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int nextpipe; /* Next pipe in linked list */
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int cycle; /* Offset of timeslot (bits) */
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int length; /* Length of timeslot (bits) */
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int first_desc; /* Index of first descriptor */
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int desc; /* Index of active descriptor */
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@ -312,8 +311,6 @@ struct snd_dbri {
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struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
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int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
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int chi_in_pipe;
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int chi_out_pipe;
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int chi_bpf;
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struct cs4215 mm; /* mmcodec special info */
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@ -827,92 +824,55 @@ static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
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reset_pipe(dbri, pipe);
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}
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/* FIXME: direction not needed */
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static void link_time_slot(struct snd_dbri * dbri, int pipe,
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enum in_or_out direction, int basepipe,
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int prevpipe, int nextpipe,
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int length, int cycle)
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{
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volatile s32 *cmd;
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int val;
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int prevpipe;
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int nextpipe;
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if (pipe < 0 || pipe > DBRI_MAX_PIPE || basepipe < 0 || basepipe > DBRI_MAX_PIPE) {
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if (pipe < 0 || pipe > DBRI_MAX_PIPE
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|| prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
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|| nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
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printk(KERN_ERR
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"DBRI: link_time_slot called with illegal pipe number\n");
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return;
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}
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if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
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if (dbri->pipes[pipe].sdp == 0
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|| dbri->pipes[prevpipe].sdp == 0
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|| dbri->pipes[nextpipe].sdp == 0) {
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printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
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return;
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}
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/* Deal with CHI special case:
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* "If transmission on edges 0 or 1 is desired, then cycle n
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* (where n = # of bit times per frame...) must be used."
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* - DBRI data sheet, page 11
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*/
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if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
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cycle = dbri->chi_bpf;
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if (basepipe == pipe) {
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prevpipe = pipe;
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nextpipe = pipe;
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} else {
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/* We're not initializing a new linked list (basepipe != pipe),
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* so run through the linked list and find where this pipe
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* should be sloted in, based on its cycle. CHI confuses
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* things a bit, since it has a single anchor for both its
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* transmit and receive lists.
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*/
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if (basepipe == 16) {
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if (direction == PIPEinput) {
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prevpipe = dbri->chi_in_pipe;
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} else {
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prevpipe = dbri->chi_out_pipe;
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}
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} else {
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prevpipe = basepipe;
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}
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nextpipe = dbri->pipes[prevpipe].nextpipe;
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while (dbri->pipes[nextpipe].cycle < cycle
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&& dbri->pipes[nextpipe].nextpipe != basepipe) {
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prevpipe = nextpipe;
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nextpipe = dbri->pipes[nextpipe].nextpipe;
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}
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}
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if (prevpipe == 16) {
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if (direction == PIPEinput) {
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dbri->chi_in_pipe = pipe;
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} else {
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dbri->chi_out_pipe = pipe;
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}
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} else {
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dbri->pipes[prevpipe].nextpipe = pipe;
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}
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dbri->pipes[prevpipe].nextpipe = pipe;
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dbri->pipes[pipe].nextpipe = nextpipe;
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dbri->pipes[pipe].cycle = cycle;
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dbri->pipes[pipe].length = length;
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cmd = dbri_cmdlock(dbri, NoGetLock);
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if (direction == PIPEinput) {
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val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
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*(cmd++) = DBRI_CMD(D_DTS, 0, val);
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*(cmd++) =
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D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
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*(cmd++) = 0;
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} else {
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if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
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/* Deal with CHI special case:
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* "If transmission on edges 0 or 1 is desired, then cycle n
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* (where n = # of bit times per frame...) must be used."
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* - DBRI data sheet, page 11
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*/
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if (prevpipe == 16 && cycle == 0)
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cycle = dbri->chi_bpf;
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val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
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*(cmd++) = DBRI_CMD(D_DTS, 0, val);
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*(cmd++) = 0;
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*(cmd++) =
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D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
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} else {
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val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
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*(cmd++) = DBRI_CMD(D_DTS, 0, val);
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*(cmd++) =
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D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
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*(cmd++) = 0;
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}
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dbri_cmdsend(dbri, cmd);
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@ -1192,21 +1152,18 @@ static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_sla
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} else {
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int pipe;
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for (pipe = dbri->chi_in_pipe;
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pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
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unlink_time_slot(dbri, pipe, PIPEinput,
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16, dbri->pipes[pipe].nextpipe);
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}
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for (pipe = dbri->chi_out_pipe;
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pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
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unlink_time_slot(dbri, pipe, PIPEoutput,
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16, dbri->pipes[pipe].nextpipe);
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}
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cmd = dbri_cmdlock(dbri, GetLock);
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for (pipe = 0; pipe < DBRI_NO_PIPES; pipe++ )
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if ( pipe != 16 ) {
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if (dbri->pipes[pipe].sdp & D_SDP_TO_SER)
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unlink_time_slot(dbri, pipe, PIPEoutput,
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16, dbri->pipes[pipe].nextpipe);
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else
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unlink_time_slot(dbri, pipe, PIPEinput,
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16, dbri->pipes[pipe].nextpipe);
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}
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cmd = dbri_cmdlock(dbri, GetLock);
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}
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dbri->chi_in_pipe = 16;
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dbri->chi_out_pipe = 16;
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if (master_or_slave == CHIslave) {
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/* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
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@ -1397,10 +1354,10 @@ static void cs4215_open(struct snd_dbri * dbri)
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*/
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data_width = dbri->mm.channels * dbri->mm.precision;
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link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
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link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
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link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
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link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
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link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
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/* FIXME: enable CHI after _setdata? */
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tmp = sbus_readl(dbri->regs + REG0);
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@ -1466,9 +1423,9 @@ static int cs4215_setctrl(struct snd_dbri * dbri)
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* Pipe 19: Receive timeslot 7 (version).
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*/
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link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
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link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
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link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
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link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
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link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
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link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
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/* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
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dbri->mm.ctrl[0] &= ~CS4215_CLB;
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@ -2445,11 +2402,11 @@ static void dbri_debug_read(struct snd_info_entry * entry,
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struct dbri_pipe *pptr = &dbri->pipes[pipe];
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snd_iprintf(buffer,
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"Pipe %d: %s SDP=0x%x desc=%d, "
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"len=%d @ %d next %d\n",
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"len=%d next %d\n",
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pipe,
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((pptr->sdp & D_SDP_TO_SER) ? "output" : "input"),
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pptr->sdp, pptr->desc,
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pptr->length, pptr->cycle, pptr->nextpipe);
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pptr->length, pptr->nextpipe);
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}
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}
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}
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