sfc: Allocate SRAM between buffer table and descriptor caches at init time
Each port has a block of 64-bit SRAM that is divided between buffer table and descriptor cache regions at initialisation time. Currently we use a fixed allocation, but it needs to be changed to support larger numbers of queues. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
This commit is contained in:
parent
a9a5250627
commit
28e47c498a
6 changed files with 50 additions and 14 deletions
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@ -1420,6 +1420,8 @@ static int efx_probe_nic(struct efx_nic *efx)
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if (rc)
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goto fail;
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efx->type->dimension_resources(efx);
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if (efx->n_channels > 1)
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get_random_bytes(&efx->rx_hash_key, sizeof(efx->rx_hash_key));
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for (i = 0; i < ARRAY_SIZE(efx->rx_indir_table); i++)
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@ -1333,6 +1333,12 @@ static int falcon_probe_nvconfig(struct efx_nic *efx)
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return rc;
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}
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static void falcon_dimension_resources(struct efx_nic *efx)
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{
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efx->rx_dc_base = 0x20000;
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efx->tx_dc_base = 0x26000;
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}
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/* Probe all SPI devices on the NIC */
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static void falcon_probe_spi_devices(struct efx_nic *efx)
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{
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@ -1749,6 +1755,7 @@ const struct efx_nic_type falcon_a1_nic_type = {
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.probe = falcon_probe_nic,
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.remove = falcon_remove_nic,
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.init = falcon_init_nic,
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.dimension_resources = falcon_dimension_resources,
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.fini = efx_port_dummy_op_void,
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.monitor = falcon_monitor,
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.map_reset_reason = falcon_map_reset_reason,
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@ -1783,8 +1790,6 @@ const struct efx_nic_type falcon_a1_nic_type = {
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.max_interrupt_mode = EFX_INT_MODE_MSI,
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.phys_addr_channels = 4,
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.timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
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.tx_dc_base = 0x130000,
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.rx_dc_base = 0x100000,
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.offload_features = NETIF_F_IP_CSUM,
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};
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@ -1792,6 +1797,7 @@ const struct efx_nic_type falcon_b0_nic_type = {
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.probe = falcon_probe_nic,
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.remove = falcon_remove_nic,
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.init = falcon_init_nic,
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.dimension_resources = falcon_dimension_resources,
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.fini = efx_port_dummy_op_void,
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.monitor = falcon_monitor,
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.map_reset_reason = falcon_map_reset_reason,
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@ -1835,8 +1841,6 @@ const struct efx_nic_type falcon_b0_nic_type = {
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* interrupt handler only supports 32
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* channels */
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.timer_period_max = 1 << FRF_AB_TC_TIMER_VAL_WIDTH,
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.tx_dc_base = 0x130000,
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.rx_dc_base = 0x100000,
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.offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
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};
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@ -658,6 +658,9 @@ struct efx_filter_state;
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* should be allocated for this NIC
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* @rxq_entries: Size of receive queues requested by user.
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* @txq_entries: Size of transmit queues requested by user.
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* @tx_dc_base: Base qword address in SRAM of TX queue descriptor caches
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* @rx_dc_base: Base qword address in SRAM of RX queue descriptor caches
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* @sram_lim_qw: Qword address limit of SRAM
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* @next_buffer_table: First available buffer table id
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* @n_channels: Number of channels in use
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* @n_rx_channels: Number of channels used for RX (= number of RX queues)
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@ -753,6 +756,9 @@ struct efx_nic {
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unsigned rxq_entries;
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unsigned txq_entries;
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unsigned tx_dc_base;
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unsigned rx_dc_base;
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unsigned sram_lim_qw;
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unsigned next_buffer_table;
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unsigned n_channels;
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unsigned n_rx_channels;
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@ -839,6 +845,8 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
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* @probe: Probe the controller
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* @remove: Free resources allocated by probe()
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* @init: Initialise the controller
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* @dimension_resources: Dimension controller resources (buffer table,
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* and VIs once the available interrupt resources are clear)
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* @fini: Shut down the controller
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* @monitor: Periodic function for polling link state and hardware monitor
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* @map_reset_reason: Map ethtool reset reason to a reset method
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@ -878,8 +886,6 @@ static inline unsigned int efx_port_num(struct efx_nic *efx)
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* @phys_addr_channels: Number of channels with physically addressed
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* descriptors
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* @timer_period_max: Maximum period of interrupt timer (in ticks)
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* @tx_dc_base: Base address in SRAM of TX queue descriptor caches
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* @rx_dc_base: Base address in SRAM of RX queue descriptor caches
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* @offload_features: net_device feature flags for protocol offload
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* features implemented in hardware
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*/
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@ -887,6 +893,7 @@ struct efx_nic_type {
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int (*probe)(struct efx_nic *efx);
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void (*remove)(struct efx_nic *efx);
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int (*init)(struct efx_nic *efx);
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void (*dimension_resources)(struct efx_nic *efx);
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void (*fini)(struct efx_nic *efx);
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void (*monitor)(struct efx_nic *efx);
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enum reset_type (*map_reset_reason)(enum reset_type reason);
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@ -923,8 +930,6 @@ struct efx_nic_type {
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unsigned int max_interrupt_mode;
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unsigned int phys_addr_channels;
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unsigned int timer_period_max;
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unsigned int tx_dc_base;
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unsigned int rx_dc_base;
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netdev_features_t offload_features;
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};
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@ -1609,6 +1609,23 @@ void efx_nic_fini_interrupt(struct efx_nic *efx)
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free_irq(efx->legacy_irq, efx);
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}
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void efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw)
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{
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unsigned vi_count, buftbl_min;
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/* Account for the buffer table entries backing the datapath channels
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* and the descriptor caches for those channels.
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*/
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buftbl_min = ((efx->n_rx_channels * EFX_MAX_DMAQ_SIZE +
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efx->n_tx_channels * EFX_TXQ_TYPES * EFX_MAX_DMAQ_SIZE +
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efx->n_channels * EFX_MAX_EVQ_SIZE)
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* sizeof(efx_qword_t) / EFX_BUF_SIZE);
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vi_count = max(efx->n_channels, efx->n_tx_channels * EFX_TXQ_TYPES);
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efx->tx_dc_base = sram_lim_qw - vi_count * TX_DC_ENTRIES;
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efx->rx_dc_base = efx->tx_dc_base - vi_count * RX_DC_ENTRIES;
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}
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u32 efx_nic_fpga_ver(struct efx_nic *efx)
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{
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efx_oword_t altera_build;
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@ -1621,11 +1638,9 @@ void efx_nic_init_common(struct efx_nic *efx)
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efx_oword_t temp;
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/* Set positions of descriptor caches in SRAM. */
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
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efx->type->tx_dc_base / 8);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, efx->tx_dc_base);
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efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
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efx->type->rx_dc_base / 8);
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EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, efx->rx_dc_base);
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efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
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/* Set TX descriptor cache size. */
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@ -230,6 +230,8 @@ extern void falcon_start_nic_stats(struct efx_nic *efx);
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extern void falcon_stop_nic_stats(struct efx_nic *efx);
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extern void falcon_setup_xaui(struct efx_nic *efx);
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extern int falcon_reset_xaui(struct efx_nic *efx);
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extern void
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efx_nic_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);
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extern void efx_nic_init_common(struct efx_nic *efx);
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extern void efx_nic_push_rx_indir_table(struct efx_nic *efx);
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@ -225,6 +225,15 @@ static int siena_probe_nvconfig(struct efx_nic *efx)
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return rc;
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}
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static void siena_dimension_resources(struct efx_nic *efx)
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{
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/* Each port has a small block of internal SRAM dedicated to
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* the buffer table and descriptor caches. In theory we can
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* map both blocks to one port, but we don't.
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*/
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efx_nic_dimension_resources(efx, FR_CZ_BUF_FULL_TBL_ROWS / 2);
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}
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static int siena_probe_nic(struct efx_nic *efx)
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{
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struct siena_nic_data *nic_data;
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@ -619,6 +628,7 @@ const struct efx_nic_type siena_a0_nic_type = {
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.probe = siena_probe_nic,
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.remove = siena_remove_nic,
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.init = siena_init_nic,
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.dimension_resources = siena_dimension_resources,
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.fini = efx_port_dummy_op_void,
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.monitor = NULL,
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.map_reset_reason = siena_map_reset_reason,
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@ -657,8 +667,6 @@ const struct efx_nic_type siena_a0_nic_type = {
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* interrupt handler only supports 32
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* channels */
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.timer_period_max = 1 << FRF_CZ_TC_TIMER_VAL_WIDTH,
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.tx_dc_base = 0x88000,
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.rx_dc_base = 0x68000,
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.offload_features = (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
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NETIF_F_RXHASH | NETIF_F_NTUPLE),
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};
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