[WATCHDOG] omap_wdt.c: sync linux-omap changes
These are changes that have been sitting in linux-omap and were never sent upstream. Hopefully, it'll never happen again at least for this driver. Signed-off-by: Felipe Balbi <felipe.balbi@nokia.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Felipe Balbi
Wim Van Sebroeck
parent
e6bb42e3d6
commit
2817142f31
3 changed files with 203 additions and 129 deletions
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@ -441,16 +441,8 @@ static inline void omap_init_uwire(void) {}
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#if defined(CONFIG_OMAP_WATCHDOG) || defined(CONFIG_OMAP_WATCHDOG_MODULE)
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#ifdef CONFIG_ARCH_OMAP24XX
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#define OMAP_WDT_BASE 0x48022000
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#else
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#define OMAP_WDT_BASE 0xfffeb000
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#endif
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static struct resource wdt_resources[] = {
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{
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.start = OMAP_WDT_BASE,
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.end = OMAP_WDT_BASE + 0x4f,
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.flags = IORESOURCE_MEM,
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},
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};
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@ -464,6 +456,19 @@ static struct platform_device omap_wdt_device = {
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static void omap_init_wdt(void)
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{
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if (cpu_is_omap16xx())
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wdt_resources[0].start = 0xfffeb000;
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else if (cpu_is_omap2420())
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wdt_resources[0].start = 0x48022000; /* WDT2 */
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else if (cpu_is_omap2430())
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wdt_resources[0].start = 0x49016000; /* WDT2 */
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else if (cpu_is_omap343x())
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wdt_resources[0].start = 0x48314000; /* WDT2 */
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else
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return;
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wdt_resources[0].end = wdt_resources[0].start + 0x4f;
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(void) platform_device_register(&omap_wdt_device);
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}
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#else
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@ -1,7 +1,7 @@
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/*
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* linux/drivers/char/watchdog/omap_wdt.c
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* omap_wdt.c
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*
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* Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
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* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
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*
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* Author: MontaVista Software, Inc.
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* <gdavis@mvista.com> or <source@mvista.com>
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@ -47,50 +47,63 @@
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#include "omap_wdt.h"
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static struct platform_device *omap_wdt_dev;
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static unsigned timer_margin;
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module_param(timer_margin, uint, 0);
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MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
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static int omap_wdt_users;
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static struct clk *armwdt_ck;
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static struct clk *mpu_wdt_ick;
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static struct clk *mpu_wdt_fck;
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static unsigned int wdt_trgr_pattern = 0x1234;
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static spinlock_t wdt_lock;
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static void omap_wdt_ping(void)
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struct omap_wdt_dev {
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void __iomem *base; /* physical */
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struct device *dev;
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int omap_wdt_users;
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struct clk *armwdt_ck;
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struct clk *mpu_wdt_ick;
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struct clk *mpu_wdt_fck;
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struct resource *mem;
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struct miscdevice omap_wdt_miscdev;
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};
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static void omap_wdt_ping(struct omap_wdt_dev *wdev)
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{
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void __iomem *base = wdev->base;
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/* wait for posted write to complete */
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while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
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while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
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cpu_relax();
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wdt_trgr_pattern = ~wdt_trgr_pattern;
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omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
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omap_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
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/* wait for posted write to complete */
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while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
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while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
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cpu_relax();
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/* reloaded WCRR from WLDR */
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}
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static void omap_wdt_enable(void)
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static void omap_wdt_enable(struct omap_wdt_dev *wdev)
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{
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void __iomem *base;
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base = wdev->base;
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/* Sequence to enable the watchdog */
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omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
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while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
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omap_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
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while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
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cpu_relax();
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omap_writel(0x4444, OMAP_WATCHDOG_SPR);
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while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
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omap_writel(0x4444, base + OMAP_WATCHDOG_SPR);
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while ((omap_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
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cpu_relax();
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}
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static void omap_wdt_disable(void)
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static void omap_wdt_disable(struct omap_wdt_dev *wdev)
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{
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void __iomem *base;
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base = wdev->base;
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/* sequence required to disable watchdog */
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omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
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omap_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
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cpu_relax();
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omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
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omap_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
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cpu_relax();
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}
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@ -103,15 +116,17 @@ static void omap_wdt_adjust_timeout(unsigned new_timeout)
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timer_margin = new_timeout;
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}
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static void omap_wdt_set_timeout(void)
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static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
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{
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u32 pre_margin = GET_WLDR_VAL(timer_margin);
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void __iomem *base;
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base = wdev->base;
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/* just count up at 32 KHz */
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
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cpu_relax();
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omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
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omap_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
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cpu_relax();
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}
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@ -121,65 +136,69 @@ static void omap_wdt_set_timeout(void)
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static int omap_wdt_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
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struct omap_wdt_dev *wdev;
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void __iomem *base;
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wdev = platform_get_drvdata(omap_wdt_dev);
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base = wdev->base;
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if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
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return -EBUSY;
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if (cpu_is_omap16xx())
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clk_enable(armwdt_ck); /* Enable the clock */
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clk_enable(wdev->armwdt_ck); /* Enable the clock */
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if (cpu_is_omap24xx()) {
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clk_enable(mpu_wdt_ick); /* Enable the interface clock */
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clk_enable(mpu_wdt_fck); /* Enable the functional clock */
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if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
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clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */
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clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */
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}
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/* initialize prescaler */
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
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cpu_relax();
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omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
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while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
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omap_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
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while (omap_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
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cpu_relax();
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omap_wdt_set_timeout();
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omap_wdt_enable();
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file->private_data = (void *) wdev;
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omap_wdt_set_timeout(wdev);
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omap_wdt_enable(wdev);
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return nonseekable_open(inode, file);
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}
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static int omap_wdt_release(struct inode *inode, struct file *file)
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{
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struct omap_wdt_dev *wdev;
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wdev = file->private_data;
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/*
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* Shut off the timer unless NOWAYOUT is defined.
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*/
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#ifndef CONFIG_WATCHDOG_NOWAYOUT
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omap_wdt_disable();
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if (cpu_is_omap16xx()) {
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clk_disable(armwdt_ck); /* Disable the clock */
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clk_put(armwdt_ck);
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armwdt_ck = NULL;
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}
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omap_wdt_disable(wdev);
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if (cpu_is_omap24xx()) {
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clk_disable(mpu_wdt_ick); /* Disable the clock */
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clk_disable(mpu_wdt_fck); /* Disable the clock */
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clk_put(mpu_wdt_ick);
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clk_put(mpu_wdt_fck);
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mpu_wdt_ick = NULL;
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mpu_wdt_fck = NULL;
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if (cpu_is_omap16xx())
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clk_disable(wdev->armwdt_ck); /* Disable the clock */
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if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
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clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */
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clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */
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}
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#else
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printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
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#endif
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omap_wdt_users = 0;
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wdev->omap_wdt_users = 0;
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return 0;
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}
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static ssize_t omap_wdt_write(struct file *file, const char __user *data,
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size_t len, loff_t *ppos)
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{
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struct omap_wdt_dev *wdev;
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wdev = file->private_data;
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/* Refresh LOAD_TIME. */
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if (len) {
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spin_lock(&wdt_lock);
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omap_wdt_ping();
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omap_wdt_ping(wdev);
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spin_unlock(&wdt_lock);
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}
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return len;
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@ -188,12 +207,14 @@ static ssize_t omap_wdt_write(struct file *file, const char __user *data,
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static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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struct omap_wdt_dev *wdev;
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int new_margin;
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static const struct watchdog_info ident = {
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.identity = "OMAP Watchdog",
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.options = WDIOF_SETTIMEOUT,
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.firmware_version = 0,
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};
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wdev = file->private_data;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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@ -210,7 +231,7 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
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(int __user *)arg);
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case WDIOC_KEEPALIVE:
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spin_lock(&wdt_lock);
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omap_wdt_ping();
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omap_wdt_ping(wdev);
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spin_unlock(&wdt_lock);
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return 0;
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case WDIOC_SETTIMEOUT:
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@ -219,11 +240,11 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
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omap_wdt_adjust_timeout(new_margin);
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spin_lock(&wdt_lock);
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omap_wdt_disable();
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omap_wdt_set_timeout();
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omap_wdt_enable();
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omap_wdt_disable(wdev);
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omap_wdt_set_timeout(wdev);
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omap_wdt_enable(wdev);
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omap_wdt_ping();
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omap_wdt_ping(wdev);
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spin_unlock(&wdt_lock);
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/* Fall */
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case WDIOC_GETTIMEOUT:
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@ -241,96 +262,150 @@ static const struct file_operations omap_wdt_fops = {
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.release = omap_wdt_release,
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};
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static struct miscdevice omap_wdt_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &omap_wdt_fops,
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};
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static int __init omap_wdt_probe(struct platform_device *pdev)
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{
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struct resource *res, *mem;
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int ret;
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struct omap_wdt_dev *wdev;
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/* reserve static register mappings */
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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if (omap_wdt_dev)
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return -EBUSY;
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mem = request_mem_region(res->start, res->end - res->start + 1,
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pdev->name);
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if (mem == NULL)
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return -EBUSY;
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platform_set_drvdata(pdev, mem);
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omap_wdt_users = 0;
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wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
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if (!wdev) {
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ret = -ENOMEM;
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goto fail;
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}
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wdev->omap_wdt_users = 0;
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wdev->mem = mem;
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if (cpu_is_omap16xx()) {
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armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
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if (IS_ERR(armwdt_ck)) {
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ret = PTR_ERR(armwdt_ck);
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armwdt_ck = NULL;
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wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
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if (IS_ERR(wdev->armwdt_ck)) {
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ret = PTR_ERR(wdev->armwdt_ck);
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wdev->armwdt_ck = NULL;
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goto fail;
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}
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}
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if (cpu_is_omap24xx()) {
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mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
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if (IS_ERR(mpu_wdt_ick)) {
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ret = PTR_ERR(mpu_wdt_ick);
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mpu_wdt_ick = NULL;
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wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
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if (IS_ERR(wdev->mpu_wdt_ick)) {
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ret = PTR_ERR(wdev->mpu_wdt_ick);
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wdev->mpu_wdt_ick = NULL;
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goto fail;
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}
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mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
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if (IS_ERR(mpu_wdt_fck)) {
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ret = PTR_ERR(mpu_wdt_fck);
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mpu_wdt_fck = NULL;
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wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
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if (IS_ERR(wdev->mpu_wdt_fck)) {
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ret = PTR_ERR(wdev->mpu_wdt_fck);
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wdev->mpu_wdt_fck = NULL;
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goto fail;
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}
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}
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omap_wdt_disable();
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if (cpu_is_omap34xx()) {
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wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick");
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if (IS_ERR(wdev->mpu_wdt_ick)) {
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ret = PTR_ERR(wdev->mpu_wdt_ick);
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wdev->mpu_wdt_ick = NULL;
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goto fail;
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}
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wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck");
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if (IS_ERR(wdev->mpu_wdt_fck)) {
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ret = PTR_ERR(wdev->mpu_wdt_fck);
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wdev->mpu_wdt_fck = NULL;
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goto fail;
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}
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}
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wdev->base = (void __iomem *) (mem->start);
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platform_set_drvdata(pdev, wdev);
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omap_wdt_disable(wdev);
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omap_wdt_adjust_timeout(timer_margin);
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omap_wdt_miscdev.parent = &pdev->dev;
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ret = misc_register(&omap_wdt_miscdev);
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wdev->omap_wdt_miscdev.parent = &pdev->dev;
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wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
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wdev->omap_wdt_miscdev.name = "watchdog";
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wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
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ret = misc_register(&(wdev->omap_wdt_miscdev));
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if (ret)
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goto fail;
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pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
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pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
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omap_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
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timer_margin);
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/* autogate OCP interface clock */
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omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
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omap_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG);
|
||||
|
||||
omap_wdt_dev = pdev;
|
||||
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
if (armwdt_ck)
|
||||
clk_put(armwdt_ck);
|
||||
if (mpu_wdt_ick)
|
||||
clk_put(mpu_wdt_ick);
|
||||
if (mpu_wdt_fck)
|
||||
clk_put(mpu_wdt_fck);
|
||||
release_resource(mem);
|
||||
if (wdev) {
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
if (wdev->armwdt_ck)
|
||||
clk_put(wdev->armwdt_ck);
|
||||
if (wdev->mpu_wdt_ick)
|
||||
clk_put(wdev->mpu_wdt_ick);
|
||||
if (wdev->mpu_wdt_fck)
|
||||
clk_put(wdev->mpu_wdt_fck);
|
||||
kfree(wdev);
|
||||
}
|
||||
if (mem) {
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void omap_wdt_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
omap_wdt_disable();
|
||||
struct omap_wdt_dev *wdev;
|
||||
wdev = platform_get_drvdata(pdev);
|
||||
|
||||
if (wdev->omap_wdt_users)
|
||||
omap_wdt_disable(wdev);
|
||||
}
|
||||
|
||||
static int omap_wdt_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *mem = platform_get_drvdata(pdev);
|
||||
misc_deregister(&omap_wdt_miscdev);
|
||||
release_resource(mem);
|
||||
if (armwdt_ck)
|
||||
clk_put(armwdt_ck);
|
||||
if (mpu_wdt_ick)
|
||||
clk_put(mpu_wdt_ick);
|
||||
if (mpu_wdt_fck)
|
||||
clk_put(mpu_wdt_fck);
|
||||
struct omap_wdt_dev *wdev;
|
||||
wdev = platform_get_drvdata(pdev);
|
||||
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
if (!res)
|
||||
return -ENOENT;
|
||||
|
||||
misc_deregister(&(wdev->omap_wdt_miscdev));
|
||||
release_mem_region(res->start, res->end - res->start + 1);
|
||||
platform_set_drvdata(pdev, NULL);
|
||||
if (wdev->armwdt_ck) {
|
||||
clk_put(wdev->armwdt_ck);
|
||||
wdev->armwdt_ck = NULL;
|
||||
}
|
||||
if (wdev->mpu_wdt_ick) {
|
||||
clk_put(wdev->mpu_wdt_ick);
|
||||
wdev->mpu_wdt_ick = NULL;
|
||||
}
|
||||
if (wdev->mpu_wdt_fck) {
|
||||
clk_put(wdev->mpu_wdt_fck);
|
||||
wdev->mpu_wdt_fck = NULL;
|
||||
}
|
||||
kfree(wdev);
|
||||
omap_wdt_dev = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -344,16 +419,20 @@ static int omap_wdt_remove(struct platform_device *pdev)
|
|||
|
||||
static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
if (omap_wdt_users)
|
||||
omap_wdt_disable();
|
||||
struct omap_wdt_dev *wdev;
|
||||
wdev = platform_get_drvdata(pdev);
|
||||
if (wdev->omap_wdt_users)
|
||||
omap_wdt_disable(wdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int omap_wdt_resume(struct platform_device *pdev)
|
||||
{
|
||||
if (omap_wdt_users) {
|
||||
omap_wdt_enable();
|
||||
omap_wdt_ping();
|
||||
struct omap_wdt_dev *wdev;
|
||||
wdev = platform_get_drvdata(pdev);
|
||||
if (wdev->omap_wdt_users) {
|
||||
omap_wdt_enable(wdev);
|
||||
omap_wdt_ping(wdev);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -30,25 +30,15 @@
|
|||
#ifndef _OMAP_WATCHDOG_H
|
||||
#define _OMAP_WATCHDOG_H
|
||||
|
||||
#define OMAP1610_WATCHDOG_BASE 0xfffeb000
|
||||
#define OMAP2420_WATCHDOG_BASE 0x48022000 /*WDT Timer 2 */
|
||||
|
||||
#ifdef CONFIG_ARCH_OMAP24XX
|
||||
#define OMAP_WATCHDOG_BASE OMAP2420_WATCHDOG_BASE
|
||||
#else
|
||||
#define OMAP_WATCHDOG_BASE OMAP1610_WATCHDOG_BASE
|
||||
#define RM_RSTST_WKUP 0
|
||||
#endif
|
||||
|
||||
#define OMAP_WATCHDOG_REV (OMAP_WATCHDOG_BASE + 0x00)
|
||||
#define OMAP_WATCHDOG_SYS_CONFIG (OMAP_WATCHDOG_BASE + 0x10)
|
||||
#define OMAP_WATCHDOG_STATUS (OMAP_WATCHDOG_BASE + 0x14)
|
||||
#define OMAP_WATCHDOG_CNTRL (OMAP_WATCHDOG_BASE + 0x24)
|
||||
#define OMAP_WATCHDOG_CRR (OMAP_WATCHDOG_BASE + 0x28)
|
||||
#define OMAP_WATCHDOG_LDR (OMAP_WATCHDOG_BASE + 0x2c)
|
||||
#define OMAP_WATCHDOG_TGR (OMAP_WATCHDOG_BASE + 0x30)
|
||||
#define OMAP_WATCHDOG_WPS (OMAP_WATCHDOG_BASE + 0x34)
|
||||
#define OMAP_WATCHDOG_SPR (OMAP_WATCHDOG_BASE + 0x48)
|
||||
#define OMAP_WATCHDOG_REV (0x00)
|
||||
#define OMAP_WATCHDOG_SYS_CONFIG (0x10)
|
||||
#define OMAP_WATCHDOG_STATUS (0x14)
|
||||
#define OMAP_WATCHDOG_CNTRL (0x24)
|
||||
#define OMAP_WATCHDOG_CRR (0x28)
|
||||
#define OMAP_WATCHDOG_LDR (0x2c)
|
||||
#define OMAP_WATCHDOG_TGR (0x30)
|
||||
#define OMAP_WATCHDOG_WPS (0x34)
|
||||
#define OMAP_WATCHDOG_SPR (0x48)
|
||||
|
||||
/* Using the prescaler, the OMAP watchdog could go for many
|
||||
* months before firing. These limits work without scaling,
|
||||
|
|
|
|||
Loading…
Reference in a new issue