Merge branch 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6
* 'idle-release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-idle-2.6: intel_idle: do not use the LAPIC timer for ATOM C2 intel_idle: add initial Sandy Bridge support acpi_idle: delete bogus data from cpuidle_state.power_usage intel_idle: delete bogus data from cpuidle_state.power_usage intel_idle: simplify test for leave_mm()
This commit is contained in:
commit
27afe58fe6
2 changed files with 46 additions and 16 deletions
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@ -1013,7 +1013,6 @@ static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
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strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
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state->exit_latency = cx->latency;
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state->target_residency = cx->latency * latency_factor;
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state->power_usage = cx->power;
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state->flags = 0;
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switch (cx->type) {
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@ -74,7 +74,7 @@ static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
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static unsigned int mwait_substates;
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/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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static unsigned int lapic_timer_reliable_states;
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static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state);
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@ -94,7 +94,6 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x00,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 3,
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.power_usage = 1000,
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.target_residency = 6,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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@ -103,7 +102,6 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x10,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.power_usage = 500,
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.target_residency = 80,
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.enter = &intel_idle },
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{ /* MWAIT C3 */
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@ -112,11 +110,46 @@ static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x20,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.power_usage = 350,
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.target_residency = 800,
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.enter = &intel_idle },
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};
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static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
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{ /* MWAIT C0 */ },
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{ /* MWAIT C1 */
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.name = "SNB-C1",
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.desc = "MWAIT 0x00",
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.driver_data = (void *) 0x00,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.target_residency = 4,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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.name = "SNB-C3",
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.desc = "MWAIT 0x10",
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.driver_data = (void *) 0x10,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 160,
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.enter = &intel_idle },
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{ /* MWAIT C3 */
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.name = "SNB-C6",
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.desc = "MWAIT 0x20",
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.driver_data = (void *) 0x20,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 104,
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.target_residency = 208,
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.enter = &intel_idle },
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{ /* MWAIT C4 */
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.name = "SNB-C7",
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.desc = "MWAIT 0x30",
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.driver_data = (void *) 0x30,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 109,
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.target_residency = 300,
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.enter = &intel_idle },
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};
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static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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{ /* MWAIT C0 */ },
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{ /* MWAIT C1 */
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@ -125,7 +158,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x00,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 1,
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.power_usage = 1000,
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.target_residency = 4,
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.enter = &intel_idle },
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{ /* MWAIT C2 */
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@ -134,7 +166,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x10,
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.flags = CPUIDLE_FLAG_TIME_VALID,
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.exit_latency = 20,
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.power_usage = 500,
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.target_residency = 80,
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.enter = &intel_idle },
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{ /* MWAIT C3 */ },
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@ -144,7 +175,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x30,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 100,
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.power_usage = 250,
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.target_residency = 400,
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.enter = &intel_idle },
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{ /* MWAIT C5 */ },
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@ -154,7 +184,6 @@ static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
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.driver_data = (void *) 0x52,
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.flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 140,
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.power_usage = 150,
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.target_residency = 560,
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.enter = &intel_idle },
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};
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@ -179,13 +208,10 @@ static int intel_idle(struct cpuidle_device *dev, struct cpuidle_state *state)
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local_irq_disable();
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/*
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* If the state flag indicates that the TLB will be flushed or if this
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* is the deepest c-state supported, do a voluntary leave mm to avoid
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* costly and mostly unnecessary wakeups for flushing the user TLB's
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* associated with the active mm.
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* leave_mm() to avoid costly and often unnecessary wakeups
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* for flushing the user TLB's associated with the active mm.
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*/
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED ||
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(&dev->states[dev->state_count - 1] == state))
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if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
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leave_mm(cpu);
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if (!(lapic_timer_reliable_states & (1 << (cstate))))
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@ -269,9 +295,14 @@ static int intel_idle_probe(void)
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case 0x1C: /* 28 - Atom Processor */
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case 0x26: /* 38 - Lincroft Atom Processor */
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lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
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lapic_timer_reliable_states = (1 << 1); /* C1 */
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cpuidle_state_table = atom_cstates;
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break;
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case 0x2A: /* SNB */
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case 0x2D: /* SNB Xeon */
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cpuidle_state_table = snb_cstates;
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break;
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#ifdef FUTURE_USE
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case 0x17: /* 23 - Core 2 Duo */
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lapic_timer_reliable_states = (1 << 2) | (1 << 1); /* C2, C1 */
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