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ARM: OMAP3+: dpll: assign clk rate from rounded rate during rate set

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The rounded rate can differ from target rate, so to better reflect
reality set clk->rate equal to the rounded rate when setting DPLL frequency.
This avoids issues where the DPLL frequency is slightly different than what
debugfs clock tree reports using the old target rate.

An example of a clock that requires this is DPLL_ABE on OMAP4 which
can have a 4x multiplier on top of the usual MN dividers depending on
register settings.  This requires a special round_rate function that
might yield a rate different from the initial target.

Signed-off-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
Mike Turquette 2011-10-07 00:53:00 -06:00 committed by Paul Walmsley
parent addf888c69
commit 273a1ce9cf
1 changed files with 1 additions and 1 deletions
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arch/arm/mach-omap2/dpll3xxx.c
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@ -455,7 +455,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
new_parent = dd->clk_bypass; new_parent = dd->clk_bypass;
} else { } else {
if (dd->last_rounded_rate != rate) if (dd->last_rounded_rate != rate)
clk->round_rate(clk, rate); rate = clk->round_rate(clk, rate);
if (dd->last_rounded_rate == 0) if (dd->last_rounded_rate == 0)
return -EINVAL; return -EINVAL;