e100: Optionally use I/O mode only to access register space
It appears that some systems still like e100 better if it uses I/O access mode. Setting the new parameter use_io=1 will cause all driver instances to use io mapping to access the register space on the e100 device. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Jesse Brandeburg
Jeff Garzik
parent
948cd43fed
commit
27345bb684
1 changed files with 39 additions and 33 deletions
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@ -159,7 +159,7 @@
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#define DRV_NAME "e100"
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#define DRV_EXT "-NAPI"
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#define DRV_VERSION "3.5.17-k2"DRV_EXT
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#define DRV_VERSION "3.5.17-k4"DRV_EXT
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#define DRV_DESCRIPTION "Intel(R) PRO/100 Network Driver"
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#define DRV_COPYRIGHT "Copyright(c) 1999-2006 Intel Corporation"
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#define PFX DRV_NAME ": "
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@ -174,10 +174,13 @@ MODULE_VERSION(DRV_VERSION);
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static int debug = 3;
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static int eeprom_bad_csum_allow = 0;
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static int use_io = 0;
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module_param(debug, int, 0);
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module_param(eeprom_bad_csum_allow, int, 0);
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module_param(use_io, int, 0);
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MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
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MODULE_PARM_DESC(eeprom_bad_csum_allow, "Allow bad eeprom checksums");
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MODULE_PARM_DESC(use_io, "Force use of i/o access mode");
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#define DPRINTK(nlevel, klevel, fmt, args...) \
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(void)((NETIF_MSG_##nlevel & nic->msg_enable) && \
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printk(KERN_##klevel PFX "%s: %s: " fmt, nic->netdev->name, \
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@ -584,7 +587,7 @@ static inline void e100_write_flush(struct nic *nic)
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{
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/* Flush previous PCI writes through intermediate bridges
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* by doing a benign read */
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(void)readb(&nic->csr->scb.status);
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(void)ioread8(&nic->csr->scb.status);
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}
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static void e100_enable_irq(struct nic *nic)
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@ -592,7 +595,7 @@ static void e100_enable_irq(struct nic *nic)
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unsigned long flags;
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spin_lock_irqsave(&nic->cmd_lock, flags);
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writeb(irq_mask_none, &nic->csr->scb.cmd_hi);
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iowrite8(irq_mask_none, &nic->csr->scb.cmd_hi);
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e100_write_flush(nic);
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spin_unlock_irqrestore(&nic->cmd_lock, flags);
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}
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@ -602,7 +605,7 @@ static void e100_disable_irq(struct nic *nic)
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unsigned long flags;
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spin_lock_irqsave(&nic->cmd_lock, flags);
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writeb(irq_mask_all, &nic->csr->scb.cmd_hi);
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iowrite8(irq_mask_all, &nic->csr->scb.cmd_hi);
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e100_write_flush(nic);
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spin_unlock_irqrestore(&nic->cmd_lock, flags);
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}
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@ -611,11 +614,11 @@ static void e100_hw_reset(struct nic *nic)
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{
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/* Put CU and RU into idle with a selective reset to get
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* device off of PCI bus */
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writel(selective_reset, &nic->csr->port);
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iowrite32(selective_reset, &nic->csr->port);
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e100_write_flush(nic); udelay(20);
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/* Now fully reset device */
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writel(software_reset, &nic->csr->port);
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iowrite32(software_reset, &nic->csr->port);
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e100_write_flush(nic); udelay(20);
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/* Mask off our interrupt line - it's unmasked after reset */
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@ -632,7 +635,7 @@ static int e100_self_test(struct nic *nic)
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nic->mem->selftest.signature = 0;
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nic->mem->selftest.result = 0xFFFFFFFF;
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writel(selftest | dma_addr, &nic->csr->port);
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iowrite32(selftest | dma_addr, &nic->csr->port);
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e100_write_flush(nic);
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/* Wait 10 msec for self-test to complete */
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msleep(10);
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@ -670,23 +673,23 @@ static void e100_eeprom_write(struct nic *nic, u16 addr_len, u16 addr, u16 data)
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for(j = 0; j < 3; j++) {
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/* Chip select */
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writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
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iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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for(i = 31; i >= 0; i--) {
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ctrl = (cmd_addr_data[j] & (1 << i)) ?
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eecs | eedi : eecs;
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writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
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iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
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iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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}
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/* Wait 10 msec for cmd to complete */
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msleep(10);
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/* Chip deselect */
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writeb(0, &nic->csr->eeprom_ctrl_lo);
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iowrite8(0, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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}
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};
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@ -702,21 +705,21 @@ static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
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cmd_addr_data = ((op_read << *addr_len) | addr) << 16;
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/* Chip select */
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writeb(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
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iowrite8(eecs | eesk, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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/* Bit-bang to read word from eeprom */
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for(i = 31; i >= 0; i--) {
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ctrl = (cmd_addr_data & (1 << i)) ? eecs | eedi : eecs;
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writeb(ctrl, &nic->csr->eeprom_ctrl_lo);
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iowrite8(ctrl, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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writeb(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
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iowrite8(ctrl | eesk, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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/* Eeprom drives a dummy zero to EEDO after receiving
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* complete address. Use this to adjust addr_len. */
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ctrl = readb(&nic->csr->eeprom_ctrl_lo);
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ctrl = ioread8(&nic->csr->eeprom_ctrl_lo);
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if(!(ctrl & eedo) && i > 16) {
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*addr_len -= (i - 16);
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i = 17;
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@ -726,7 +729,7 @@ static u16 e100_eeprom_read(struct nic *nic, u16 *addr_len, u16 addr)
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}
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/* Chip deselect */
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writeb(0, &nic->csr->eeprom_ctrl_lo);
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iowrite8(0, &nic->csr->eeprom_ctrl_lo);
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e100_write_flush(nic); udelay(4);
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return le16_to_cpu(data);
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@ -797,7 +800,7 @@ static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
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/* Previous command is accepted when SCB clears */
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for(i = 0; i < E100_WAIT_SCB_TIMEOUT; i++) {
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if(likely(!readb(&nic->csr->scb.cmd_lo)))
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if(likely(!ioread8(&nic->csr->scb.cmd_lo)))
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break;
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cpu_relax();
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if(unlikely(i > E100_WAIT_SCB_FAST))
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@ -809,8 +812,8 @@ static int e100_exec_cmd(struct nic *nic, u8 cmd, dma_addr_t dma_addr)
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}
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if(unlikely(cmd != cuc_resume))
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writel(dma_addr, &nic->csr->scb.gen_ptr);
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writeb(cmd, &nic->csr->scb.cmd_lo);
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iowrite32(dma_addr, &nic->csr->scb.gen_ptr);
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iowrite8(cmd, &nic->csr->scb.cmd_lo);
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err_unlock:
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spin_unlock_irqrestore(&nic->cmd_lock, flags);
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@ -888,7 +891,7 @@ static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
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*/
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spin_lock_irqsave(&nic->mdio_lock, flags);
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for (i = 100; i; --i) {
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if (readl(&nic->csr->mdi_ctrl) & mdi_ready)
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if (ioread32(&nic->csr->mdi_ctrl) & mdi_ready)
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break;
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udelay(20);
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}
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@ -898,11 +901,11 @@ static u16 mdio_ctrl(struct nic *nic, u32 addr, u32 dir, u32 reg, u16 data)
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spin_unlock_irqrestore(&nic->mdio_lock, flags);
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return 0; /* No way to indicate timeout error */
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}
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writel((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
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iowrite32((reg << 16) | (addr << 21) | dir | data, &nic->csr->mdi_ctrl);
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for (i = 0; i < 100; i++) {
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udelay(20);
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if ((data_out = readl(&nic->csr->mdi_ctrl)) & mdi_ready)
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if ((data_out = ioread32(&nic->csr->mdi_ctrl)) & mdi_ready)
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break;
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}
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spin_unlock_irqrestore(&nic->mdio_lock, flags);
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@ -1311,7 +1314,7 @@ static inline int e100_exec_cb_wait(struct nic *nic, struct sk_buff *skb,
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}
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/* ack any interupts, something could have been set */
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writeb(~0, &nic->csr->scb.stat_ack);
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iowrite8(~0, &nic->csr->scb.stat_ack);
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/* if the command failed, or is not OK, notify and return */
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if (!counter || !(cb->status & cpu_to_le16(cb_ok))) {
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@ -1573,7 +1576,7 @@ static void e100_watchdog(unsigned long data)
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* accidentally, due to hardware that shares a register between the
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* interrupt mask bit and the SW Interrupt generation bit */
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spin_lock_irq(&nic->cmd_lock);
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writeb(readb(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
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iowrite8(ioread8(&nic->csr->scb.cmd_hi) | irq_sw_gen,&nic->csr->scb.cmd_hi);
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e100_write_flush(nic);
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spin_unlock_irq(&nic->cmd_lock);
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@ -1902,7 +1905,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id)
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{
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struct net_device *netdev = dev_id;
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struct nic *nic = netdev_priv(netdev);
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u8 stat_ack = readb(&nic->csr->scb.stat_ack);
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u8 stat_ack = ioread8(&nic->csr->scb.stat_ack);
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DPRINTK(INTR, DEBUG, "stat_ack = 0x%02X\n", stat_ack);
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@ -1911,7 +1914,7 @@ static irqreturn_t e100_intr(int irq, void *dev_id)
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return IRQ_NONE;
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/* Ack interrupt(s) */
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writeb(stat_ack, &nic->csr->scb.stat_ack);
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iowrite8(stat_ack, &nic->csr->scb.stat_ack);
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if(likely(netif_rx_schedule_prep(netdev))) {
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e100_disable_irq(nic);
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@ -2053,7 +2056,7 @@ static void e100_tx_timeout_task(struct work_struct *work)
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struct net_device *netdev = nic->netdev;
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DPRINTK(TX_ERR, DEBUG, "scb.status=0x%02X\n",
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readb(&nic->csr->scb.status));
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ioread8(&nic->csr->scb.status));
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e100_down(netdev_priv(netdev));
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e100_up(netdev_priv(netdev));
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}
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@ -2176,9 +2179,9 @@ static void e100_get_regs(struct net_device *netdev,
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int i;
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regs->version = (1 << 24) | nic->rev_id;
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buff[0] = readb(&nic->csr->scb.cmd_hi) << 24 |
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readb(&nic->csr->scb.cmd_lo) << 16 |
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readw(&nic->csr->scb.status);
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buff[0] = ioread8(&nic->csr->scb.cmd_hi) << 24 |
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ioread8(&nic->csr->scb.cmd_lo) << 16 |
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ioread16(&nic->csr->scb.status);
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for(i = E100_PHY_REGS; i >= 0; i--)
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buff[1 + E100_PHY_REGS - i] =
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mdio_read(netdev, nic->mii.phy_id, i);
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@ -2550,7 +2553,10 @@ static int __devinit e100_probe(struct pci_dev *pdev,
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SET_MODULE_OWNER(netdev);
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SET_NETDEV_DEV(netdev, &pdev->dev);
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nic->csr = ioremap(pci_resource_start(pdev, 0), sizeof(struct csr));
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if (use_io)
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DPRINTK(PROBE, INFO, "using i/o access mode\n");
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nic->csr = pci_iomap(pdev, (use_io ? 1 : 0), sizeof(struct csr));
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if(!nic->csr) {
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DPRINTK(PROBE, ERR, "Cannot map device registers, aborting.\n");
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err = -ENOMEM;
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@ -2627,7 +2633,7 @@ static int __devinit e100_probe(struct pci_dev *pdev,
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DPRINTK(PROBE, INFO, "addr 0x%llx, irq %d, "
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"MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n",
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(unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
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(unsigned long long)pci_resource_start(pdev, use_io ? 1 : 0), pdev->irq,
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netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
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netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
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@ -2636,7 +2642,7 @@ static int __devinit e100_probe(struct pci_dev *pdev,
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err_out_free:
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e100_free(nic);
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err_out_iounmap:
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iounmap(nic->csr);
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pci_iounmap(pdev, nic->csr);
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err_out_free_res:
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pci_release_regions(pdev);
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err_out_disable_pdev:
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