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Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6

Browse source 
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging-2.6: (25 commits)
  staging: at76_usb wireless driver
  Staging: workaround build system bug
  Staging: Lindent sxg.c
  Staging: SLICOSS: Call pci_release_regions at driver exit
  Staging: SLICOSS: Fix remaining type names
  Staging: SLICOSS: Fix warnings due to static usage
  Staging: SLICOSS: lots of checkpatch fixes
  Staging: go7007 v4l fixes
  Staging: Fix gcc warnings in sxg
  Staging: add echo cancelation module
  Staging: add wlan-ng prism2 usb driver
  Staging: add w35und wifi driver
  Staging: USB/IP: add host driver
  Staging: USB/IP: add client driver
  Staging: USB/IP: add common functions needed
  Staging: add the go7007 video driver
  Staging: add me4000 pci data collection driver
  Staging: add me4000 firmware files
  Staging: add sxg network driver
  Staging: add Alacritech slicoss network driver
  ...

Fixed up conflicts due to taint flags changes and MAINTAINERS cleanup in
MAINTAINERS, include/linux/kernel.h and kernel/panic.c.
This commit is contained in:
Linus Torvalds 2008-10-17 09:50:12 -07:00
commit 26e9a39777
211 changed files with 152422 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
Documentation/sysctl/kernel.txt
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@ -369,4 +369,5 @@ can be ORed together:
2 - A module was force loaded by insmod -f.
Set by modutils >= 2.4.9 and module-init-tools.
4 - Unsafe SMP processors: SMP with CPUs not designed for SMP.
64 - A module from drivers/staging was loaded.

9
MAINTAINERS
View file

@ -3937,7 +3937,7 @@ M: jbglaw@lug-owl.de
L: linux-kernel@vger.kernel.org
S: Maintained
STABLE BRANCH:
STABLE BRANCH
P: Greg Kroah-Hartman
M: greg@kroah.com
P: Chris Wright
@ -3945,6 +3945,13 @@ M: chrisw@sous-sol.org
L: stable@kernel.org
S: Maintained
STAGING SUBSYSTEM
P: Greg Kroah-Hartman
M: gregkh@suse.de
L: linux-kernel@vger.kernel.org
T: quilt kernel.org/pub/linux/kernel/people/gregkh/gregkh-2.6/
S: Maintained
STARFIRE/DURALAN NETWORK DRIVER
P: Ion Badulescu
M: ionut@cs.columbia.edu

2
drivers/Kconfig
View file

@ -101,4 +101,6 @@ source "drivers/auxdisplay/Kconfig"
source "drivers/uio/Kconfig"
source "drivers/xen/Kconfig"
source "drivers/staging/Kconfig"
endmenu

1
drivers/Makefile
View file

@ -99,3 +99,4 @@ obj-$(CONFIG_OF) += of/
obj-$(CONFIG_SSB) += ssb/
obj-$(CONFIG_VIRTIO) += virtio/
obj-$(CONFIG_REGULATOR) += regulator/
obj-$(CONFIG_STAGING) += staging/

46
drivers/staging/Kconfig Normal file
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@ -0,0 +1,46 @@
menuconfig STAGING
bool "Staging drivers"
default n
---help---
This option allows you to select a number of drivers that are
not of the "normal" Linux kernel quality level. These drivers
are placed here in order to get a wider audience for use of
them. Please note that these drivers are under heavy
development, may or may not work, and may contain userspace
interfaces that most likely will be changed in the near
future.
Using any of these drivers will taint your kernel which might
affect support options from both the community, and various
commercial support orginizations.
If you wish to work on these drivers, to help improve them, or
to report problems you have with them, please see the
driver_name.README file in the drivers/staging/ directory to
see what needs to be worked on, and who to contact.
If in doubt, say N here.
if STAGING
source "drivers/staging/et131x/Kconfig"
source "drivers/staging/slicoss/Kconfig"
source "drivers/staging/sxg/Kconfig"
source "drivers/staging/me4000/Kconfig"
source "drivers/staging/go7007/Kconfig"
source "drivers/staging/usbip/Kconfig"
source "drivers/staging/winbond/Kconfig"
source "drivers/staging/wlan-ng/Kconfig"
source "drivers/staging/echo/Kconfig"
source "drivers/staging/at76_usb/Kconfig"
endif # STAGING

15
drivers/staging/Makefile Normal file
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@ -0,0 +1,15 @@
# Makefile for staging directory
# fix for build system bug...
obj-$(CONFIG_STAGING) += staging.o
obj-$(CONFIG_ET131X) += et131x/
obj-$(CONFIG_SLICOSS) += slicoss/
obj-$(CONFIG_SXG) += sxg/
obj-$(CONFIG_ME4000) += me4000/
obj-$(CONFIG_VIDEO_GO7007) += go7007/
obj-$(CONFIG_USB_IP_COMMON) += usbip/
obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
obj-$(CONFIG_USB_ATMEL) += at76_usb/

8
drivers/staging/at76_usb/Kconfig Normal file
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@ -0,0 +1,8 @@
config USB_ATMEL
tristate "Atmel at76c503/at76c505/at76c505a USB cards"
depends on WLAN_80211 && USB
default N
select FW_LOADER
---help---
Enable support for USB Wireless devices using Atmel at76c503,
at76c505 or at76c505a chips.

1
drivers/staging/at76_usb/Makefile Normal file
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@ -0,0 +1 @@
obj-$(CONFIG_USB_ATMEL) += at76_usb.o

2
drivers/staging/at76_usb/TODO Normal file
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@ -0,0 +1,2 @@
rewrite the driver to use the proper in-kernel wireless stack
instead of using its own.

5559
drivers/staging/at76_usb/at76_usb.c Normal file
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File diff suppressed because it is too large Load diff

619
drivers/staging/at76_usb/at76_usb.h Normal file
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@ -0,0 +1,619 @@
/*
* Copyright (c) 2002,2003 Oliver Kurth
* (c) 2003,2004 Joerg Albert <joerg.albert@gmx.de>
* (c) 2007 Guido Guenther <agx@sigxcpu.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This driver was based on information from the Sourceforge driver
* released and maintained by Atmel:
*
* http://sourceforge.net/projects/atmelwlandriver/
*
* Although the code was completely re-written,
* it would have been impossible without Atmel's decision to
* release an Open Source driver (unfortunately the firmware was
* kept binary only). Thanks for that decision to Atmel!
*/
#ifndef _AT76_USB_H
#define _AT76_USB_H
/* Board types */
enum board_type {
BOARD_503_ISL3861 = 1,
BOARD_503_ISL3863 = 2,
BOARD_503 = 3,
BOARD_503_ACC = 4,
BOARD_505 = 5,
BOARD_505_2958 = 6,
BOARD_505A = 7,
BOARD_505AMX = 8
};
/* our private ioctl's */
/* preamble length (0 - long, 1 - short, 2 - auto) */
#define AT76_SET_SHORT_PREAMBLE (SIOCIWFIRSTPRIV + 0)
#define AT76_GET_SHORT_PREAMBLE (SIOCIWFIRSTPRIV + 1)
/* which debug channels are enabled */
#define AT76_SET_DEBUG (SIOCIWFIRSTPRIV + 2)
#define AT76_GET_DEBUG (SIOCIWFIRSTPRIV + 3)
/* power save mode (incl. the Atmel proprietary smart save mode) */
#define AT76_SET_POWERSAVE_MODE (SIOCIWFIRSTPRIV + 4)
#define AT76_GET_POWERSAVE_MODE (SIOCIWFIRSTPRIV + 5)
/* min and max channel times for scan */
#define AT76_SET_SCAN_TIMES (SIOCIWFIRSTPRIV + 6)
#define AT76_GET_SCAN_TIMES (SIOCIWFIRSTPRIV + 7)
/* scan mode (0 - active, 1 - passive) */
#define AT76_SET_SCAN_MODE (SIOCIWFIRSTPRIV + 8)
#define AT76_GET_SCAN_MODE (SIOCIWFIRSTPRIV + 9)
#define CMD_STATUS_IDLE 0x00
#define CMD_STATUS_COMPLETE 0x01
#define CMD_STATUS_UNKNOWN 0x02
#define CMD_STATUS_INVALID_PARAMETER 0x03
#define CMD_STATUS_FUNCTION_NOT_SUPPORTED 0x04
#define CMD_STATUS_TIME_OUT 0x07
#define CMD_STATUS_IN_PROGRESS 0x08
#define CMD_STATUS_HOST_FAILURE 0xff
#define CMD_STATUS_SCAN_FAILED 0xf0
/* answers to get op mode */
#define OPMODE_NONE 0x00
#define OPMODE_NORMAL_NIC_WITH_FLASH 0x01
#define OPMODE_HW_CONFIG_MODE 0x02
#define OPMODE_DFU_MODE_WITH_FLASH 0x03
#define OPMODE_NORMAL_NIC_WITHOUT_FLASH 0x04
#define CMD_SET_MIB 0x01
#define CMD_GET_MIB 0x02
#define CMD_SCAN 0x03
#define CMD_JOIN 0x04
#define CMD_START_IBSS 0x05
#define CMD_RADIO_ON 0x06
#define CMD_RADIO_OFF 0x07
#define CMD_STARTUP 0x0B
#define MIB_LOCAL 0x01
#define MIB_MAC_ADDR 0x02
#define MIB_MAC 0x03
#define MIB_MAC_MGMT 0x05
#define MIB_MAC_WEP 0x06
#define MIB_PHY 0x07
#define MIB_FW_VERSION 0x08
#define MIB_MDOMAIN 0x09
#define ADHOC_MODE 1
#define INFRASTRUCTURE_MODE 2
/* values for struct mib_local, field preamble_type */
#define PREAMBLE_TYPE_LONG 0
#define PREAMBLE_TYPE_SHORT 1
#define PREAMBLE_TYPE_AUTO 2
/* values for tx_rate */
#define TX_RATE_1MBIT 0
#define TX_RATE_2MBIT 1
#define TX_RATE_5_5MBIT 2
#define TX_RATE_11MBIT 3
#define TX_RATE_AUTO 4
/* power management modes */
#define AT76_PM_OFF 1
#define AT76_PM_ON 2
#define AT76_PM_SMART 3
struct hwcfg_r505 {
u8 cr39_values[14];
u8 reserved1[14];
u8 bb_cr[14];
u8 pidvid[4];
u8 mac_addr[ETH_ALEN];
u8 regulatory_domain;
u8 reserved2[14];
u8 cr15_values[14];
u8 reserved3[3];
} __attribute__((packed));
struct hwcfg_rfmd {
u8 cr20_values[14];
u8 cr21_values[14];
u8 bb_cr[14];
u8 pidvid[4];
u8 mac_addr[ETH_ALEN];
u8 regulatory_domain;
u8 low_power_values[14];
u8 normal_power_values[14];
u8 reserved1[3];
} __attribute__((packed));
struct hwcfg_intersil {
u8 mac_addr[ETH_ALEN];
u8 cr31_values[14];
u8 cr58_values[14];
u8 pidvid[4];
u8 regulatory_domain;
u8 reserved[1];
} __attribute__((packed));
union at76_hwcfg {
struct hwcfg_intersil i;
struct hwcfg_rfmd r3;
struct hwcfg_r505 r5;
};
#define WEP_SMALL_KEY_LEN (40 / 8)
#define WEP_LARGE_KEY_LEN (104 / 8)
struct at76_card_config {
u8 exclude_unencrypted;
u8 promiscuous_mode;
u8 short_retry_limit;
u8 encryption_type;
__le16 rts_threshold;
__le16 fragmentation_threshold; /* 256..2346 */
u8 basic_rate_set[4];
u8 auto_rate_fallback; /* 0,1 */
u8 channel;
u8 privacy_invoked;
u8 wep_default_key_id; /* 0..3 */
u8 current_ssid[32];
u8 wep_default_key_value[4][WEP_KEY_LEN];
u8 ssid_len;
u8 short_preamble;
__le16 beacon_period;
} __attribute__((packed));
struct at76_command {
u8 cmd;
u8 reserved;
__le16 size;
u8 data[0];
} __attribute__((packed));
/* Length of Atmel-specific Rx header before 802.11 frame */
#define AT76_RX_HDRLEN offsetof(struct at76_rx_buffer, packet)
struct at76_rx_buffer {
__le16 wlength;
u8 rx_rate;
u8 newbss;
u8 fragmentation;
u8 rssi;
u8 link_quality;
u8 noise_level;
__le32 rx_time;
u8 packet[IEEE80211_FRAME_LEN + IEEE80211_FCS_LEN];
} __attribute__((packed));
/* Length of Atmel-specific Tx header before 802.11 frame */
#define AT76_TX_HDRLEN offsetof(struct at76_tx_buffer, packet)
struct at76_tx_buffer {
__le16 wlength;
u8 tx_rate;
u8 padding;
u8 reserved[4];
u8 packet[IEEE80211_FRAME_LEN + IEEE80211_FCS_LEN];
} __attribute__((packed));
/* defines for scan_type below */
#define SCAN_TYPE_ACTIVE 0
#define SCAN_TYPE_PASSIVE 1
struct at76_req_scan {
u8 bssid[ETH_ALEN];
u8 essid[32];
u8 scan_type;
u8 channel;
__le16 probe_delay;
__le16 min_channel_time;
__le16 max_channel_time;
u8 essid_size;
u8 international_scan;
} __attribute__((packed));
struct at76_req_ibss {
u8 bssid[ETH_ALEN];
u8 essid[32];
u8 bss_type;
u8 channel;
u8 essid_size;
u8 reserved[3];
} __attribute__((packed));
struct at76_req_join {
u8 bssid[ETH_ALEN];
u8 essid[32];
u8 bss_type;
u8 channel;
__le16 timeout;
u8 essid_size;
u8 reserved;
} __attribute__((packed));
struct set_mib_buffer {
u8 type;
u8 size;
u8 index;
u8 reserved;
union {
u8 byte;
__le16 word;
u8 addr[ETH_ALEN];
} data;
} __attribute__((packed));
struct mib_local {
u16 reserved0;
u8 beacon_enable;
u8 txautorate_fallback;
u8 reserved1;
u8 ssid_size;
u8 promiscuous_mode;
u16 reserved2;
u8 preamble_type;
u16 reserved3;
} __attribute__((packed));
struct mib_mac_addr {
u8 mac_addr[ETH_ALEN];
u8 res[2]; /* ??? */
u8 group_addr[4][ETH_ALEN];
u8 group_addr_status[4];
} __attribute__((packed));
struct mib_mac {
__le32 max_tx_msdu_lifetime;
__le32 max_rx_lifetime;
__le16 frag_threshold;
__le16 rts_threshold;
__le16 cwmin;
__le16 cwmax;
u8 short_retry_time;
u8 long_retry_time;
u8 scan_type; /* active or passive */
u8 scan_channel;
__le16 probe_delay; /* delay before ProbeReq in active scan, RO */
__le16 min_channel_time;
__le16 max_channel_time;
__le16 listen_interval;
u8 desired_ssid[32];
u8 desired_bssid[ETH_ALEN];
u8 desired_bsstype; /* ad-hoc or infrastructure */
u8 reserved2;
} __attribute__((packed));
struct mib_mac_mgmt {
__le16 beacon_period;
__le16 CFP_max_duration;
__le16 medium_occupancy_limit;
__le16 station_id; /* assoc id */
__le16 ATIM_window;
u8 CFP_mode;
u8 privacy_option_implemented;
u8 DTIM_period;
u8 CFP_period;
u8 current_bssid[ETH_ALEN];
u8 current_essid[32];
u8 current_bss_type;
u8 power_mgmt_mode;
/* rfmd and 505 */
u8 ibss_change;
u8 res;
u8 multi_domain_capability_implemented;
u8 multi_domain_capability_enabled;
u8 country_string[3];
u8 reserved[3];
} __attribute__((packed));
struct mib_mac_wep {
u8 privacy_invoked; /* 0 disable encr., 1 enable encr */
u8 wep_default_key_id;
u8 wep_key_mapping_len;
u8 exclude_unencrypted;
__le32 wep_icv_error_count;
__le32 wep_excluded_count;
u8 wep_default_keyvalue[WEP_KEYS][WEP_KEY_LEN];
u8 encryption_level; /* 1 for 40bit, 2 for 104bit encryption */
} __attribute__((packed));
struct mib_phy {
__le32 ed_threshold;
__le16 slot_time;
__le16 sifs_time;
__le16 preamble_length;
__le16 plcp_header_length;
__le16 mpdu_max_length;
__le16 cca_mode_supported;
u8 operation_rate_set[4];
u8 channel_id;
u8 current_cca_mode;
u8 phy_type;
u8 current_reg_domain;
} __attribute__((packed));
struct mib_fw_version {
u8 major;
u8 minor;
u8 patch;
u8 build;
} __attribute__((packed));
struct mib_mdomain {
u8 tx_powerlevel[14];
u8 channel_list[14]; /* 0 for invalid channels */
} __attribute__((packed));
struct at76_fw_header {
__le32 crc; /* CRC32 of the whole image */
__le32 board_type; /* firmware compatibility code */
u8 build; /* firmware build number */
u8 patch; /* firmware patch level */
u8 minor; /* firmware minor version */
u8 major; /* firmware major version */
__le32 str_offset; /* offset of the copyright string */
__le32 int_fw_offset; /* internal firmware image offset */
__le32 int_fw_len; /* internal firmware image length */
__le32 ext_fw_offset; /* external firmware image offset */
__le32 ext_fw_len; /* external firmware image length */
} __attribute__((packed));
enum mac_state {
MAC_INIT,
MAC_SCANNING,
MAC_AUTH,
MAC_ASSOC,
MAC_JOINING,
MAC_CONNECTED,
MAC_OWN_IBSS
};
/* a description of a regulatory domain and the allowed channels */
struct reg_domain {
u16 code;
char const *name;
u32 channel_map; /* if bit N is set, channel (N+1) is allowed */
};
/* how long do we keep a (I)BSS in the bss_list in jiffies
this should be long enough for the user to retrieve the table
(by iwlist ?) after the device started, because all entries from
other channels than the one the device locks on get removed, too */
#define BSS_LIST_TIMEOUT (120 * HZ)
/* struct to store BSS info found during scan */
#define BSS_LIST_MAX_RATE_LEN 32 /* 32 rates should be enough ... */
struct bss_info {
struct list_head list;
u8 bssid[ETH_ALEN]; /* bssid */
u8 ssid[IW_ESSID_MAX_SIZE]; /* essid */
u8 ssid_len; /* length of ssid above */
u8 channel;
u16 capa; /* BSS capabilities */
u16 beacon_interval; /* beacon interval, Kus (1024 microseconds) */
u8 rates[BSS_LIST_MAX_RATE_LEN]; /* supported rates in units of
500 kbps, ORed with 0x80 for
basic rates */
u8 rates_len;
/* quality of received beacon */
u8 rssi;
u8 link_qual;
u8 noise_level;
unsigned long last_rx; /* time (jiffies) of last beacon received */
};
/* a rx data buffer to collect rx fragments */
struct rx_data_buf {
u8 sender[ETH_ALEN]; /* sender address */
u16 seqnr; /* sequence number */
u16 fragnr; /* last fragment received */
unsigned long last_rx; /* jiffies of last rx */
struct sk_buff *skb; /* == NULL if entry is free */
};
#define NR_RX_DATA_BUF 8
/* Data for one loaded firmware file */
struct fwentry {
const char *const fwname;
const struct firmware *fw;
int extfw_size;
int intfw_size;
/* pointer to loaded firmware, no need to free */
u8 *extfw; /* external firmware, extfw_size bytes long */
u8 *intfw; /* internal firmware, intfw_size bytes long */
enum board_type board_type; /* board type */
struct mib_fw_version fw_version;
int loaded; /* Loaded and parsed successfully */
};
struct at76_priv {
struct usb_device *udev; /* USB device pointer */
struct net_device *netdev; /* net device pointer */
struct net_device_stats stats; /* net device stats */
struct iw_statistics wstats; /* wireless stats */
struct sk_buff *rx_skb; /* skbuff for receiving data */
void *bulk_out_buffer; /* buffer for sending data */
struct urb *tx_urb; /* URB for sending data */
struct urb *rx_urb; /* URB for receiving data */
unsigned int tx_pipe; /* bulk out pipe */
unsigned int rx_pipe; /* bulk in pipe */
struct mutex mtx; /* locks this structure */
/* work queues */
struct work_struct work_assoc_done;
struct work_struct work_join;
struct work_struct work_new_bss;
struct work_struct work_start_scan;
struct work_struct work_set_promisc;
struct work_struct work_submit_rx;
struct delayed_work dwork_restart;
struct delayed_work dwork_get_scan;
struct delayed_work dwork_beacon;
struct delayed_work dwork_auth;
struct delayed_work dwork_assoc;
struct tasklet_struct rx_tasklet;
/* the WEP stuff */
int wep_enabled; /* 1 if WEP is enabled */
int wep_key_id; /* key id to be used */
u8 wep_keys[WEP_KEYS][WEP_KEY_LEN]; /* the four WEP keys,
5 or 13 bytes are used */
u8 wep_keys_len[WEP_KEYS]; /* the length of the above keys */
int channel;
int iw_mode;
u8 bssid[ETH_ALEN];
u8 essid[IW_ESSID_MAX_SIZE];
int essid_size;
int radio_on;
int promisc;
int preamble_type; /* 0 - long, 1 - short, 2 - auto */
int auth_mode; /* authentication type: 0 open, 1 shared key */
int txrate; /* 0,1,2,3 = 1,2,5.5,11 Mbps, 4 is auto */
int frag_threshold; /* threshold for fragmentation of tx packets */
int rts_threshold; /* threshold for RTS mechanism */
int short_retry_limit;
int scan_min_time; /* scan min channel time */
int scan_max_time; /* scan max channel time */
int scan_mode; /* SCAN_TYPE_ACTIVE, SCAN_TYPE_PASSIVE */
int scan_need_any; /* if set, need to scan for any ESSID */
/* the list we got from scanning */
spinlock_t bss_list_spinlock; /* protects bss_list operations */
struct list_head bss_list; /* list of BSS we got beacons from */
struct timer_list bss_list_timer; /* timer to purge old entries
from bss_list */
struct bss_info *curr_bss; /* current BSS */
u16 assoc_id; /* current association ID, if associated */
u8 wanted_bssid[ETH_ALEN];
int wanted_bssid_valid; /* != 0 if wanted_bssid is to be used */
/* some data for infrastructure mode only */
spinlock_t mgmt_spinlock; /* this spinlock protects access to
next_mgmt_bulk */
struct at76_tx_buffer *next_mgmt_bulk; /* pending management msg to
send via bulk out */
enum mac_state mac_state;
enum {
SCAN_IDLE,
SCAN_IN_PROGRESS,
SCAN_COMPLETED
} scan_state;
time_t last_scan;
int retries; /* remaining retries in case of timeout when
* sending AuthReq or AssocReq */
u8 pm_mode; /* power management mode */
u32 pm_period; /* power management period in microseconds */
struct reg_domain const *domain; /* reg domain description */
/* iwspy support */
spinlock_t spy_spinlock;
struct iw_spy_data spy_data;
struct iw_public_data wireless_data;
/* These fields contain HW config provided by the device (not all of
* these fields are used by all board types) */
u8 mac_addr[ETH_ALEN];
u8 regulatory_domain;
struct at76_card_config card_config;
/* store rx fragments until complete */
struct rx_data_buf rx_data[NR_RX_DATA_BUF];
enum board_type board_type;
struct mib_fw_version fw_version;
unsigned int device_unplugged:1;
unsigned int netdev_registered:1;
struct set_mib_buffer mib_buf; /* global buffer for set_mib calls */
/* beacon counting */
int beacon_period; /* period of mgmt beacons, Kus */
int beacons_received;
unsigned long beacons_last_qual; /* time we restarted counting
beacons */
};
struct at76_rx_radiotap {
struct ieee80211_radiotap_header rt_hdr;
__le64 rt_tsft;
u8 rt_flags;
u8 rt_rate;
s8 rt_signal;
s8 rt_noise;
};
#define AT76_RX_RADIOTAP_PRESENT \
((1 << IEEE80211_RADIOTAP_TSFT) | \
(1 << IEEE80211_RADIOTAP_FLAGS) | \
(1 << IEEE80211_RADIOTAP_RATE) | \
(1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \
(1 << IEEE80211_RADIOTAP_DB_ANTNOISE))
#define BEACON_MAX_DATA_LENGTH 1500
/* the maximum size of an AssocReq packet */
#define ASSOCREQ_MAX_SIZE \
(AT76_TX_HDRLEN + sizeof(struct ieee80211_assoc_request) + \
1 + 1 + IW_ESSID_MAX_SIZE + 1 + 1 + 4)
/* for shared secret auth, add the challenge text size */
#define AUTH_FRAME_SIZE (AT76_TX_HDRLEN + sizeof(struct ieee80211_auth))
/* Maximal number of AuthReq retries */
#define AUTH_RETRIES 3
/* Maximal number of AssocReq retries */
#define ASSOC_RETRIES 3
/* Beacon timeout in managed mode when we are connected */
#define BEACON_TIMEOUT (10 * HZ)
/* Timeout for authentication response */
#define AUTH_TIMEOUT (1 * HZ)
/* Timeout for association response */
#define ASSOC_TIMEOUT (1 * HZ)
/* Polling interval when scan is running */
#define SCAN_POLL_INTERVAL (HZ / 4)
/* Command completion timeout */
#define CMD_COMPLETION_TIMEOUT (5 * HZ)
#define DEF_RTS_THRESHOLD 1536
#define DEF_FRAG_THRESHOLD 1536
#define DEF_SHORT_RETRY_LIMIT 8
#define DEF_CHANNEL 10
#define DEF_SCAN_MIN_TIME 10
#define DEF_SCAN_MAX_TIME 120
#define MAX_RTS_THRESHOLD (MAX_FRAG_THRESHOLD + 1)
/* the max padding size for tx in bytes (see calc_padding) */
#define MAX_PADDING_SIZE 53
#endif /* _AT76_USB_H */

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config ECHO
tristate "Line Echo Canceller support"
default n
---help---
This driver provides line echo cancelling support for mISDN and
Zaptel drivers.
To compile this driver as a module, choose M here. The module
will be called echo.

1
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obj-$(CONFIG_ECHO) += echo.o

10
drivers/staging/echo/TODO Normal file
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TODO:
- checkpatch.pl cleanups
- Lindent
- typedef removals
- handle bit_operations.h (merge in or make part of common code?)
- remove proc interface, only use echo.h interface (proc interface is
racy and not correct.)
Please send patches to Greg Kroah-Hartman <greg@kroah.com> and Cc: Steve
Underwood <steveu@coppice.org> and David Rowe <david@rowetel.com>

253
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/*
* SpanDSP - a series of DSP components for telephony
*
* bit_operations.h - Various bit level operations, such as bit reversal
*
* Written by Steve Underwood <steveu@coppice.org>
*
* Copyright (C) 2006 Steve Underwood
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* $Id: bit_operations.h,v 1.11 2006/11/28 15:37:03 steveu Exp $
*/
/*! \file */
#if !defined(_BIT_OPERATIONS_H_)
#define _BIT_OPERATIONS_H_
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__i386__) || defined(__x86_64__)
/*! \brief Find the bit position of the highest set bit in a word
\param bits The word to be searched
\return The bit number of the highest set bit, or -1 if the word is zero. */
static __inline__ int top_bit(unsigned int bits)
{
int res;
__asm__ (" xorl %[res],%[res];\n"
" decl %[res];\n"
" bsrl %[bits],%[res]\n"
: [res] "=&r" (res)
: [bits] "rm" (bits));
return res;
}
/*- End of function --------------------------------------------------------*/
/*! \brief Find the bit position of the lowest set bit in a word
\param bits The word to be searched
\return The bit number of the lowest set bit, or -1 if the word is zero. */
static __inline__ int bottom_bit(unsigned int bits)
{
int res;
__asm__ (" xorl %[res],%[res];\n"
" decl %[res];\n"
" bsfl %[bits],%[res]\n"
: [res] "=&r" (res)
: [bits] "rm" (bits));
return res;
}
/*- End of function --------------------------------------------------------*/
#else
static __inline__ int top_bit(unsigned int bits)
{
int i;
if (bits == 0)
return -1;
i = 0;
if (bits & 0xFFFF0000)
{
bits &= 0xFFFF0000;
i += 16;
}
if (bits & 0xFF00FF00)
{
bits &= 0xFF00FF00;
i += 8;
}
if (bits & 0xF0F0F0F0)
{
bits &= 0xF0F0F0F0;
i += 4;
}
if (bits & 0xCCCCCCCC)
{
bits &= 0xCCCCCCCC;
i += 2;
}
if (bits & 0xAAAAAAAA)
{
bits &= 0xAAAAAAAA;
i += 1;
}
return i;
}
/*- End of function --------------------------------------------------------*/
static __inline__ int bottom_bit(unsigned int bits)
{
int i;
if (bits == 0)
return -1;
i = 32;
if (bits & 0x0000FFFF)
{
bits &= 0x0000FFFF;
i -= 16;
}
if (bits & 0x00FF00FF)
{
bits &= 0x00FF00FF;
i -= 8;
}
if (bits & 0x0F0F0F0F)
{
bits &= 0x0F0F0F0F;
i -= 4;
}
if (bits & 0x33333333)
{
bits &= 0x33333333;
i -= 2;
}
if (bits & 0x55555555)
{
bits &= 0x55555555;
i -= 1;
}
return i;
}
/*- End of function --------------------------------------------------------*/
#endif
/*! \brief Bit reverse a byte.
\param data The byte to be reversed.
\return The bit reversed version of data. */
static __inline__ uint8_t bit_reverse8(uint8_t x)
{
#if defined(__i386__) || defined(__x86_64__)
/* If multiply is fast */
return ((x*0x0802U & 0x22110U) | (x*0x8020U & 0x88440U))*0x10101U >> 16;
#else
/* If multiply is slow, but we have a barrel shifter */
x = (x >> 4) | (x << 4);
x = ((x & 0xCC) >> 2) | ((x & 0x33) << 2);
return ((x & 0xAA) >> 1) | ((x & 0x55) << 1);
#endif
}
/*- End of function --------------------------------------------------------*/
/*! \brief Bit reverse a 16 bit word.
\param data The word to be reversed.
\return The bit reversed version of data. */
uint16_t bit_reverse16(uint16_t data);
/*! \brief Bit reverse a 32 bit word.
\param data The word to be reversed.
\return The bit reversed version of data. */
uint32_t bit_reverse32(uint32_t data);
/*! \brief Bit reverse each of the four bytes in a 32 bit word.
\param data The word to be reversed.
\return The bit reversed version of data. */
uint32_t bit_reverse_4bytes(uint32_t data);
/*! \brief Find the number of set bits in a 32 bit word.
\param x The word to be searched.
\return The number of set bits. */
int one_bits32(uint32_t x);
/*! \brief Create a mask as wide as the number in a 32 bit word.
\param x The word to be searched.
\return The mask. */
uint32_t make_mask32(uint32_t x);
/*! \brief Create a mask as wide as the number in a 16 bit word.
\param x The word to be searched.
\return The mask. */
uint16_t make_mask16(uint16_t x);
/*! \brief Find the least significant one in a word, and return a word
with just that bit set.
\param x The word to be searched.
\return The word with the single set bit. */
static __inline__ uint32_t least_significant_one32(uint32_t x)
{
return (x & (-(int32_t) x));
}
/*- End of function --------------------------------------------------------*/
/*! \brief Find the most significant one in a word, and return a word
with just that bit set.
\param x The word to be searched.
\return The word with the single set bit. */
static __inline__ uint32_t most_significant_one32(uint32_t x)
{
#if defined(__i386__) || defined(__x86_64__)
return 1 << top_bit(x);
#else
x = make_mask32(x);
return (x ^ (x >> 1));
#endif
}
/*- End of function --------------------------------------------------------*/
/*! \brief Find the parity of a byte.
\param x The byte to be checked.
\return 1 for odd, or 0 for even. */
static __inline__ int parity8(uint8_t x)
{
x = (x ^ (x >> 4)) & 0x0F;
return (0x6996 >> x) & 1;
}
/*- End of function --------------------------------------------------------*/
/*! \brief Find the parity of a 16 bit word.
\param x The word to be checked.
\return 1 for odd, or 0 for even. */
static __inline__ int parity16(uint16_t x)
{
x ^= (x >> 8);
x = (x ^ (x >> 4)) & 0x0F;
return (0x6996 >> x) & 1;
}
/*- End of function --------------------------------------------------------*/
/*! \brief Find the parity of a 32 bit word.
\param x The word to be checked.
\return 1 for odd, or 0 for even. */
static __inline__ int parity32(uint32_t x)
{
x ^= (x >> 16);
x ^= (x >> 8);
x = (x ^ (x >> 4)) & 0x0F;
return (0x6996 >> x) & 1;
}
/*- End of function --------------------------------------------------------*/
#ifdef __cplusplus
}
#endif
#endif
/*- End of file ------------------------------------------------------------*/

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/*
* SpanDSP - a series of DSP components for telephony
*
* echo.c - A line echo canceller. This code is being developed
* against and partially complies with G168.
*
* Written by Steve Underwood <steveu@coppice.org>
* and David Rowe <david_at_rowetel_dot_com>
*
* Copyright (C) 2001, 2003 Steve Underwood, 2007 David Rowe
*
* Based on a bit from here, a bit from there, eye of toad, ear of
* bat, 15 years of failed attempts by David and a few fried brain
* cells.
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* $Id: echo.c,v 1.20 2006/12/01 18:00:48 steveu Exp $
*/
/*! \file */
/* Implementation Notes
David Rowe
April 2007
This code started life as Steve's NLMS algorithm with a tap
rotation algorithm to handle divergence during double talk. I
added a Geigel Double Talk Detector (DTD) [2] and performed some
G168 tests. However I had trouble meeting the G168 requirements,
especially for double talk - there were always cases where my DTD
failed, for example where near end speech was under the 6dB
threshold required for declaring double talk.
So I tried a two path algorithm [1], which has so far given better
results. The original tap rotation/Geigel algorithm is available
in SVN http://svn.rowetel.com/software/oslec/tags/before_16bit.
It's probably possible to make it work if some one wants to put some
serious work into it.
At present no special treatment is provided for tones, which
generally cause NLMS algorithms to diverge. Initial runs of a
subset of the G168 tests for tones (e.g ./echo_test 6) show the
current algorithm is passing OK, which is kind of surprising. The
full set of tests needs to be performed to confirm this result.
One other interesting change is that I have managed to get the NLMS
code to work with 16 bit coefficients, rather than the original 32
bit coefficents. This reduces the MIPs and storage required.
I evaulated the 16 bit port using g168_tests.sh and listening tests
on 4 real-world samples.
I also attempted the implementation of a block based NLMS update
[2] but although this passes g168_tests.sh it didn't converge well
on the real-world samples. I have no idea why, perhaps a scaling
problem. The block based code is also available in SVN
http://svn.rowetel.com/software/oslec/tags/before_16bit. If this
code can be debugged, it will lead to further reduction in MIPS, as
the block update code maps nicely onto DSP instruction sets (it's a
dot product) compared to the current sample-by-sample update.
Steve also has some nice notes on echo cancellers in echo.h
References:
[1] Ochiai, Areseki, and Ogihara, "Echo Canceller with Two Echo
Path Models", IEEE Transactions on communications, COM-25,
No. 6, June
1977.
http://www.rowetel.com/images/echo/dual_path_paper.pdf
[2] The classic, very useful paper that tells you how to
actually build a real world echo canceller:
Messerschmitt, Hedberg, Cole, Haoui, Winship, "Digital Voice
Echo Canceller with a TMS320020,
http://www.rowetel.com/images/echo/spra129.pdf
[3] I have written a series of blog posts on this work, here is
Part 1: http://www.rowetel.com/blog/?p=18
[4] The source code http://svn.rowetel.com/software/oslec/
[5] A nice reference on LMS filters:
http://en.wikipedia.org/wiki/Least_mean_squares_filter
Credits:
Thanks to Steve Underwood, Jean-Marc Valin, and Ramakrishnan
Muthukrishnan for their suggestions and email discussions. Thanks
also to those people who collected echo samples for me such as
Mark, Pawel, and Pavel.
*/
#include <linux/kernel.h> /* We're doing kernel work */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#define malloc(a) kmalloc((a), GFP_KERNEL)
#define free(a) kfree(a)
#include "bit_operations.h"
#include "echo.h"
#define MIN_TX_POWER_FOR_ADAPTION 64
#define MIN_RX_POWER_FOR_ADAPTION 64
#define DTD_HANGOVER 600 /* 600 samples, or 75ms */
#define DC_LOG2BETA 3 /* log2() of DC filter Beta */
/*-----------------------------------------------------------------------*\
FUNCTIONS
\*-----------------------------------------------------------------------*/
/* adapting coeffs using the traditional stochastic descent (N)LMS algorithm */
#ifdef __BLACKFIN_ASM__
static void __inline__ lms_adapt_bg(echo_can_state_t *ec, int clean, int shift)
{
int i, j;
int offset1;
int offset2;
int factor;
int exp;
int16_t *phist;
int n;
if (shift > 0)
factor = clean << shift;
else
factor = clean >> -shift;
/* Update the FIR taps */
offset2 = ec->curr_pos;
offset1 = ec->taps - offset2;
phist = &ec->fir_state_bg.history[offset2];
/* st: and en: help us locate the assembler in echo.s */
//asm("st:");
n = ec->taps;
for (i = 0, j = offset2; i < n; i++, j++)
{
exp = *phist++ * factor;
ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15);
}
//asm("en:");
/* Note the asm for the inner loop above generated by Blackfin gcc
4.1.1 is pretty good (note even parallel instructions used):
R0 = W [P0++] (X);
R0 *= R2;
R0 = R0 + R3 (NS) ||
R1 = W [P1] (X) ||
nop;
R0 >>>= 15;
R0 = R0 + R1;
W [P1++] = R0;
A block based update algorithm would be much faster but the
above can't be improved on much. Every instruction saved in
the loop above is 2 MIPs/ch! The for loop above is where the
Blackfin spends most of it's time - about 17 MIPs/ch measured
with speedtest.c with 256 taps (32ms). Write-back and
Write-through cache gave about the same performance.
*/
}
/*
IDEAS for further optimisation of lms_adapt_bg():
1/ The rounding is quite costly. Could we keep as 32 bit coeffs
then make filter pluck the MS 16-bits of the coeffs when filtering?
However this would lower potential optimisation of filter, as I
think the dual-MAC architecture requires packed 16 bit coeffs.
2/ Block based update would be more efficient, as per comments above,
could use dual MAC architecture.
3/ Look for same sample Blackfin LMS code, see if we can get dual-MAC
packing.
4/ Execute the whole e/c in a block of say 20ms rather than sample
by sample. Processing a few samples every ms is inefficient.
*/
#else
static __inline__ void lms_adapt_bg(echo_can_state_t *ec, int clean, int shift)
{
int i;
int offset1;
int offset2;
int factor;
int exp;
if (shift > 0)
factor = clean << shift;
else
factor = clean >> -shift;
/* Update the FIR taps */
offset2 = ec->curr_pos;
offset1 = ec->taps - offset2;
for (i = ec->taps - 1; i >= offset1; i--)
{
exp = (ec->fir_state_bg.history[i - offset1]*factor);
ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15);
}
for ( ; i >= 0; i--)
{
exp = (ec->fir_state_bg.history[i + offset2]*factor);
ec->fir_taps16[1][i] += (int16_t) ((exp+(1<<14)) >> 15);
}
}
#endif
/*- End of function --------------------------------------------------------*/
echo_can_state_t *echo_can_create(int len, int adaption_mode)
{
echo_can_state_t *ec;
int i;
int j;
ec = kmalloc(sizeof(*ec), GFP_KERNEL);
if (ec == NULL)
return NULL;
memset(ec, 0, sizeof(*ec));
ec->taps = len;
ec->log2taps = top_bit(len);
ec->curr_pos = ec->taps - 1;
for (i = 0; i < 2; i++)
{
if ((ec->fir_taps16[i] = (int16_t *) malloc((ec->taps)*sizeof(int16_t))) == NULL)
{
for (j = 0; j < i; j++)
kfree(ec->fir_taps16[j]);
kfree(ec);
return NULL;
}
memset(ec->fir_taps16[i], 0, (ec->taps)*sizeof(int16_t));
}
fir16_create(&ec->fir_state,
ec->fir_taps16[0],
ec->taps);
fir16_create(&ec->fir_state_bg,
ec->fir_taps16[1],
ec->taps);
for(i=0; i<5; i++) {
ec->xvtx[i] = ec->yvtx[i] = ec->xvrx[i] = ec->yvrx[i] = 0;
}
ec->cng_level = 1000;
echo_can_adaption_mode(ec, adaption_mode);
ec->snapshot = (int16_t*)malloc(ec->taps*sizeof(int16_t));
memset(ec->snapshot, 0, sizeof(int16_t)*ec->taps);
ec->cond_met = 0;
ec->Pstates = 0;
ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0;
ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0;
ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0;
ec->Lbgn = ec->Lbgn_acc = 0;
ec->Lbgn_upper = 200;
ec->Lbgn_upper_acc = ec->Lbgn_upper << 13;
return ec;
}
/*- End of function --------------------------------------------------------*/
void echo_can_free(echo_can_state_t *ec)
{
int i;
fir16_free(&ec->fir_state);
fir16_free(&ec->fir_state_bg);
for (i = 0; i < 2; i++)
kfree(ec->fir_taps16[i]);
kfree(ec->snapshot);
kfree(ec);
}
/*- End of function --------------------------------------------------------*/
void echo_can_adaption_mode(echo_can_state_t *ec, int adaption_mode)
{
ec->adaption_mode = adaption_mode;
}
/*- End of function --------------------------------------------------------*/
void echo_can_flush(echo_can_state_t *ec)
{
int i;
ec->Ltxacc = ec->Lrxacc = ec->Lcleanacc = ec->Lclean_bgacc = 0;
ec->Ltx = ec->Lrx = ec->Lclean = ec->Lclean_bg = 0;
ec->tx_1 = ec->tx_2 = ec->rx_1 = ec->rx_2 = 0;
ec->Lbgn = ec->Lbgn_acc = 0;
ec->Lbgn_upper = 200;
ec->Lbgn_upper_acc = ec->Lbgn_upper << 13;
ec->nonupdate_dwell = 0;
fir16_flush(&ec->fir_state);
fir16_flush(&ec->fir_state_bg);
ec->fir_state.curr_pos = ec->taps - 1;
ec->fir_state_bg.curr_pos = ec->taps - 1;
for (i = 0; i < 2; i++)
memset(ec->fir_taps16[i], 0, ec->taps*sizeof(int16_t));
ec->curr_pos = ec->taps - 1;
ec->Pstates = 0;
}
/*- End of function --------------------------------------------------------*/
void echo_can_snapshot(echo_can_state_t *ec) {
memcpy(ec->snapshot, ec->fir_taps16[0], ec->taps*sizeof(int16_t));
}
/*- End of function --------------------------------------------------------*/
/* Dual Path Echo Canceller ------------------------------------------------*/
int16_t echo_can_update(echo_can_state_t *ec, int16_t tx, int16_t rx)
{
int32_t echo_value;
int clean_bg;
int tmp, tmp1;
/* Input scaling was found be required to prevent problems when tx
starts clipping. Another possible way to handle this would be the
filter coefficent scaling. */
ec->tx = tx; ec->rx = rx;
tx >>=1;
rx >>=1;
/*
Filter DC, 3dB point is 160Hz (I think), note 32 bit precision required
otherwise values do not track down to 0. Zero at DC, Pole at (1-Beta)
only real axis. Some chip sets (like Si labs) don't need
this, but something like a $10 X100P card does. Any DC really slows
down convergence.
Note: removes some low frequency from the signal, this reduces
the speech quality when listening to samples through headphones
but may not be obvious through a telephone handset.
Note that the 3dB frequency in radians is approx Beta, e.g. for
Beta = 2^(-3) = 0.125, 3dB freq is 0.125 rads = 159Hz.
*/
if (ec->adaption_mode & ECHO_CAN_USE_RX_HPF) {
tmp = rx << 15;
#if 1
/* Make sure the gain of the HPF is 1.0. This can still saturate a little under
impulse conditions, and it might roll to 32768 and need clipping on sustained peak
level signals. However, the scale of such clipping is small, and the error due to
any saturation should not markedly affect the downstream processing. */
tmp -= (tmp >> 4);
#endif
ec->rx_1 += -(ec->rx_1>>DC_LOG2BETA) + tmp - ec->rx_2;
/* hard limit filter to prevent clipping. Note that at this stage
rx should be limited to +/- 16383 due to right shift above */
tmp1 = ec->rx_1 >> 15;
if (tmp1 > 16383) tmp1 = 16383;
if (tmp1 < -16383) tmp1 = -16383;
rx = tmp1;
ec->rx_2 = tmp;
}
/* Block average of power in the filter states. Used for
adaption power calculation. */
{
int new, old;
/* efficient "out with the old and in with the new" algorithm so
we don't have to recalculate over the whole block of
samples. */
new = (int)tx * (int)tx;
old = (int)ec->fir_state.history[ec->fir_state.curr_pos] *
(int)ec->fir_state.history[ec->fir_state.curr_pos];
ec->Pstates += ((new - old) + (1<<ec->log2taps)) >> ec->log2taps;
if (ec->Pstates < 0) ec->Pstates = 0;
}
/* Calculate short term average levels using simple single pole IIRs */
ec->Ltxacc += abs(tx) - ec->Ltx;
ec->Ltx = (ec->Ltxacc + (1<<4)) >> 5;
ec->Lrxacc += abs(rx) - ec->Lrx;
ec->Lrx = (ec->Lrxacc + (1<<4)) >> 5;
/* Foreground filter ---------------------------------------------------*/
ec->fir_state.coeffs = ec->fir_taps16[0];
echo_value = fir16(&ec->fir_state, tx);
ec->clean = rx - echo_value;
ec->Lcleanacc += abs(ec->clean) - ec->Lclean;
ec->Lclean = (ec->Lcleanacc + (1<<4)) >> 5;
/* Background filter ---------------------------------------------------*/
echo_value = fir16(&ec->fir_state_bg, tx);
clean_bg = rx - echo_value;
ec->Lclean_bgacc += abs(clean_bg) - ec->Lclean_bg;
ec->Lclean_bg = (ec->Lclean_bgacc + (1<<4)) >> 5;
/* Background Filter adaption -----------------------------------------*/
/* Almost always adap bg filter, just simple DT and energy
detection to minimise adaption in cases of strong double talk.
However this is not critical for the dual path algorithm.
*/
ec->factor = 0;
ec->shift = 0;
if ((ec->nonupdate_dwell == 0)) {
int P, logP, shift;
/* Determine:
f = Beta * clean_bg_rx/P ------ (1)
where P is the total power in the filter states.
The Boffins have shown that if we obey (1) we converge
quickly and avoid instability.
The correct factor f must be in Q30, as this is the fixed
point format required by the lms_adapt_bg() function,
therefore the scaled version of (1) is:
(2^30) * f = (2^30) * Beta * clean_bg_rx/P
factor = (2^30) * Beta * clean_bg_rx/P ----- (2)
We have chosen Beta = 0.25 by experiment, so:
factor = (2^30) * (2^-2) * clean_bg_rx/P
(30 - 2 - log2(P))
factor = clean_bg_rx 2 ----- (3)
To avoid a divide we approximate log2(P) as top_bit(P),
which returns the position of the highest non-zero bit in
P. This approximation introduces an error as large as a
factor of 2, but the algorithm seems to handle it OK.
Come to think of it a divide may not be a big deal on a
modern DSP, so its probably worth checking out the cycles
for a divide versus a top_bit() implementation.
*/
P = MIN_TX_POWER_FOR_ADAPTION + ec->Pstates;
logP = top_bit(P) + ec->log2taps;
shift = 30 - 2 - logP;
ec->shift = shift;
lms_adapt_bg(ec, clean_bg, shift);
}
/* very simple DTD to make sure we dont try and adapt with strong
near end speech */
ec->adapt = 0;
if ((ec->Lrx > MIN_RX_POWER_FOR_ADAPTION) && (ec->Lrx > ec->Ltx))
ec->nonupdate_dwell = DTD_HANGOVER;
if (ec->nonupdate_dwell)
ec->nonupdate_dwell--;
/* Transfer logic ------------------------------------------------------*/
/* These conditions are from the dual path paper [1], I messed with
them a bit to improve performance. */
if ((ec->adaption_mode & ECHO_CAN_USE_ADAPTION) &&
(ec->nonupdate_dwell == 0) &&
(8*ec->Lclean_bg < 7*ec->Lclean) /* (ec->Lclean_bg < 0.875*ec->Lclean) */ &&
(8*ec->Lclean_bg < ec->Ltx) /* (ec->Lclean_bg < 0.125*ec->Ltx) */ )
{
if (ec->cond_met == 6) {
/* BG filter has had better results for 6 consecutive samples */
ec->adapt = 1;
memcpy(ec->fir_taps16[0], ec->fir_taps16[1], ec->taps*sizeof(int16_t));
}
else
ec->cond_met++;
}
else
ec->cond_met = 0;
/* Non-Linear Processing ---------------------------------------------------*/
ec->clean_nlp = ec->clean;
if (ec->adaption_mode & ECHO_CAN_USE_NLP)
{
/* Non-linear processor - a fancy way to say "zap small signals, to avoid
residual echo due to (uLaw/ALaw) non-linearity in the channel.". */
if ((16*ec->Lclean < ec->Ltx))
{
/* Our e/c has improved echo by at least 24 dB (each factor of 2 is 6dB,
so 2*2*2*2=16 is the same as 6+6+6+6=24dB) */
if (ec->adaption_mode & ECHO_CAN_USE_CNG)
{
ec->cng_level = ec->Lbgn;
/* Very elementary comfort noise generation. Just random
numbers rolled off very vaguely Hoth-like. DR: This
noise doesn't sound quite right to me - I suspect there
are some overlfow issues in the filtering as it's too
"crackly". TODO: debug this, maybe just play noise at
high level or look at spectrum.
*/
ec->cng_rndnum = 1664525U*ec->cng_rndnum + 1013904223U;
ec->cng_filter = ((ec->cng_rndnum & 0xFFFF) - 32768 + 5*ec->cng_filter) >> 3;
ec->clean_nlp = (ec->cng_filter*ec->cng_level*8) >> 14;
}
else if (ec->adaption_mode & ECHO_CAN_USE_CLIP)
{
/* This sounds much better than CNG */
if (ec->clean_nlp > ec->Lbgn)
ec->clean_nlp = ec->Lbgn;
if (ec->clean_nlp < -ec->Lbgn)
ec->clean_nlp = -ec->Lbgn;
}
else
{
/* just mute the residual, doesn't sound very good, used mainly
in G168 tests */
ec->clean_nlp = 0;
}
}
else {
/* Background noise estimator. I tried a few algorithms
here without much luck. This very simple one seems to
work best, we just average the level using a slow (1 sec
time const) filter if the current level is less than a
(experimentally derived) constant. This means we dont
include high level signals like near end speech. When
combined with CNG or especially CLIP seems to work OK.
*/
if (ec->Lclean < 40) {
ec->Lbgn_acc += abs(ec->clean) - ec->Lbgn;
ec->Lbgn = (ec->Lbgn_acc + (1<<11)) >> 12;
}
}
}
/* Roll around the taps buffer */
if (ec->curr_pos <= 0)
ec->curr_pos = ec->taps;
ec->curr_pos--;
if (ec->adaption_mode & ECHO_CAN_DISABLE)
ec->clean_nlp = rx;
/* Output scaled back up again to match input scaling */
return (int16_t) ec->clean_nlp << 1;
}
/*- End of function --------------------------------------------------------*/
/* This function is seperated from the echo canceller is it is usually called
as part of the tx process. See rx HP (DC blocking) filter above, it's
the same design.
Some soft phones send speech signals with a lot of low frequency
energy, e.g. down to 20Hz. This can make the hybrid non-linear
which causes the echo canceller to fall over. This filter can help
by removing any low frequency before it gets to the tx port of the
hybrid.
It can also help by removing and DC in the tx signal. DC is bad
for LMS algorithms.
This is one of the classic DC removal filters, adjusted to provide sufficient
bass rolloff to meet the above requirement to protect hybrids from things that
upset them. The difference between successive samples produces a lousy HPF, and
then a suitably placed pole flattens things out. The final result is a nicely
rolled off bass end. The filtering is implemented with extended fractional
precision, which noise shapes things, giving very clean DC removal.
*/
int16_t echo_can_hpf_tx(echo_can_state_t *ec, int16_t tx) {
int tmp, tmp1;
if (ec->adaption_mode & ECHO_CAN_USE_TX_HPF) {
tmp = tx << 15;
#if 1
/* Make sure the gain of the HPF is 1.0. The first can still saturate a little under
impulse conditions, and it might roll to 32768 and need clipping on sustained peak
level signals. However, the scale of such clipping is small, and the error due to
any saturation should not markedly affect the downstream processing. */
tmp -= (tmp >> 4);
#endif
ec->tx_1 += -(ec->tx_1>>DC_LOG2BETA) + tmp - ec->tx_2;
tmp1 = ec->tx_1 >> 15;
if (tmp1 > 32767) tmp1 = 32767;
if (tmp1 < -32767) tmp1 = -32767;
tx = tmp1;
ec->tx_2 = tmp;
}
return tx;
}

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/*
* SpanDSP - a series of DSP components for telephony
*
* echo.c - A line echo canceller. This code is being developed
* against and partially complies with G168.
*
* Written by Steve Underwood <steveu@coppice.org>
* and David Rowe <david_at_rowetel_dot_com>
*
* Copyright (C) 2001 Steve Underwood and 2007 David Rowe
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* $Id: echo.h,v 1.9 2006/10/24 13:45:28 steveu Exp $
*/
#ifndef __ECHO_H
#define __ECHO_H
/*! \page echo_can_page Line echo cancellation for voice
\section echo_can_page_sec_1 What does it do?
This module aims to provide G.168-2002 compliant echo cancellation, to remove
electrical echoes (e.g. from 2-4 wire hybrids) from voice calls.
\section echo_can_page_sec_2 How does it work?
The heart of the echo cancellor is FIR filter. This is adapted to match the
echo impulse response of the telephone line. It must be long enough to
adequately cover the duration of that impulse response. The signal transmitted
to the telephone line is passed through the FIR filter. Once the FIR is
properly adapted, the resulting output is an estimate of the echo signal
received from the line. This is subtracted from the received signal. The result
is an estimate of the signal which originated at the far end of the line, free
from echos of our own transmitted signal.
The least mean squares (LMS) algorithm is attributed to Widrow and Hoff, and
was introduced in 1960. It is the commonest form of filter adaption used in
things like modem line equalisers and line echo cancellers. There it works very
well. However, it only works well for signals of constant amplitude. It works
very poorly for things like speech echo cancellation, where the signal level
varies widely. This is quite easy to fix. If the signal level is normalised -
similar to applying AGC - LMS can work as well for a signal of varying
amplitude as it does for a modem signal. This normalised least mean squares
(NLMS) algorithm is the commonest one used for speech echo cancellation. Many
other algorithms exist - e.g. RLS (essentially the same as Kalman filtering),
FAP, etc. Some perform significantly better than NLMS. However, factors such
as computational complexity and patents favour the use of NLMS.
A simple refinement to NLMS can improve its performance with speech. NLMS tends
to adapt best to the strongest parts of a signal. If the signal is white noise,
the NLMS algorithm works very well. However, speech has more low frequency than
high frequency content. Pre-whitening (i.e. filtering the signal to flatten its
spectrum) the echo signal improves the adapt rate for speech, and ensures the
final residual signal is not heavily biased towards high frequencies. A very
low complexity filter is adequate for this, so pre-whitening adds little to the
compute requirements of the echo canceller.
An FIR filter adapted using pre-whitened NLMS performs well, provided certain
conditions are met:
- The transmitted signal has poor self-correlation.
- There is no signal being generated within the environment being
cancelled.
The difficulty is that neither of these can be guaranteed.
If the adaption is performed while transmitting noise (or something fairly
noise like, such as voice) the adaption works very well. If the adaption is
performed while transmitting something highly correlative (typically narrow
band energy such as signalling tones or DTMF), the adaption can go seriously
wrong. The reason is there is only one solution for the adaption on a near
random signal - the impulse response of the line. For a repetitive signal,
there are any number of solutions which converge the adaption, and nothing
guides the adaption to choose the generalised one. Allowing an untrained
canceller to converge on this kind of narrowband energy probably a good thing,
since at least it cancels the tones. Allowing a well converged canceller to
continue converging on such energy is just a way to ruin its generalised
adaption. A narrowband detector is needed, so adapation can be suspended at
appropriate times.
The adaption process is based on trying to eliminate the received signal. When
there is any signal from within the environment being cancelled it may upset
the adaption process. Similarly, if the signal we are transmitting is small,
noise may dominate and disturb the adaption process. If we can ensure that the
adaption is only performed when we are transmitting a significant signal level,
and the environment is not, things will be OK. Clearly, it is easy to tell when
we are sending a significant signal. Telling, if the environment is generating
a significant signal, and doing it with sufficient speed that the adaption will
not have diverged too much more we stop it, is a little harder.
The key problem in detecting when the environment is sourcing significant
energy is that we must do this very quickly. Given a reasonably long sample of
the received signal, there are a number of strategies which may be used to
assess whether that signal contains a strong far end component. However, by the
time that assessment is complete the far end signal will have already caused
major mis-convergence in the adaption process. An assessment algorithm is
needed which produces a fairly accurate result from a very short burst of far
end energy.
\section echo_can_page_sec_3 How do I use it?
The echo cancellor processes both the transmit and receive streams sample by
sample. The processing function is not declared inline. Unfortunately,
cancellation requires many operations per sample, so the call overhead is only
a minor burden.
*/
#include "fir.h"
/* Mask bits for the adaption mode */
#define ECHO_CAN_USE_ADAPTION 0x01
#define ECHO_CAN_USE_NLP 0x02
#define ECHO_CAN_USE_CNG 0x04
#define ECHO_CAN_USE_CLIP 0x08
#define ECHO_CAN_USE_TX_HPF 0x10
#define ECHO_CAN_USE_RX_HPF 0x20
#define ECHO_CAN_DISABLE 0x40
/*!
G.168 echo canceller descriptor. This defines the working state for a line
echo canceller.
*/
typedef struct
{
int16_t tx,rx;
int16_t clean;
int16_t clean_nlp;
int nonupdate_dwell;
int curr_pos;
int taps;
int log2taps;
int adaption_mode;
int cond_met;
int32_t Pstates;
int16_t adapt;
int32_t factor;
int16_t shift;
/* Average levels and averaging filter states */
int Ltxacc, Lrxacc, Lcleanacc, Lclean_bgacc;
int Ltx, Lrx;
int Lclean;
int Lclean_bg;
int Lbgn, Lbgn_acc, Lbgn_upper, Lbgn_upper_acc;
/* foreground and background filter states */
fir16_state_t fir_state;
fir16_state_t fir_state_bg;
int16_t *fir_taps16[2];
/* DC blocking filter states */
int tx_1, tx_2, rx_1, rx_2;
/* optional High Pass Filter states */
int32_t xvtx[5], yvtx[5];
int32_t xvrx[5], yvrx[5];
/* Parameters for the optional Hoth noise generator */
int cng_level;
int cng_rndnum;
int cng_filter;
/* snapshot sample of coeffs used for development */
int16_t *snapshot;
} echo_can_state_t;
/*! Create a voice echo canceller context.
\param len The length of the canceller, in samples.
\return The new canceller context, or NULL if the canceller could not be created.
*/
echo_can_state_t *echo_can_create(int len, int adaption_mode);
/*! Free a voice echo canceller context.
\param ec The echo canceller context.
*/
void echo_can_free(echo_can_state_t *ec);
/*! Flush (reinitialise) a voice echo canceller context.
\param ec The echo canceller context.
*/
void echo_can_flush(echo_can_state_t *ec);
/*! Set the adaption mode of a voice echo canceller context.
\param ec The echo canceller context.
\param adapt The mode.
*/
void echo_can_adaption_mode(echo_can_state_t *ec, int adaption_mode);
void echo_can_snapshot(echo_can_state_t *ec);
/*! Process a sample through a voice echo canceller.
\param ec The echo canceller context.
\param tx The transmitted audio sample.
\param rx The received audio sample.
\return The clean (echo cancelled) received sample.
*/
int16_t echo_can_update(echo_can_state_t *ec, int16_t tx, int16_t rx);
/*! Process to high pass filter the tx signal.
\param ec The echo canceller context.
\param tx The transmitted auio sample.
\return The HP filtered transmit sample, send this to your D/A.
*/
int16_t echo_can_hpf_tx(echo_can_state_t *ec, int16_t tx);
#endif /* __ECHO_H */

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/*
* SpanDSP - a series of DSP components for telephony
*
* fir.h - General telephony FIR routines
*
* Written by Steve Underwood <steveu@coppice.org>
*
* Copyright (C) 2002 Steve Underwood
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2, as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* $Id: fir.h,v 1.8 2006/10/24 13:45:28 steveu Exp $
*/
/*! \page fir_page FIR filtering
\section fir_page_sec_1 What does it do?
???.
\section fir_page_sec_2 How does it work?
???.
*/
#if !defined(_FIR_H_)
#define _FIR_H_
/*
Blackfin NOTES & IDEAS:
A simple dot product function is used to implement the filter. This performs
just one MAC/cycle which is inefficient but was easy to implement as a first
pass. The current Blackfin code also uses an unrolled form of the filter
history to avoid 0 length hardware loop issues. This is wasteful of
memory.
Ideas for improvement:
1/ Rewrite filter for dual MAC inner loop. The issue here is handling
history sample offsets that are 16 bit aligned - the dual MAC needs
32 bit aligmnent. There are some good examples in libbfdsp.
2/ Use the hardware circular buffer facility tohalve memory usage.
3/ Consider using internal memory.
Using less memory might also improve speed as cache misses will be
reduced. A drop in MIPs and memory approaching 50% should be
possible.
The foreground and background filters currenlty use a total of
about 10 MIPs/ch as measured with speedtest.c on a 256 TAP echo
can.
*/
#if defined(USE_MMX) || defined(USE_SSE2)
#include "mmx.h"
#endif
/*!
16 bit integer FIR descriptor. This defines the working state for a single
instance of an FIR filter using 16 bit integer coefficients.
*/
typedef struct
{
int taps;
int curr_pos;
const int16_t *coeffs;
int16_t *history;
} fir16_state_t;
/*!
32 bit integer FIR descriptor. This defines the working state for a single
instance of an FIR filter using 32 bit integer coefficients, and filtering
16 bit integer data.
*/
typedef struct
{
int taps;
int curr_pos;
const int32_t *coeffs;
int16_t *history;
} fir32_state_t;
/*!
Floating point FIR descriptor. This defines the working state for a single
instance of an FIR filter using floating point coefficients and data.
*/
typedef struct
{
int taps;
int curr_pos;
const float *coeffs;
float *history;
} fir_float_state_t;
#ifdef __cplusplus
extern "C" {
#endif
static __inline__ const int16_t *fir16_create(fir16_state_t *fir,
const int16_t *coeffs,
int taps)
{
fir->taps = taps;
fir->curr_pos = taps - 1;
fir->coeffs = coeffs;
#if defined(USE_MMX) || defined(USE_SSE2) || defined(__BLACKFIN_ASM__)
if ((fir->history = malloc(2*taps*sizeof(int16_t))))
memset(fir->history, 0, 2*taps*sizeof(int16_t));
#else
if ((fir->history = (int16_t *) malloc(taps*sizeof(int16_t))))
memset(fir->history, 0, taps*sizeof(int16_t));
#endif
return fir->history;
}
/*- End of function --------------------------------------------------------*/
static __inline__ void fir16_flush(fir16_state_t *fir)
{
#if defined(USE_MMX) || defined(USE_SSE2) || defined(__BLACKFIN_ASM__)
memset(fir->history, 0, 2*fir->taps*sizeof(int16_t));
#else
memset(fir->history, 0, fir->taps*sizeof(int16_t));
#endif
}
/*- End of function --------------------------------------------------------*/
static __inline__ void fir16_free(fir16_state_t *fir)
{
free(fir->history);
}
/*- End of function --------------------------------------------------------*/
#ifdef __BLACKFIN_ASM__
static inline int32_t dot_asm(short *x, short *y, int len)
{
int dot;
len--;
__asm__
(
"I0 = %1;\n\t"
"I1 = %2;\n\t"
"A0 = 0;\n\t"
"R0.L = W[I0++] || R1.L = W[I1++];\n\t"
"LOOP dot%= LC0 = %3;\n\t"
"LOOP_BEGIN dot%=;\n\t"
"A0 += R0.L * R1.L (IS) || R0.L = W[I0++] || R1.L = W[I1++];\n\t"
"LOOP_END dot%=;\n\t"
"A0 += R0.L*R1.L (IS);\n\t"
"R0 = A0;\n\t"
"%0 = R0;\n\t"
: "=&d" (dot)
: "a" (x), "a" (y), "a" (len)
: "I0", "I1", "A1", "A0", "R0", "R1"
);
return dot;
}
#endif
/*- End of function --------------------------------------------------------*/
static __inline__ int16_t fir16(fir16_state_t *fir, int16_t sample)
{
int32_t y;
#if defined(USE_MMX)
int i;
mmx_t *mmx_coeffs;
mmx_t *mmx_hist;
fir->history[fir->curr_pos] = sample;
fir->history[fir->curr_pos + fir->taps] = sample;
mmx_coeffs = (mmx_t *) fir->coeffs;
mmx_hist = (mmx_t *) &fir->history[fir->curr_pos];
i = fir->taps;
pxor_r2r(mm4, mm4);
/* 8 samples per iteration, so the filter must be a multiple of 8 long. */
while (i > 0)
{
movq_m2r(mmx_coeffs[0], mm0);
movq_m2r(mmx_coeffs[1], mm2);
movq_m2r(mmx_hist[0], mm1);
movq_m2r(mmx_hist[1], mm3);
mmx_coeffs += 2;
mmx_hist += 2;
pmaddwd_r2r(mm1, mm0);
pmaddwd_r2r(mm3, mm2);
paddd_r2r(mm0, mm4);
paddd_r2r(mm2, mm4);
i -= 8;
}
movq_r2r(mm4, mm0);
psrlq_i2r(32, mm0);
paddd_r2r(mm0, mm4);
movd_r2m(mm4, y);
emms();
#elif defined(USE_SSE2)
int i;
xmm_t *xmm_coeffs;
xmm_t *xmm_hist;
fir->history[fir->curr_pos] = sample;
fir->history[fir->curr_pos + fir->taps] = sample;
xmm_coeffs = (xmm_t *) fir->coeffs;
xmm_hist = (xmm_t *) &fir->history[fir->curr_pos];
i = fir->taps;
pxor_r2r(xmm4, xmm4);
/* 16 samples per iteration, so the filter must be a multiple of 16 long. */
while (i > 0)
{
movdqu_m2r(xmm_coeffs[0], xmm0);
movdqu_m2r(xmm_coeffs[1], xmm2);
movdqu_m2r(xmm_hist[0], xmm1);
movdqu_m2r(xmm_hist[1], xmm3);
xmm_coeffs += 2;
xmm_hist += 2;
pmaddwd_r2r(xmm1, xmm0);
pmaddwd_r2r(xmm3, xmm2);
paddd_r2r(xmm0, xmm4);
paddd_r2r(xmm2, xmm4);
i -= 16;
}
movdqa_r2r(xmm4, xmm0);
psrldq_i2r(8, xmm0);
paddd_r2r(xmm0, xmm4);
movdqa_r2r(xmm4, xmm0);
psrldq_i2r(4, xmm0);
paddd_r2r(xmm0, xmm4);
movd_r2m(xmm4, y);
#elif defined(__BLACKFIN_ASM__)
fir->history[fir->curr_pos] = sample;
fir->history[fir->curr_pos + fir->taps] = sample;
y = dot_asm((int16_t*)fir->coeffs, &fir->history[fir->curr_pos], fir->taps);
#else
int i;
int offset1;
int offset2;
fir->history[fir->curr_pos] = sample;
offset2 = fir->curr_pos;
offset1 = fir->taps - offset2;
y = 0;
for (i = fir->taps - 1; i >= offset1; i--)
y += fir->coeffs[i]*fir->history[i - offset1];
for ( ; i >= 0; i--)
y += fir->coeffs[i]*fir->history[i + offset2];
#endif
if (fir->curr_pos <= 0)
fir->curr_pos = fir->taps;
fir->curr_pos--;
return (int16_t) (y >> 15);
}
/*- End of function --------------------------------------------------------*/
static __inline__ const int16_t *fir32_create(fir32_state_t *fir,
const int32_t *coeffs,
int taps)
{
fir->taps = taps;
fir->curr_pos = taps - 1;
fir->coeffs = coeffs;
fir->history = (int16_t *) malloc(taps*sizeof(int16_t));
if (fir->history)
memset(fir->history, '\0', taps*sizeof(int16_t));
return fir->history;
}
/*- End of function --------------------------------------------------------*/
static __inline__ void fir32_flush(fir32_state_t *fir)
{
memset(fir->history, 0, fir->taps*sizeof(int16_t));
}
/*- End of function --------------------------------------------------------*/
static __inline__ void fir32_free(fir32_state_t *fir)
{
free(fir->history);
}
/*- End of function --------------------------------------------------------*/
static __inline__ int16_t fir32(fir32_state_t *fir, int16_t sample)
{
int i;
int32_t y;
int offset1;
int offset2;
fir->history[fir->curr_pos] = sample;
offset2 = fir->curr_pos;
offset1 = fir->taps - offset2;
y = 0;
for (i = fir->taps - 1; i >= offset1; i--)
y += fir->coeffs[i]*fir->history[i - offset1];
for ( ; i >= 0; i--)
y += fir->coeffs[i]*fir->history[i + offset2];
if (fir->curr_pos <= 0)
fir->curr_pos = fir->taps;
fir->curr_pos--;
return (int16_t) (y >> 15);
}
/*- End of function --------------------------------------------------------*/
#ifndef __KERNEL__
static __inline__ const float *fir_float_create(fir_float_state_t *fir,
const float *coeffs,
int taps)
{
fir->taps = taps;
fir->curr_pos = taps - 1;
fir->coeffs = coeffs;
fir->history = (float *) malloc(taps*sizeof(float));
if (fir->history)
memset(fir->history, '\0', taps*sizeof(float));
return fir->history;
}
/*- End of function --------------------------------------------------------*/
static __inline__ void fir_float_free(fir_float_state_t *fir)
{
free(fir->history);
}
/*- End of function --------------------------------------------------------*/
static __inline__ int16_t fir_float(fir_float_state_t *fir, int16_t sample)
{
int i;
float y;
int offset1;
int offset2;
fir->history[fir->curr_pos] = sample;
offset2 = fir->curr_pos;
offset1 = fir->taps - offset2;
y = 0;
for (i = fir->taps - 1; i >= offset1; i--)
y += fir->coeffs[i]*fir->history[i - offset1];
for ( ; i >= 0; i--)
y += fir->coeffs[i]*fir->history[i + offset2];
if (fir->curr_pos <= 0)
fir->curr_pos = fir->taps;
fir->curr_pos--;
return (int16_t) y;
}
/*- End of function --------------------------------------------------------*/
#endif
#ifdef __cplusplus
}
#endif
#endif
/*- End of file ------------------------------------------------------------*/

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/*
* mmx.h
* Copyright (C) 1997-2001 H. Dietz and R. Fisher
*
* This file is part of FFmpeg.
*
* FFmpeg is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* FFmpeg is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with FFmpeg; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef AVCODEC_I386MMX_H
#define AVCODEC_I386MMX_H
/*
* The type of an value that fits in an MMX register (note that long
* long constant values MUST be suffixed by LL and unsigned long long
* values by ULL, lest they be truncated by the compiler)
*/
typedef union {
long long q; /* Quadword (64-bit) value */
unsigned long long uq; /* Unsigned Quadword */
int d[2]; /* 2 Doubleword (32-bit) values */
unsigned int ud[2]; /* 2 Unsigned Doubleword */
short w[4]; /* 4 Word (16-bit) values */
unsigned short uw[4]; /* 4 Unsigned Word */
char b[8]; /* 8 Byte (8-bit) values */
unsigned char ub[8]; /* 8 Unsigned Byte */
float s[2]; /* Single-precision (32-bit) value */
} mmx_t; /* On an 8-byte (64-bit) boundary */
/* SSE registers */
typedef union {
char b[16];
} xmm_t;
#define mmx_i2r(op,imm,reg) \
__asm__ __volatile__ (#op " %0, %%" #reg \
: /* nothing */ \
: "i" (imm) )
#define mmx_m2r(op,mem,reg) \
__asm__ __volatile__ (#op " %0, %%" #reg \
: /* nothing */ \
: "m" (mem))
#define mmx_r2m(op,reg,mem) \
__asm__ __volatile__ (#op " %%" #reg ", %0" \
: "=m" (mem) \
: /* nothing */ )
#define mmx_r2r(op,regs,regd) \
__asm__ __volatile__ (#op " %" #regs ", %" #regd)
#define emms() __asm__ __volatile__ ("emms")
#define movd_m2r(var,reg) mmx_m2r (movd, var, reg)
#define movd_r2m(reg,var) mmx_r2m (movd, reg, var)
#define movd_r2r(regs,regd) mmx_r2r (movd, regs, regd)
#define movq_m2r(var,reg) mmx_m2r (movq, var, reg)
#define movq_r2m(reg,var) mmx_r2m (movq, reg, var)
#define movq_r2r(regs,regd) mmx_r2r (movq, regs, regd)
#define packssdw_m2r(var,reg) mmx_m2r (packssdw, var, reg)
#define packssdw_r2r(regs,regd) mmx_r2r (packssdw, regs, regd)
#define packsswb_m2r(var,reg) mmx_m2r (packsswb, var, reg)
#define packsswb_r2r(regs,regd) mmx_r2r (packsswb, regs, regd)
#define packuswb_m2r(var,reg) mmx_m2r (packuswb, var, reg)
#define packuswb_r2r(regs,regd) mmx_r2r (packuswb, regs, regd)
#define paddb_m2r(var,reg) mmx_m2r (paddb, var, reg)
#define paddb_r2r(regs,regd) mmx_r2r (paddb, regs, regd)
#define paddd_m2r(var,reg) mmx_m2r (paddd, var, reg)
#define paddd_r2r(regs,regd) mmx_r2r (paddd, regs, regd)
#define paddw_m2r(var,reg) mmx_m2r (paddw, var, reg)
#define paddw_r2r(regs,regd) mmx_r2r (paddw, regs, regd)
#define paddsb_m2r(var,reg) mmx_m2r (paddsb, var, reg)
#define paddsb_r2r(regs,regd) mmx_r2r (paddsb, regs, regd)
#define paddsw_m2r(var,reg) mmx_m2r (paddsw, var, reg)
#define paddsw_r2r(regs,regd) mmx_r2r (paddsw, regs, regd)
#define paddusb_m2r(var,reg) mmx_m2r (paddusb, var, reg)
#define paddusb_r2r(regs,regd) mmx_r2r (paddusb, regs, regd)
#define paddusw_m2r(var,reg) mmx_m2r (paddusw, var, reg)
#define paddusw_r2r(regs,regd) mmx_r2r (paddusw, regs, regd)
#define pand_m2r(var,reg) mmx_m2r (pand, var, reg)
#define pand_r2r(regs,regd) mmx_r2r (pand, regs, regd)
#define pandn_m2r(var,reg) mmx_m2r (pandn, var, reg)
#define pandn_r2r(regs,regd) mmx_r2r (pandn, regs, regd)
#define pcmpeqb_m2r(var,reg) mmx_m2r (pcmpeqb, var, reg)
#define pcmpeqb_r2r(regs,regd) mmx_r2r (pcmpeqb, regs, regd)
#define pcmpeqd_m2r(var,reg) mmx_m2r (pcmpeqd, var, reg)
#define pcmpeqd_r2r(regs,regd) mmx_r2r (pcmpeqd, regs, regd)
#define pcmpeqw_m2r(var,reg) mmx_m2r (pcmpeqw, var, reg)
#define pcmpeqw_r2r(regs,regd) mmx_r2r (pcmpeqw, regs, regd)
#define pcmpgtb_m2r(var,reg) mmx_m2r (pcmpgtb, var, reg)
#define pcmpgtb_r2r(regs,regd) mmx_r2r (pcmpgtb, regs, regd)
#define pcmpgtd_m2r(var,reg) mmx_m2r (pcmpgtd, var, reg)
#define pcmpgtd_r2r(regs,regd) mmx_r2r (pcmpgtd, regs, regd)
#define pcmpgtw_m2r(var,reg) mmx_m2r (pcmpgtw, var, reg)
#define pcmpgtw_r2r(regs,regd) mmx_r2r (pcmpgtw, regs, regd)
#define pmaddwd_m2r(var,reg) mmx_m2r (pmaddwd, var, reg)
#define pmaddwd_r2r(regs,regd) mmx_r2r (pmaddwd, regs, regd)
#define pmulhw_m2r(var,reg) mmx_m2r (pmulhw, var, reg)
#define pmulhw_r2r(regs,regd) mmx_r2r (pmulhw, regs, regd)
#define pmullw_m2r(var,reg) mmx_m2r (pmullw, var, reg)
#define pmullw_r2r(regs,regd) mmx_r2r (pmullw, regs, regd)
#define por_m2r(var,reg) mmx_m2r (por, var, reg)
#define por_r2r(regs,regd) mmx_r2r (por, regs, regd)
#define pslld_i2r(imm,reg) mmx_i2r (pslld, imm, reg)
#define pslld_m2r(var,reg) mmx_m2r (pslld, var, reg)
#define pslld_r2r(regs,regd) mmx_r2r (pslld, regs, regd)
#define psllq_i2r(imm,reg) mmx_i2r (psllq, imm, reg)
#define psllq_m2r(var,reg) mmx_m2r (psllq, var, reg)
#define psllq_r2r(regs,regd) mmx_r2r (psllq, regs, regd)
#define psllw_i2r(imm,reg) mmx_i2r (psllw, imm, reg)
#define psllw_m2r(var,reg) mmx_m2r (psllw, var, reg)
#define psllw_r2r(regs,regd) mmx_r2r (psllw, regs, regd)
#define psrad_i2r(imm,reg) mmx_i2r (psrad, imm, reg)
#define psrad_m2r(var,reg) mmx_m2r (psrad, var, reg)
#define psrad_r2r(regs,regd) mmx_r2r (psrad, regs, regd)
#define psraw_i2r(imm,reg) mmx_i2r (psraw, imm, reg)
#define psraw_m2r(var,reg) mmx_m2r (psraw, var, reg)
#define psraw_r2r(regs,regd) mmx_r2r (psraw, regs, regd)
#define psrld_i2r(imm,reg) mmx_i2r (psrld, imm, reg)
#define psrld_m2r(var,reg) mmx_m2r (psrld, var, reg)
#define psrld_r2r(regs,regd) mmx_r2r (psrld, regs, regd)
#define psrlq_i2r(imm,reg) mmx_i2r (psrlq, imm, reg)
#define psrlq_m2r(var,reg) mmx_m2r (psrlq, var, reg)
#define psrlq_r2r(regs,regd) mmx_r2r (psrlq, regs, regd)
#define psrlw_i2r(imm,reg) mmx_i2r (psrlw, imm, reg)
#define psrlw_m2r(var,reg) mmx_m2r (psrlw, var, reg)
#define psrlw_r2r(regs,regd) mmx_r2r (psrlw, regs, regd)
#define psubb_m2r(var,reg) mmx_m2r (psubb, var, reg)
#define psubb_r2r(regs,regd) mmx_r2r (psubb, regs, regd)
#define psubd_m2r(var,reg) mmx_m2r (psubd, var, reg)
#define psubd_r2r(regs,regd) mmx_r2r (psubd, regs, regd)
#define psubw_m2r(var,reg) mmx_m2r (psubw, var, reg)
#define psubw_r2r(regs,regd) mmx_r2r (psubw, regs, regd)
#define psubsb_m2r(var,reg) mmx_m2r (psubsb, var, reg)
#define psubsb_r2r(regs,regd) mmx_r2r (psubsb, regs, regd)
#define psubsw_m2r(var,reg) mmx_m2r (psubsw, var, reg)
#define psubsw_r2r(regs,regd) mmx_r2r (psubsw, regs, regd)
#define psubusb_m2r(var,reg) mmx_m2r (psubusb, var, reg)
#define psubusb_r2r(regs,regd) mmx_r2r (psubusb, regs, regd)
#define psubusw_m2r(var,reg) mmx_m2r (psubusw, var, reg)
#define psubusw_r2r(regs,regd) mmx_r2r (psubusw, regs, regd)
#define punpckhbw_m2r(var,reg) mmx_m2r (punpckhbw, var, reg)
#define punpckhbw_r2r(regs,regd) mmx_r2r (punpckhbw, regs, regd)
#define punpckhdq_m2r(var,reg) mmx_m2r (punpckhdq, var, reg)
#define punpckhdq_r2r(regs,regd) mmx_r2r (punpckhdq, regs, regd)
#define punpckhwd_m2r(var,reg) mmx_m2r (punpckhwd, var, reg)
#define punpckhwd_r2r(regs,regd) mmx_r2r (punpckhwd, regs, regd)
#define punpcklbw_m2r(var,reg) mmx_m2r (punpcklbw, var, reg)
#define punpcklbw_r2r(regs,regd) mmx_r2r (punpcklbw, regs, regd)
#define punpckldq_m2r(var,reg) mmx_m2r (punpckldq, var, reg)
#define punpckldq_r2r(regs,regd) mmx_r2r (punpckldq, regs, regd)
#define punpcklwd_m2r(var,reg) mmx_m2r (punpcklwd, var, reg)
#define punpcklwd_r2r(regs,regd) mmx_r2r (punpcklwd, regs, regd)
#define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg)
#define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd)
/* 3DNOW extensions */
#define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg)
#define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd)
/* AMD MMX extensions - also available in intel SSE */
#define mmx_m2ri(op,mem,reg,imm) \
__asm__ __volatile__ (#op " %1, %0, %%" #reg \
: /* nothing */ \
: "m" (mem), "i" (imm))
#define mmx_r2ri(op,regs,regd,imm) \
__asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
: /* nothing */ \
: "i" (imm) )
#define mmx_fetch(mem,hint) \
__asm__ __volatile__ ("prefetch" #hint " %0" \
: /* nothing */ \
: "m" (mem))
#define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg)
#define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var)
#define pavgb_m2r(var,reg) mmx_m2r (pavgb, var, reg)
#define pavgb_r2r(regs,regd) mmx_r2r (pavgb, regs, regd)
#define pavgw_m2r(var,reg) mmx_m2r (pavgw, var, reg)
#define pavgw_r2r(regs,regd) mmx_r2r (pavgw, regs, regd)
#define pextrw_r2r(mmreg,reg,imm) mmx_r2ri (pextrw, mmreg, reg, imm)
#define pinsrw_r2r(reg,mmreg,imm) mmx_r2ri (pinsrw, reg, mmreg, imm)
#define pmaxsw_m2r(var,reg) mmx_m2r (pmaxsw, var, reg)
#define pmaxsw_r2r(regs,regd) mmx_r2r (pmaxsw, regs, regd)
#define pmaxub_m2r(var,reg) mmx_m2r (pmaxub, var, reg)
#define pmaxub_r2r(regs,regd) mmx_r2r (pmaxub, regs, regd)
#define pminsw_m2r(var,reg) mmx_m2r (pminsw, var, reg)
#define pminsw_r2r(regs,regd) mmx_r2r (pminsw, regs, regd)
#define pminub_m2r(var,reg) mmx_m2r (pminub, var, reg)
#define pminub_r2r(regs,regd) mmx_r2r (pminub, regs, regd)
#define pmovmskb(mmreg,reg) \
__asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg)
#define pmulhuw_m2r(var,reg) mmx_m2r (pmulhuw, var, reg)
#define pmulhuw_r2r(regs,regd) mmx_r2r (pmulhuw, regs, regd)
#define prefetcht0(mem) mmx_fetch (mem, t0)
#define prefetcht1(mem) mmx_fetch (mem, t1)
#define prefetcht2(mem) mmx_fetch (mem, t2)
#define prefetchnta(mem) mmx_fetch (mem, nta)
#define psadbw_m2r(var,reg) mmx_m2r (psadbw, var, reg)
#define psadbw_r2r(regs,regd) mmx_r2r (psadbw, regs, regd)
#define pshufw_m2r(var,reg,imm) mmx_m2ri(pshufw, var, reg, imm)
#define pshufw_r2r(regs,regd,imm) mmx_r2ri(pshufw, regs, regd, imm)
#define sfence() __asm__ __volatile__ ("sfence\n\t")
/* SSE2 */
#define pshufhw_m2r(var,reg,imm) mmx_m2ri(pshufhw, var, reg, imm)
#define pshufhw_r2r(regs,regd,imm) mmx_r2ri(pshufhw, regs, regd, imm)
#define pshuflw_m2r(var,reg,imm) mmx_m2ri(pshuflw, var, reg, imm)
#define pshuflw_r2r(regs,regd,imm) mmx_r2ri(pshuflw, regs, regd, imm)
#define pshufd_r2r(regs,regd,imm) mmx_r2ri(pshufd, regs, regd, imm)
#define movdqa_m2r(var,reg) mmx_m2r (movdqa, var, reg)
#define movdqa_r2m(reg,var) mmx_r2m (movdqa, reg, var)
#define movdqa_r2r(regs,regd) mmx_r2r (movdqa, regs, regd)
#define movdqu_m2r(var,reg) mmx_m2r (movdqu, var, reg)
#define movdqu_r2m(reg,var) mmx_r2m (movdqu, reg, var)
#define movdqu_r2r(regs,regd) mmx_r2r (movdqu, regs, regd)
#define pmullw_r2m(reg,var) mmx_r2m (pmullw, reg, var)
#define pslldq_i2r(imm,reg) mmx_i2r (pslldq, imm, reg)
#define psrldq_i2r(imm,reg) mmx_i2r (psrldq, imm, reg)
#define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd)
#define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd)
#endif /* AVCODEC_I386MMX_H */

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config ET131X
tristate "Agere ET-1310 Gigabit Ethernet support"
depends on NETDEV_1000 && PCI
default n
---help---
This driver supports Agere ET-1310 ethernet adapters.
To compile this driver as a module, choose M here. The module
will be called et131x.
config ET131X_DEBUG
bool "Enable et131x debugging"
depends on ET131X
default n
---help---
Say Y for detailed debug information.
If in doubt, say N.

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#
# Makefile for the Agere ET-131x ethernet driver
#
obj-$(CONFIG_ET131X) += et131x.o
et131x-objs := et1310_eeprom.o \
et1310_jagcore.o \
et1310_mac.o \
et1310_phy.o \
et1310_pm.o \
et1310_rx.o \
et1310_tx.o \
et131x_config.o \
et131x_debug.o \
et131x_initpci.o \
et131x_isr.o \
et131x_netdev.o

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This is a driver for the ET1310 network device.
Based on the driver found at https://sourceforge.net/projects/et131x/
Cleaned up immensely by Olaf Hartman <o.hartmann@telovital.com> and Christoph
Hellwig <hch@infradead.org>
Note, the powermanagement options were removed from the vendor provided
driver as they did not build properly at the time.
TODO:
- kernel coding style cleanups
- forward port for latest network driver changes
- kill useless typecasts (e.g. in et1310_phy.c)
- alloc_etherdev is initializing memory with zero?!?
- add_timer call in et131x_netdev.c is correct?
- Add power saving functionality (suspend, sleep, resume)
- Implement a few more kernel Parameter (set mac )
Please send patches to:
Greg Kroah-Hartman <gregkh@suse.de>
And Cc: Olaf Hartmann <o.hartmann@telovital.com> as he has this device and can
test any changes.

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_eeprom.c - Code used to access the device's EEPROM
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_eeprom.h"
#include "et131x_adapter.h"
#include "et131x_initpci.h"
#include "et131x_isr.h"
#include "et1310_tx.h"
/*
* EEPROM Defines
*/
/* LBCIF Register Groups (addressed via 32-bit offsets) */
#define LBCIF_DWORD0_GROUP_OFFSET 0xAC
#define LBCIF_DWORD1_GROUP_OFFSET 0xB0
/* LBCIF Registers (addressed via 8-bit offsets) */
#define LBCIF_ADDRESS_REGISTER_OFFSET 0xAC
#define LBCIF_DATA_REGISTER_OFFSET 0xB0
#define LBCIF_CONTROL_REGISTER_OFFSET 0xB1
#define LBCIF_STATUS_REGISTER_OFFSET 0xB2
/* LBCIF Control Register Bits */
#define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
#define LBCIF_CONTROL_PAGE_WRITE 0x02
#define LBCIF_CONTROL_UNUSED1 0x04
#define LBCIF_CONTROL_EEPROM_RELOAD 0x08
#define LBCIF_CONTROL_UNUSED2 0x10
#define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
#define LBCIF_CONTROL_I2C_WRITE 0x40
#define LBCIF_CONTROL_LBCIF_ENABLE 0x80
/* LBCIF Status Register Bits */
#define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
#define LBCIF_STATUS_I2C_IDLE 0x02
#define LBCIF_STATUS_ACK_ERROR 0x04
#define LBCIF_STATUS_GENERAL_ERROR 0x08
#define LBCIF_STATUS_UNUSED 0x30
#define LBCIF_STATUS_CHECKSUM_ERROR 0x40
#define LBCIF_STATUS_EEPROM_PRESENT 0x80
/* Miscellaneous Constraints */
#define MAX_NUM_REGISTER_POLLS 1000
#define MAX_NUM_WRITE_RETRIES 2
/*
* Define macros that allow individual register values to be extracted from a
* DWORD1 register grouping
*/
#define EXTRACT_DATA_REGISTER(x) (uint8_t)(x & 0xFF)
#define EXTRACT_STATUS_REGISTER(x) (uint8_t)((x >> 16) & 0xFF)
#define EXTRACT_CONTROL_REG(x) (uint8_t)((x >> 8) & 0xFF)
/**
* EepromWriteByte - Write a byte to the ET1310's EEPROM
* @pAdapter: pointer to our private adapter structure
* @unAddress: the address to write
* @bData: the value to write
* @unEepronId: the ID of the EEPROM
* @unAddressingMode: how the EEPROM is to be accessed
*
* Returns SUCCESS or FAILURE
*/
int32_t EepromWriteByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
uint8_t bData, uint32_t unEepromId,
uint32_t unAddressingMode)
{
struct pci_dev *pdev = pAdapter->pdev;
int32_t nIndex;
int32_t nRetries;
int32_t nError = false;
int32_t nI2CWriteActive = 0;
int32_t nWriteSuccessful = 0;
uint8_t bControl;
uint8_t bStatus = 0;
uint32_t unDword1 = 0;
uint32_t unData = 0;
/*
* The following excerpt is from "Serial EEPROM HW Design
* Specification" Version 0.92 (9/20/2004):
*
* Single Byte Writes
*
* For an EEPROM, an I2C single byte write is defined as a START
* condition followed by the device address, EEPROM address, one byte
* of data and a STOP condition. The STOP condition will trigger the
* EEPROM's internally timed write cycle to the nonvolatile memory.
* All inputs are disabled during this write cycle and the EEPROM will
* not respond to any access until the internal write is complete.
* The steps to execute a single byte write are as follows:
*
* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
* bits 7,1:0 both equal to 1, at least once after reset.
* Subsequent operations need only to check that bits 1:0 are
* equal to 1 prior to starting a single byte write.
*
* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
* and bits 1:0 both =0. Bit 5 should be set according to the
* type of EEPROM being accessed (1=two byte addressing, 0=one
* byte addressing).
*
* 3. Write the address to the LBCIF Address Register.
*
* 4. Write the data to the LBCIF Data Register (the I2C write will
* begin).
*
* 5. Monitor bit 1:0 of the LBCIF Status Register. When bits 1:0 are
* both equal to 1, the I2C write has completed and the internal
* write cycle of the EEPROM is about to start. (bits 1:0 = 01 is
* a legal state while waiting from both equal to 1, but bits
* 1:0 = 10 is invalid and implies that something is broken).
*
* 6. Check bit 3 of the LBCIF Status Register. If equal to 1, an
* error has occurred.
*
* 7. Check bit 2 of the LBCIF Status Register. If equal to 1 an ACK
* error has occurred on the address phase of the write. This
* could be due to an actual hardware failure or the EEPROM may
* still be in its internal write cycle from a previous write.
* This write operation was ignored and must be repeated later.
*
* 8. Set bit 6 of the LBCIF Control Register = 0. If another write is
* required, go to step 1.
*/
/* Step 1: */
for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
&unDword1)) {
nError = 1;
break;
}
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* bits 1:0 are equal to 1 */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
return FAILURE;
}
/* Step 2: */
bControl = 0;
bControl |= LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE;
if (unAddressingMode == DUAL_BYTE) {
bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
}
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
bControl)) {
return FAILURE;
}
nI2CWriteActive = 1;
/* Prepare EEPROM address for Step 3 */
unAddress |= (unAddressingMode == DUAL_BYTE) ?
(unEepromId << 16) : (unEepromId << 8);
for (nRetries = 0; nRetries < MAX_NUM_WRITE_RETRIES; nRetries++) {
/* Step 3:*/
if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
unAddress)) {
break;
}
/* Step 4: */
if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER_OFFSET,
bData)) {
break;
}
/* Step 5: */
for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev,
LBCIF_DWORD1_GROUP_OFFSET,
&unDword1)) {
nError = 1;
break;
}
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* I2C write complete */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
break;
}
/*
* Step 6: Don't break here if we are revision 1, this is
* so we do a blind write for load bug.
*/
if (bStatus & LBCIF_STATUS_GENERAL_ERROR
&& pAdapter->RevisionID == 0) {
break;
}
/* Step 7 */
if (bStatus & LBCIF_STATUS_ACK_ERROR) {
/*
* This could be due to an actual hardware failure
* or the EEPROM may still be in its internal write
* cycle from a previous write. This write operation
* was ignored and must be repeated later.
*/
udelay(10);
continue;
}
nWriteSuccessful = 1;
break;
}
/* Step 8: */
udelay(10);
nIndex = 0;
while (nI2CWriteActive) {
bControl &= ~LBCIF_CONTROL_I2C_WRITE;
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
bControl)) {
nWriteSuccessful = 0;
}
/* Do read until internal ACK_ERROR goes away meaning write
* completed
*/
do {
pci_write_config_dword(pdev,
LBCIF_ADDRESS_REGISTER_OFFSET,
unAddress);
do {
pci_read_config_dword(pdev,
LBCIF_DATA_REGISTER_OFFSET, &unData);
} while ((unData & 0x00010000) == 0);
} while (unData & 0x00040000);
bControl = EXTRACT_CONTROL_REG(unData);
if (bControl != 0xC0 || nIndex == 10000) {
break;
}
nIndex++;
}
return nWriteSuccessful ? SUCCESS : FAILURE;
}
/**
* EepromReadByte - Read a byte from the ET1310's EEPROM
* @pAdapter: pointer to our private adapter structure
* @unAddress: the address from which to read
* @pbData: a pointer to a byte in which to store the value of the read
* @unEepronId: the ID of the EEPROM
* @unAddressingMode: how the EEPROM is to be accessed
*
* Returns SUCCESS or FAILURE
*/
int32_t EepromReadByte(struct et131x_adapter *pAdapter, uint32_t unAddress,
uint8_t *pbData, uint32_t unEepromId,
uint32_t unAddressingMode)
{
struct pci_dev *pdev = pAdapter->pdev;
int32_t nIndex;
int32_t nError = 0;
uint8_t bControl;
uint8_t bStatus = 0;
uint32_t unDword1 = 0;
/*
* The following excerpt is from "Serial EEPROM HW Design
* Specification" Version 0.92 (9/20/2004):
*
* Single Byte Reads
*
* A single byte read is similar to the single byte write, with the
* exception of the data flow:
*
* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
* bits 7,1:0 both equal to 1, at least once after reset.
* Subsequent operations need only to check that bits 1:0 are equal
* to 1 prior to starting a single byte read.
*
* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
* and bits 1:0 both =0. Bit 5 should be set according to the type
* of EEPROM being accessed (1=two byte addressing, 0=one byte
* addressing).
*
* 3. Write the address to the LBCIF Address Register (I2C read will
* begin).
*
* 4. Monitor bit 0 of the LBCIF Status Register. When =1, I2C read
* is complete. (if bit 1 =1 and bit 0 stays =0, a hardware failure
* has occurred).
*
* 5. Check bit 2 of the LBCIF Status Register. If =1, then an error
* has occurred. The data that has been returned from the PHY may
* be invalid.
*
* 6. Regardless of error status, read data byte from LBCIF Data
* Register. If another byte is required, go to step 1.
*/
/* Step 1: */
for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
&unDword1)) {
nError = 1;
break;
}
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL &&
bStatus & LBCIF_STATUS_I2C_IDLE) {
/* bits 1:0 are equal to 1 */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
return FAILURE;
}
/* Step 2: */
bControl = 0;
bControl |= LBCIF_CONTROL_LBCIF_ENABLE;
if (unAddressingMode == DUAL_BYTE) {
bControl |= LBCIF_CONTROL_TWO_BYTE_ADDR;
}
if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER_OFFSET,
bControl)) {
return FAILURE;
}
/* Step 3: */
unAddress |= (unAddressingMode == DUAL_BYTE) ?
(unEepromId << 16) : (unEepromId << 8);
if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER_OFFSET,
unAddress)) {
return FAILURE;
}
/* Step 4: */
for (nIndex = 0; nIndex < MAX_NUM_REGISTER_POLLS; nIndex++) {
/* Read registers grouped in DWORD1 */
if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP_OFFSET,
&unDword1)) {
nError = 1;
break;
}
bStatus = EXTRACT_STATUS_REGISTER(unDword1);
if (bStatus & LBCIF_STATUS_PHY_QUEUE_AVAIL
&& bStatus & LBCIF_STATUS_I2C_IDLE) {
/* I2C read complete */
break;
}
}
if (nError || (nIndex >= MAX_NUM_REGISTER_POLLS)) {
return FAILURE;
}
/* Step 6: */
*pbData = EXTRACT_DATA_REGISTER(unDword1);
return (bStatus & LBCIF_STATUS_ACK_ERROR) ? FAILURE : SUCCESS;
}

89
drivers/staging/et131x/et1310_eeprom.h Normal file
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_eeprom.h - Defines, structs, enums, prototypes, etc. used for EEPROM
* access routines
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET1310_EEPROM_H__
#define __ET1310_EEPROM_H__
#include "et1310_address_map.h"
#ifndef SUCCESS
#define SUCCESS 0
#define FAILURE 1
#endif
#ifndef READ
#define READ 0
#define WRITE 1
#endif
#ifndef SINGLE_BYTE
#define SINGLE_BYTE 0
#define DUAL_BYTE 1
#endif
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
int32_t EepromWriteByte(struct et131x_adapter *adapter, u32 unAddress,
u8 bData, u32 unEepromId,
u32 unAddressingMode);
int32_t EepromReadByte(struct et131x_adapter *adapter, u32 unAddress,
u8 *pbData, u32 unEepromId,
u32 unAddressingMode);
#endif /* _ET1310_EEPROM_H_ */

220
drivers/staging/et131x/et1310_jagcore.c Normal file
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_jagcore.c - All code pertaining to the ET1301/ET131x's JAGcore
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et131x_adapter.h"
#include "et131x_initpci.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
/**
* ConfigGlobalRegs - Used to configure the global registers on the JAGCore
* @pAdpater: pointer to our adapter structure
*/
void ConfigGlobalRegs(struct et131x_adapter *pAdapter)
{
struct _GLOBAL_t __iomem *pGbl = &pAdapter->CSRAddress->global;
DBG_ENTER(et131x_dbginfo);
if (pAdapter->RegistryPhyLoopbk == false) {
if (pAdapter->RegistryJumboPacket < 2048) {
/* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
* block of RAM that the driver can split between Tx
* and Rx as it desires. Our default is to split it
* 50/50:
*/
writel(0, &pGbl->rxq_start_addr.value);
writel(pAdapter->RegistryRxMemEnd,
&pGbl->rxq_end_addr.value);
writel(pAdapter->RegistryRxMemEnd + 1,
&pGbl->txq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1,
&pGbl->txq_end_addr.value);
} else if (pAdapter->RegistryJumboPacket < 8192) {
/* For jumbo packets > 2k but < 8k, split 50-50. */
writel(0, &pGbl->rxq_start_addr.value);
writel(INTERNAL_MEM_RX_OFFSET,
&pGbl->rxq_end_addr.value);
writel(INTERNAL_MEM_RX_OFFSET + 1,
&pGbl->txq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1,
&pGbl->txq_end_addr.value);
} else {
/* 9216 is the only packet size greater than 8k that
* is available. The Tx buffer has to be big enough
* for one whole packet on the Tx side. We'll make
* the Tx 9408, and give the rest to Rx
*/
writel(0x0000, &pGbl->rxq_start_addr.value);
writel(0x01b3, &pGbl->rxq_end_addr.value);
writel(0x01b4, &pGbl->txq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1,
&pGbl->txq_end_addr.value);
}
/* Initialize the loopback register. Disable all loopbacks. */
writel(0, &pGbl->loopback.value);
} else {
/* For PHY Line loopback, the memory is configured as if Tx
* and Rx both have all the memory. This is because the
* RxMAC will write data into the space, and the TxMAC will
* read it out.
*/
writel(0, &pGbl->rxq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1, &pGbl->rxq_end_addr.value);
writel(0, &pGbl->txq_start_addr.value);
writel(INTERNAL_MEM_SIZE - 1, &pGbl->txq_end_addr.value);
/* Initialize the loopback register (MAC loopback). */
writel(1, &pGbl->loopback.value);
}
/* MSI Register */
writel(0, &pGbl->msi_config.value);
/* By default, disable the watchdog timer. It will be enabled when
* a packet is queued.
*/
writel(0, &pGbl->watchdog_timer);
DBG_LEAVE(et131x_dbginfo);
}
/**
* ConfigMMCRegs - Used to configure the main memory registers in the JAGCore
* @pAdapter: pointer to our adapter structure
*/
void ConfigMMCRegs(struct et131x_adapter *pAdapter)
{
MMC_CTRL_t mmc_ctrl = { 0 };
DBG_ENTER(et131x_dbginfo);
/* All we need to do is initialize the Memory Control Register */
mmc_ctrl.bits.force_ce = 0x0;
mmc_ctrl.bits.rxdma_disable = 0x0;
mmc_ctrl.bits.txdma_disable = 0x0;
mmc_ctrl.bits.txmac_disable = 0x0;
mmc_ctrl.bits.rxmac_disable = 0x0;
mmc_ctrl.bits.arb_disable = 0x0;
mmc_ctrl.bits.mmc_enable = 0x1;
writel(mmc_ctrl.value, &pAdapter->CSRAddress->mmc.mmc_ctrl.value);
DBG_LEAVE(et131x_dbginfo);
}
void et131x_enable_interrupts(struct et131x_adapter *adapter)
{
uint32_t MaskValue;
/* Enable all global interrupts */
if ((adapter->FlowControl == TxOnly) || (adapter->FlowControl == Both)) {
MaskValue = INT_MASK_ENABLE;
} else {
MaskValue = INT_MASK_ENABLE_NO_FLOW;
}
if (adapter->DriverNoPhyAccess) {
MaskValue |= 0x10000;
}
adapter->CachedMaskValue.value = MaskValue;
writel(MaskValue, &adapter->CSRAddress->global.int_mask.value);
}
void et131x_disable_interrupts(struct et131x_adapter * adapter)
{
/* Disable all global interrupts */
adapter->CachedMaskValue.value = INT_MASK_DISABLE;
writel(INT_MASK_DISABLE, &adapter->CSRAddress->global.int_mask.value);
}

112
drivers/staging/et131x/et1310_jagcore.h Normal file
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_jagcore.h - Defines, structs, enums, prototypes, etc. pertaining to
* the JAGCore
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET1310_JAGCORE_H__
#define __ET1310_JAGCORE_H__
#include "et1310_address_map.h"
#define INTERNAL_MEM_SIZE 0x400 //1024 of internal memory
#define INTERNAL_MEM_RX_OFFSET 0x1FF //50% Tx, 50% Rx
#define REGS_MAX_ARRAY 4096
/*
* For interrupts, normal running is:
* rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
* watchdog_interrupt & txdma_xfer_done
*
* In both cases, when flow control is enabled for either Tx or bi-direction,
* we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
* buffer rings are running low.
*/
#define INT_MASK_DISABLE 0xffffffff
// NOTE: Masking out MAC_STAT Interrupt for now...
//#define INT_MASK_ENABLE 0xfff6bf17
//#define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
#define INT_MASK_ENABLE 0xfffebf17
#define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
/* DATA STRUCTURES FOR DIRECT REGISTER ACCESS */
typedef struct {
u8 bReadWrite;
u32 nRegCount;
u32 nData[REGS_MAX_ARRAY];
u32 nOffsets[REGS_MAX_ARRAY];
} JAGCORE_ACCESS_REGS, *PJAGCORE_ACCESS_REGS;
typedef struct {
u8 bReadWrite;
u32 nDataWidth;
u32 nRegCount;
u32 nOffsets[REGS_MAX_ARRAY];
u32 nData[REGS_MAX_ARRAY];
} PCI_CFG_SPACE_REGS, *PPCI_CFG_SPACE_REGS;
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
void ConfigGlobalRegs(struct et131x_adapter *pAdapter);
void ConfigMMCRegs(struct et131x_adapter *pAdapter);
void et131x_enable_interrupts(struct et131x_adapter *adapter);
void et131x_disable_interrupts(struct et131x_adapter *adapter);
#endif /* __ET1310_JAGCORE_H__ */

792
drivers/staging/et131x/et1310_mac.c Normal file
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@ -0,0 +1,792 @@
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_mac.c - All code and routines pertaining to the MAC
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include <linux/crc32.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_mac.h"
#include "et131x_adapter.h"
#include "et131x_initpci.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
/**
* ConfigMacRegs1 - Initialize the first part of MAC regs
* @pAdpater: pointer to our adapter structure
*/
void ConfigMACRegs1(struct et131x_adapter *pAdapter)
{
struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
MAC_STATION_ADDR1_t station1;
MAC_STATION_ADDR2_t station2;
MAC_IPG_t ipg;
MAC_HFDP_t hfdp;
MII_MGMT_CFG_t mii_mgmt_cfg;
DBG_ENTER(et131x_dbginfo);
/* First we need to reset everything. Write to MAC configuration
* register 1 to perform reset.
*/
writel(0xC00F0000, &pMac->cfg1.value);
/* Next lets configure the MAC Inter-packet gap register */
ipg.bits.non_B2B_ipg_1 = 0x38; // 58d
ipg.bits.non_B2B_ipg_2 = 0x58; // 88d
ipg.bits.min_ifg_enforce = 0x50; // 80d
ipg.bits.B2B_ipg = 0x60; // 96d
writel(ipg.value, &pMac->ipg.value);
/* Next lets configure the MAC Half Duplex register */
hfdp.bits.alt_beb_trunc = 0xA;
hfdp.bits.alt_beb_enable = 0x0;
hfdp.bits.bp_no_backoff = 0x0;
hfdp.bits.no_backoff = 0x0;
hfdp.bits.excess_defer = 0x1;
hfdp.bits.rexmit_max = 0xF;
hfdp.bits.coll_window = 0x37; // 55d
writel(hfdp.value, &pMac->hfdp.value);
/* Next lets configure the MAC Interface Control register */
writel(0, &pMac->if_ctrl.value);
/* Let's move on to setting up the mii managment configuration */
mii_mgmt_cfg.bits.reset_mii_mgmt = 0;
mii_mgmt_cfg.bits.scan_auto_incremt = 0;
mii_mgmt_cfg.bits.preamble_suppress = 0;
mii_mgmt_cfg.bits.mgmt_clk_reset = 0x7;
writel(mii_mgmt_cfg.value, &pMac->mii_mgmt_cfg.value);
/* Next lets configure the MAC Station Address register. These
* values are read from the EEPROM during initialization and stored
* in the adapter structure. We write what is stored in the adapter
* structure to the MAC Station Address registers high and low. This
* station address is used for generating and checking pause control
* packets.
*/
station2.bits.Octet1 = pAdapter->CurrentAddress[0];
station2.bits.Octet2 = pAdapter->CurrentAddress[1];
station1.bits.Octet3 = pAdapter->CurrentAddress[2];
station1.bits.Octet4 = pAdapter->CurrentAddress[3];
station1.bits.Octet5 = pAdapter->CurrentAddress[4];
station1.bits.Octet6 = pAdapter->CurrentAddress[5];
writel(station1.value, &pMac->station_addr_1.value);
writel(station2.value, &pMac->station_addr_2.value);
/* Max ethernet packet in bytes that will passed by the mac without
* being truncated. Allow the MAC to pass 4 more than our max packet
* size. This is 4 for the Ethernet CRC.
*
* Packets larger than (RegistryJumboPacket) that do not contain a
* VLAN ID will be dropped by the Rx function.
*/
writel(pAdapter->RegistryJumboPacket + 4, &pMac->max_fm_len.value);
/* clear out MAC config reset */
writel(0, &pMac->cfg1.value);
DBG_LEAVE(et131x_dbginfo);
}
/**
* ConfigMacRegs2 - Initialize the second part of MAC regs
* @pAdpater: pointer to our adapter structure
*/
void ConfigMACRegs2(struct et131x_adapter *pAdapter)
{
int32_t delay = 0;
struct _MAC_t __iomem *pMac = &pAdapter->CSRAddress->mac;
MAC_CFG1_t cfg1;
MAC_CFG2_t cfg2;
MAC_IF_CTRL_t ifctrl;
TXMAC_CTL_t ctl;
DBG_ENTER(et131x_dbginfo);
ctl.value = readl(&pAdapter->CSRAddress->txmac.ctl.value);
cfg1.value = readl(&pMac->cfg1.value);
cfg2.value = readl(&pMac->cfg2.value);
ifctrl.value = readl(&pMac->if_ctrl.value);
if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_1000MBPS) {
cfg2.bits.if_mode = 0x2;
ifctrl.bits.phy_mode = 0x0;
} else {
cfg2.bits.if_mode = 0x1;
ifctrl.bits.phy_mode = 0x1;
}
/* We need to enable Rx/Tx */
cfg1.bits.rx_enable = 0x1;
cfg1.bits.tx_enable = 0x1;
/* Set up flow control */
cfg1.bits.tx_flow = 0x1;
if ((pAdapter->FlowControl == RxOnly) ||
(pAdapter->FlowControl == Both)) {
cfg1.bits.rx_flow = 0x1;
} else {
cfg1.bits.rx_flow = 0x0;
}
/* Initialize loop back to off */
cfg1.bits.loop_back = 0;
writel(cfg1.value, &pMac->cfg1.value);
/* Now we need to initialize the MAC Configuration 2 register */
cfg2.bits.preamble_len = 0x7;
cfg2.bits.huge_frame = 0x0;
/* LENGTH FIELD CHECKING bit4: Set this bit to cause the MAC to check
* the frame's length field to ensure it matches the actual data
* field length. Clear this bit if no length field checking is
* desired. Its default is 0.
*/
cfg2.bits.len_check = 0x1;
if (pAdapter->RegistryPhyLoopbk == false) {
cfg2.bits.pad_crc = 0x1;
cfg2.bits.crc_enable = 0x1;
} else {
cfg2.bits.pad_crc = 0;
cfg2.bits.crc_enable = 0;
}
/* 1 - full duplex, 0 - half-duplex */
cfg2.bits.full_duplex = pAdapter->uiDuplexMode;
ifctrl.bits.ghd_mode = !pAdapter->uiDuplexMode;
writel(ifctrl.value, &pMac->if_ctrl.value);
writel(cfg2.value, &pMac->cfg2.value);
do {
udelay(10);
delay++;
cfg1.value = readl(&pMac->cfg1.value);
} while ((!cfg1.bits.syncd_rx_en ||
!cfg1.bits.syncd_tx_en) &&
delay < 100);
if (delay == 100) {
DBG_ERROR(et131x_dbginfo,
"Syncd bits did not respond correctly cfg1 word 0x%08x\n",
cfg1.value);
}
DBG_TRACE(et131x_dbginfo,
"Speed %d, Dup %d, CFG1 0x%08x, CFG2 0x%08x, if_ctrl 0x%08x\n",
pAdapter->uiLinkSpeed, pAdapter->uiDuplexMode,
readl(&pMac->cfg1.value), readl(&pMac->cfg2.value),
readl(&pMac->if_ctrl.value));
/* Enable TXMAC */
ctl.bits.txmac_en = 0x1;
ctl.bits.fc_disable = 0x1;
writel(ctl.value, &pAdapter->CSRAddress->txmac.ctl.value);
/* Ready to start the RXDMA/TXDMA engine */
if (!MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER)) {
et131x_rx_dma_enable(pAdapter);
et131x_tx_dma_enable(pAdapter);
} else {
DBG_WARNING(et131x_dbginfo,
"Didn't enable Rx/Tx due to low-power mode\n");
}
DBG_LEAVE(et131x_dbginfo);
}
void ConfigRxMacRegs(struct et131x_adapter *pAdapter)
{
struct _RXMAC_t __iomem *pRxMac = &pAdapter->CSRAddress->rxmac;
RXMAC_WOL_SA_LO_t sa_lo;
RXMAC_WOL_SA_HI_t sa_hi;
RXMAC_PF_CTRL_t pf_ctrl = { 0 };
DBG_ENTER(et131x_dbginfo);
/* Disable the MAC while it is being configured (also disable WOL) */
writel(0x8, &pRxMac->ctrl.value);
/* Initialize WOL to disabled. */
writel(0, &pRxMac->crc0.value);
writel(0, &pRxMac->crc12.value);
writel(0, &pRxMac->crc34.value);
/* We need to set the WOL mask0 - mask4 next. We initialize it to
* its default Values of 0x00000000 because there are not WOL masks
* as of this time.
*/
writel(0, &pRxMac->mask0_word0);
writel(0, &pRxMac->mask0_word1);
writel(0, &pRxMac->mask0_word2);
writel(0, &pRxMac->mask0_word3);
writel(0, &pRxMac->mask1_word0);
writel(0, &pRxMac->mask1_word1);
writel(0, &pRxMac->mask1_word2);
writel(0, &pRxMac->mask1_word3);
writel(0, &pRxMac->mask2_word0);
writel(0, &pRxMac->mask2_word1);
writel(0, &pRxMac->mask2_word2);
writel(0, &pRxMac->mask2_word3);
writel(0, &pRxMac->mask3_word0);
writel(0, &pRxMac->mask3_word1);
writel(0, &pRxMac->mask3_word2);
writel(0, &pRxMac->mask3_word3);
writel(0, &pRxMac->mask4_word0);
writel(0, &pRxMac->mask4_word1);
writel(0, &pRxMac->mask4_word2);
writel(0, &pRxMac->mask4_word3);
/* Lets setup the WOL Source Address */
sa_lo.bits.sa3 = pAdapter->CurrentAddress[2];
sa_lo.bits.sa4 = pAdapter->CurrentAddress[3];
sa_lo.bits.sa5 = pAdapter->CurrentAddress[4];
sa_lo.bits.sa6 = pAdapter->CurrentAddress[5];
writel(sa_lo.value, &pRxMac->sa_lo.value);
sa_hi.bits.sa1 = pAdapter->CurrentAddress[0];
sa_hi.bits.sa2 = pAdapter->CurrentAddress[1];
writel(sa_hi.value, &pRxMac->sa_hi.value);
/* Disable all Packet Filtering */
writel(0, &pRxMac->pf_ctrl.value);
/* Let's initialize the Unicast Packet filtering address */
if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_DIRECTED) {
SetupDeviceForUnicast(pAdapter);
pf_ctrl.bits.filter_uni_en = 1;
} else {
writel(0, &pRxMac->uni_pf_addr1.value);
writel(0, &pRxMac->uni_pf_addr2.value);
writel(0, &pRxMac->uni_pf_addr3.value);
}
/* Let's initialize the Multicast hash */
if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
pf_ctrl.bits.filter_multi_en = 0;
} else {
pf_ctrl.bits.filter_multi_en = 1;
SetupDeviceForMulticast(pAdapter);
}
/* Runt packet filtering. Didn't work in version A silicon. */
pf_ctrl.bits.min_pkt_size = NIC_MIN_PACKET_SIZE + 4;
pf_ctrl.bits.filter_frag_en = 1;
if (pAdapter->RegistryJumboPacket > 8192) {
RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;
/* In order to transmit jumbo packets greater than 8k, the
* FIFO between RxMAC and RxDMA needs to be reduced in size
* to (16k - Jumbo packet size). In order to implement this,
* we must use "cut through" mode in the RxMAC, which chops
* packets down into segments which are (max_size * 16). In
* this case we selected 256 bytes, since this is the size of
* the PCI-Express TLP's that the 1310 uses.
*/
mcif_ctrl_max_seg.bits.seg_en = 0x1;
mcif_ctrl_max_seg.bits.fc_en = 0x0;
mcif_ctrl_max_seg.bits.max_size = 0x10;
writel(mcif_ctrl_max_seg.value,
&pRxMac->mcif_ctrl_max_seg.value);
} else {
writel(0, &pRxMac->mcif_ctrl_max_seg.value);
}
/* Initialize the MCIF water marks */
writel(0, &pRxMac->mcif_water_mark.value);
/* Initialize the MIF control */
writel(0, &pRxMac->mif_ctrl.value);
/* Initialize the Space Available Register */
writel(0, &pRxMac->space_avail.value);
/* Initialize the the mif_ctrl register
* bit 3: Receive code error. One or more nibbles were signaled as
* errors during the reception of the packet. Clear this
* bit in Gigabit, set it in 100Mbit. This was derived
* experimentally at UNH.
* bit 4: Receive CRC error. The packet's CRC did not match the
* internally generated CRC.
* bit 5: Receive length check error. Indicates that frame length
* field value in the packet does not match the actual data
* byte length and is not a type field.
* bit 16: Receive frame truncated.
* bit 17: Drop packet enable
*/
if (pAdapter->uiLinkSpeed == TRUEPHY_SPEED_100MBPS) {
writel(0x30038, &pRxMac->mif_ctrl.value);
} else {
writel(0x30030, &pRxMac->mif_ctrl.value);
}
/* Finally we initialize RxMac to be enabled & WOL disabled. Packet
* filter is always enabled since it is where the runt packets are
* supposed to be dropped. For version A silicon, runt packet
* dropping doesn't work, so it is disabled in the pf_ctrl register,
* but we still leave the packet filter on.
*/
writel(pf_ctrl.value, &pRxMac->pf_ctrl.value);
writel(0x9, &pRxMac->ctrl.value);
DBG_LEAVE(et131x_dbginfo);
}
void ConfigTxMacRegs(struct et131x_adapter *pAdapter)
{
struct _TXMAC_t __iomem *pTxMac = &pAdapter->CSRAddress->txmac;
TXMAC_CF_PARAM_t Local;
DBG_ENTER(et131x_dbginfo);
/* We need to update the Control Frame Parameters
* cfpt - control frame pause timer set to 64 (0x40)
* cfep - control frame extended pause timer set to 0x0
*/
if (pAdapter->FlowControl == None) {
writel(0, &pTxMac->cf_param.value);
} else {
Local.bits.cfpt = 0x40;
Local.bits.cfep = 0x0;
writel(Local.value, &pTxMac->cf_param.value);
}
DBG_LEAVE(et131x_dbginfo);
}
void ConfigMacStatRegs(struct et131x_adapter *pAdapter)
{
struct _MAC_STAT_t __iomem *pDevMacStat =
&pAdapter->CSRAddress->macStat;
DBG_ENTER(et131x_dbginfo);
/* Next we need to initialize all the MAC_STAT registers to zero on
* the device.
*/
writel(0, &pDevMacStat->RFcs);
writel(0, &pDevMacStat->RAln);
writel(0, &pDevMacStat->RFlr);
writel(0, &pDevMacStat->RDrp);
writel(0, &pDevMacStat->RCde);
writel(0, &pDevMacStat->ROvr);
writel(0, &pDevMacStat->RFrg);
writel(0, &pDevMacStat->TScl);
writel(0, &pDevMacStat->TDfr);
writel(0, &pDevMacStat->TMcl);
writel(0, &pDevMacStat->TLcl);
writel(0, &pDevMacStat->TNcl);
writel(0, &pDevMacStat->TOvr);
writel(0, &pDevMacStat->TUnd);
/* Unmask any counters that we want to track the overflow of.
* Initially this will be all counters. It may become clear later
* that we do not need to track all counters.
*/
{
MAC_STAT_REG_1_t Carry1M = { 0xffffffff };
Carry1M.bits.rdrp = 0;
Carry1M.bits.rjbr = 1;
Carry1M.bits.rfrg = 0;
Carry1M.bits.rovr = 0;
Carry1M.bits.rund = 1;
Carry1M.bits.rcse = 1;
Carry1M.bits.rcde = 0;
Carry1M.bits.rflr = 0;
Carry1M.bits.raln = 0;
Carry1M.bits.rxuo = 1;
Carry1M.bits.rxpf = 1;
Carry1M.bits.rxcf = 1;
Carry1M.bits.rbca = 1;
Carry1M.bits.rmca = 1;
Carry1M.bits.rfcs = 0;
Carry1M.bits.rpkt = 1;
Carry1M.bits.rbyt = 1;
Carry1M.bits.trmgv = 1;
Carry1M.bits.trmax = 1;
Carry1M.bits.tr1k = 1;
Carry1M.bits.tr511 = 1;
Carry1M.bits.tr255 = 1;
Carry1M.bits.tr127 = 1;
Carry1M.bits.tr64 = 1;
writel(Carry1M.value, &pDevMacStat->Carry1M.value);
}
{
MAC_STAT_REG_2_t Carry2M = { 0xffffffff };
Carry2M.bits.tdrp = 1;
Carry2M.bits.tpfh = 1;
Carry2M.bits.tncl = 0;
Carry2M.bits.txcl = 1;
Carry2M.bits.tlcl = 0;
Carry2M.bits.tmcl = 0;
Carry2M.bits.tscl = 0;
Carry2M.bits.tedf = 1;
Carry2M.bits.tdfr = 0;
Carry2M.bits.txpf = 1;
Carry2M.bits.tbca = 1;
Carry2M.bits.tmca = 1;
Carry2M.bits.tpkt = 1;
Carry2M.bits.tbyt = 1;
Carry2M.bits.tfrg = 1;
Carry2M.bits.tund = 0;
Carry2M.bits.tovr = 0;
Carry2M.bits.txcf = 1;
Carry2M.bits.tfcs = 1;
Carry2M.bits.tjbr = 1;
writel(Carry2M.value, &pDevMacStat->Carry2M.value);
}
DBG_LEAVE(et131x_dbginfo);
}
void ConfigFlowControl(struct et131x_adapter * pAdapter)
{
if (pAdapter->uiDuplexMode == 0) {
pAdapter->FlowControl = None;
} else {
char RemotePause, RemoteAsyncPause;
ET1310_PhyAccessMiBit(pAdapter,
TRUEPHY_BIT_READ, 5, 10, &RemotePause);
ET1310_PhyAccessMiBit(pAdapter,
TRUEPHY_BIT_READ, 5, 11,
&RemoteAsyncPause);
if ((RemotePause == TRUEPHY_BIT_SET) &&
(RemoteAsyncPause == TRUEPHY_BIT_SET)) {
pAdapter->FlowControl = pAdapter->RegistryFlowControl;
} else if ((RemotePause == TRUEPHY_BIT_SET) &&
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
if (pAdapter->RegistryFlowControl == Both) {
pAdapter->FlowControl = Both;
} else {
pAdapter->FlowControl = None;
}
} else if ((RemotePause == TRUEPHY_BIT_CLEAR) &&
(RemoteAsyncPause == TRUEPHY_BIT_CLEAR)) {
pAdapter->FlowControl = None;
} else {/* if (RemotePause == TRUEPHY_CLEAR_BIT &&
RemoteAsyncPause == TRUEPHY_SET_BIT) */
if (pAdapter->RegistryFlowControl == Both) {
pAdapter->FlowControl = RxOnly;
} else {
pAdapter->FlowControl = None;
}
}
}
}
/**
* UpdateMacStatHostCounters - Update the local copy of the statistics
* @pAdapter: pointer to the adapter structure
*/
void UpdateMacStatHostCounters(struct et131x_adapter *pAdapter)
{
struct _ce_stats_t *stats = &pAdapter->Stats;
struct _MAC_STAT_t __iomem *pDevMacStat =
&pAdapter->CSRAddress->macStat;
stats->collisions += readl(&pDevMacStat->TNcl);
stats->first_collision += readl(&pDevMacStat->TScl);
stats->tx_deferred += readl(&pDevMacStat->TDfr);
stats->excessive_collisions += readl(&pDevMacStat->TMcl);
stats->late_collisions += readl(&pDevMacStat->TLcl);
stats->tx_uflo += readl(&pDevMacStat->TUnd);
stats->max_pkt_error += readl(&pDevMacStat->TOvr);
stats->alignment_err += readl(&pDevMacStat->RAln);
stats->crc_err += readl(&pDevMacStat->RCde);
stats->norcvbuf += readl(&pDevMacStat->RDrp);
stats->rx_ov_flow += readl(&pDevMacStat->ROvr);
stats->code_violations += readl(&pDevMacStat->RFcs);
stats->length_err += readl(&pDevMacStat->RFlr);
stats->other_errors += readl(&pDevMacStat->RFrg);
}
/**
* HandleMacStatInterrupt
* @pAdapter: pointer to the adapter structure
*
* One of the MACSTAT counters has wrapped. Update the local copy of
* the statistics held in the adapter structure, checking the "wrap"
* bit for each counter.
*/
void HandleMacStatInterrupt(struct et131x_adapter *pAdapter)
{
MAC_STAT_REG_1_t Carry1;
MAC_STAT_REG_2_t Carry2;
DBG_ENTER(et131x_dbginfo);
/* Read the interrupt bits from the register(s). These are Clear On
* Write.
*/
Carry1.value = readl(&pAdapter->CSRAddress->macStat.Carry1.value);
Carry2.value = readl(&pAdapter->CSRAddress->macStat.Carry2.value);
writel(Carry1.value, &pAdapter->CSRAddress->macStat.Carry1.value);
writel(Carry2.value, &pAdapter->CSRAddress->macStat.Carry2.value);
/* We need to do update the host copy of all the MAC_STAT counters.
* For each counter, check it's overflow bit. If the overflow bit is
* set, then increment the host version of the count by one complete
* revolution of the counter. This routine is called when the counter
* block indicates that one of the counters has wrapped.
*/
if (Carry1.bits.rfcs) {
pAdapter->Stats.code_violations += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.raln) {
pAdapter->Stats.alignment_err += COUNTER_WRAP_12_BIT;
}
if (Carry1.bits.rflr) {
pAdapter->Stats.length_err += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rfrg) {
pAdapter->Stats.other_errors += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rcde) {
pAdapter->Stats.crc_err += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rovr) {
pAdapter->Stats.rx_ov_flow += COUNTER_WRAP_16_BIT;
}
if (Carry1.bits.rdrp) {
pAdapter->Stats.norcvbuf += COUNTER_WRAP_16_BIT;
}
if (Carry2.bits.tovr) {
pAdapter->Stats.max_pkt_error += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tund) {
pAdapter->Stats.tx_uflo += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tscl) {
pAdapter->Stats.first_collision += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tdfr) {
pAdapter->Stats.tx_deferred += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tmcl) {
pAdapter->Stats.excessive_collisions += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tlcl) {
pAdapter->Stats.late_collisions += COUNTER_WRAP_12_BIT;
}
if (Carry2.bits.tncl) {
pAdapter->Stats.collisions += COUNTER_WRAP_12_BIT;
}
DBG_LEAVE(et131x_dbginfo);
}
void SetupDeviceForMulticast(struct et131x_adapter *pAdapter)
{
struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
uint32_t nIndex;
uint32_t result;
uint32_t hash1 = 0;
uint32_t hash2 = 0;
uint32_t hash3 = 0;
uint32_t hash4 = 0;
PM_CSR_t pm_csr;
DBG_ENTER(et131x_dbginfo);
/* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
* the multi-cast LIST. If it is NOT specified, (and "ALL" is not
* specified) then we should pass NO multi-cast addresses to the
* driver.
*/
if (pAdapter->PacketFilter & ET131X_PACKET_TYPE_MULTICAST) {
DBG_VERBOSE(et131x_dbginfo,
"MULTICAST flag is set, MCCount: %d\n",
pAdapter->MCAddressCount);
/* Loop through our multicast array and set up the device */
for (nIndex = 0; nIndex < pAdapter->MCAddressCount; nIndex++) {
DBG_VERBOSE(et131x_dbginfo,
"MCList[%d]: %02x:%02x:%02x:%02x:%02x:%02x\n",
nIndex,
pAdapter->MCList[nIndex][0],
pAdapter->MCList[nIndex][1],
pAdapter->MCList[nIndex][2],
pAdapter->MCList[nIndex][3],
pAdapter->MCList[nIndex][4],
pAdapter->MCList[nIndex][5]);
result = ether_crc(6, pAdapter->MCList[nIndex]);
result = (result & 0x3F800000) >> 23;
if (result < 32) {
hash1 |= (1 << result);
} else if ((31 < result) && (result < 64)) {
result -= 32;
hash2 |= (1 << result);
} else if ((63 < result) && (result < 96)) {
result -= 64;
hash3 |= (1 << result);
} else {
result -= 96;
hash4 |= (1 << result);
}
}
}
/* Write out the new hash to the device */
pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
if (pm_csr.bits.pm_phy_sw_coma == 0) {
writel(hash1, &rxmac->multi_hash1);
writel(hash2, &rxmac->multi_hash2);
writel(hash3, &rxmac->multi_hash3);
writel(hash4, &rxmac->multi_hash4);
}
DBG_LEAVE(et131x_dbginfo);
}
void SetupDeviceForUnicast(struct et131x_adapter *pAdapter)
{
struct _RXMAC_t __iomem *rxmac = &pAdapter->CSRAddress->rxmac;
RXMAC_UNI_PF_ADDR1_t uni_pf1;
RXMAC_UNI_PF_ADDR2_t uni_pf2;
RXMAC_UNI_PF_ADDR3_t uni_pf3;
PM_CSR_t pm_csr;
DBG_ENTER(et131x_dbginfo);
/* Set up unicast packet filter reg 3 to be the first two octets of
* the MAC address for both address
*
* Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
* MAC address for second address
*
* Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
* MAC address for first address
*/
uni_pf3.bits.addr1_1 = pAdapter->CurrentAddress[0];
uni_pf3.bits.addr1_2 = pAdapter->CurrentAddress[1];
uni_pf3.bits.addr2_1 = pAdapter->CurrentAddress[0];
uni_pf3.bits.addr2_2 = pAdapter->CurrentAddress[1];
uni_pf2.bits.addr2_3 = pAdapter->CurrentAddress[2];
uni_pf2.bits.addr2_4 = pAdapter->CurrentAddress[3];
uni_pf2.bits.addr2_5 = pAdapter->CurrentAddress[4];
uni_pf2.bits.addr2_6 = pAdapter->CurrentAddress[5];
uni_pf1.bits.addr1_3 = pAdapter->CurrentAddress[2];
uni_pf1.bits.addr1_4 = pAdapter->CurrentAddress[3];
uni_pf1.bits.addr1_5 = pAdapter->CurrentAddress[4];
uni_pf1.bits.addr1_6 = pAdapter->CurrentAddress[5];
pm_csr.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
if (pm_csr.bits.pm_phy_sw_coma == 0) {
writel(uni_pf1.value, &rxmac->uni_pf_addr1.value);
writel(uni_pf2.value, &rxmac->uni_pf_addr2.value);
writel(uni_pf3.value, &rxmac->uni_pf_addr3.value);
}
DBG_LEAVE(et131x_dbginfo);
}

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_mac.h - Defines, structs, enums, prototypes, etc. pertaining to the
* MAC.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef _ET1310_MAC_H_
#define _ET1310_MAC_H_
#include "et1310_address_map.h"
#define COUNTER_WRAP_28_BIT 0x10000000
#define COUNTER_WRAP_22_BIT 0x400000
#define COUNTER_WRAP_16_BIT 0x10000
#define COUNTER_WRAP_12_BIT 0x1000
#define COUNTER_MASK_28_BIT (COUNTER_WRAP_28_BIT - 1)
#define COUNTER_MASK_22_BIT (COUNTER_WRAP_22_BIT - 1)
#define COUNTER_MASK_16_BIT (COUNTER_WRAP_16_BIT - 1)
#define COUNTER_MASK_12_BIT (COUNTER_WRAP_12_BIT - 1)
#define UPDATE_COUNTER(HostCnt,DevCnt) \
HostCnt = HostCnt + DevCnt;
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
void ConfigMACRegs1(struct et131x_adapter *adapter);
void ConfigMACRegs2(struct et131x_adapter *adapter);
void ConfigRxMacRegs(struct et131x_adapter *adapter);
void ConfigTxMacRegs(struct et131x_adapter *adapter);
void ConfigMacStatRegs(struct et131x_adapter *adapter);
void ConfigFlowControl(struct et131x_adapter *adapter);
void UpdateMacStatHostCounters(struct et131x_adapter *adapter);
void HandleMacStatInterrupt(struct et131x_adapter *adapter);
void SetupDeviceForMulticast(struct et131x_adapter *adapter);
void SetupDeviceForUnicast(struct et131x_adapter *adapter);
#endif /* _ET1310_MAC_H_ */

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drivers/staging/et131x/et1310_phy.c Normal file
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_phy.h - Defines, structs, enums, prototypes, etc. pertaining to the
* PHY.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef _ET1310_PHY_H_
#define _ET1310_PHY_H_
#include "et1310_address_map.h"
#define TRUEPHY_SUCCESS 0
#define TRUEPHY_FAILURE 1
typedef void *TRUEPHY_HANDLE;
typedef void *TRUEPHY_PLATFORM_HANDLE;
typedef void *TRUEPHY_OSAL_HANDLE;
/* MI Register Addresses */
#define MI_CONTROL_REG 0
#define MI_STATUS_REG 1
#define MI_PHY_IDENTIFIER_1_REG 2
#define MI_PHY_IDENTIFIER_2_REG 3
#define MI_AUTONEG_ADVERTISEMENT_REG 4
#define MI_AUTONEG_LINK_PARTNER_ABILITY_REG 5
#define MI_AUTONEG_EXPANSION_REG 6
#define MI_AUTONEG_NEXT_PAGE_TRANSMIT_REG 7
#define MI_LINK_PARTNER_NEXT_PAGE_REG 8
#define MI_1000BASET_CONTROL_REG 9
#define MI_1000BASET_STATUS_REG 10
#define MI_RESERVED11_REG 11
#define MI_RESERVED12_REG 12
#define MI_RESERVED13_REG 13
#define MI_RESERVED14_REG 14
#define MI_EXTENDED_STATUS_REG 15
/* VMI Register Addresses */
#define VMI_RESERVED16_REG 16
#define VMI_RESERVED17_REG 17
#define VMI_RESERVED18_REG 18
#define VMI_LOOPBACK_CONTROL_REG 19
#define VMI_RESERVED20_REG 20
#define VMI_MI_CONTROL_REG 21
#define VMI_PHY_CONFIGURATION_REG 22
#define VMI_PHY_CONTROL_REG 23
#define VMI_INTERRUPT_MASK_REG 24
#define VMI_INTERRUPT_STATUS_REG 25
#define VMI_PHY_STATUS_REG 26
#define VMI_LED_CONTROL_1_REG 27
#define VMI_LED_CONTROL_2_REG 28
#define VMI_RESERVED29_REG 29
#define VMI_RESERVED30_REG 30
#define VMI_RESERVED31_REG 31
/* PHY Register Mapping(MI) Management Interface Regs */
typedef struct _MI_REGS_t {
u8 bmcr; // Basic mode control reg(Reg 0x00)
u8 bmsr; // Basic mode status reg(Reg 0x01)
u8 idr1; // Phy identifier reg 1(Reg 0x02)
u8 idr2; // Phy identifier reg 2(Reg 0x03)
u8 anar; // Auto-Negotiation advertisement(Reg 0x04)
u8 anlpar; // Auto-Negotiation link Partner Ability(Reg 0x05)
u8 aner; // Auto-Negotiation expansion reg(Reg 0x06)
u8 annptr; // Auto-Negotiation next page transmit reg(Reg 0x07)
u8 lpnpr; // link partner next page reg(Reg 0x08)
u8 gcr; // Gigabit basic mode control reg(Reg 0x09)
u8 gsr; // Gigabit basic mode status reg(Reg 0x0A)
u8 mi_res1[4]; // Future use by MI working group(Reg 0x0B - 0x0E)
u8 esr; // Extended status reg(Reg 0x0F)
u8 mi_res2[3]; // Future use by MI working group(Reg 0x10 - 0x12)
u8 loop_ctl; // Loopback Control Reg(Reg 0x13)
u8 mi_res3; // Future use by MI working group(Reg 0x14)
u8 mcr; // MI Control Reg(Reg 0x15)
u8 pcr; // Configuration Reg(Reg 0x16)
u8 phy_ctl; // PHY Control Reg(Reg 0x17)
u8 imr; // Interrupt Mask Reg(Reg 0x18)
u8 isr; // Interrupt Status Reg(Reg 0x19)
u8 psr; // PHY Status Reg(Reg 0x1A)
u8 lcr1; // LED Control 1 Reg(Reg 0x1B)
u8 lcr2; // LED Control 2 Reg(Reg 0x1C)
u8 mi_res4[3]; // Future use by MI working group(Reg 0x1D - 0x1F)
} MI_REGS_t, *PMI_REGS_t;
/* MI Register 0: Basic mode control register */
typedef union _MI_BMCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 reset:1; // bit 15
u16 loopback:1; // bit 14
u16 speed_sel:1; // bit 13
u16 enable_autoneg:1; // bit 12
u16 power_down:1; // bit 11
u16 isolate:1; // bit 10
u16 restart_autoneg:1; // bit 9
u16 duplex_mode:1; // bit 8
u16 col_test:1; // bit 7
u16 speed_1000_sel:1; // bit 6
u16 res1:6; // bits 0-5
#else
u16 res1:6; // bits 0-5
u16 speed_1000_sel:1; // bit 6
u16 col_test:1; // bit 7
u16 duplex_mode:1; // bit 8
u16 restart_autoneg:1; // bit 9
u16 isolate:1; // bit 10
u16 power_down:1; // bit 11
u16 enable_autoneg:1; // bit 12
u16 speed_sel:1; // bit 13
u16 loopback:1; // bit 14
u16 reset:1; // bit 15
#endif
} bits;
} MI_BMCR_t, *PMI_BMCR_t;
/* MI Register 1: Basic mode status register */
typedef union _MI_BMSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 link_100T4:1; // bit 15
u16 link_100fdx:1; // bit 14
u16 link_100hdx:1; // bit 13
u16 link_10fdx:1; // bit 12
u16 link_10hdx:1; // bit 11
u16 link_100T2fdx:1; // bit 10
u16 link_100T2hdx:1; // bit 9
u16 extend_status:1; // bit 8
u16 res1:1; // bit 7
u16 preamble_supress:1; // bit 6
u16 auto_neg_complete:1; // bit 5
u16 remote_fault:1; // bit 4
u16 auto_neg_able:1; // bit 3
u16 link_status:1; // bit 2
u16 jabber_detect:1; // bit 1
u16 ext_cap:1; // bit 0
#else
u16 ext_cap:1; // bit 0
u16 jabber_detect:1; // bit 1
u16 link_status:1; // bit 2
u16 auto_neg_able:1; // bit 3
u16 remote_fault:1; // bit 4
u16 auto_neg_complete:1; // bit 5
u16 preamble_supress:1; // bit 6
u16 res1:1; // bit 7
u16 extend_status:1; // bit 8
u16 link_100T2hdx:1; // bit 9
u16 link_100T2fdx:1; // bit 10
u16 link_10hdx:1; // bit 11
u16 link_10fdx:1; // bit 12
u16 link_100hdx:1; // bit 13
u16 link_100fdx:1; // bit 14
u16 link_100T4:1; // bit 15
#endif
} bits;
} MI_BMSR_t, *PMI_BMSR_t;
/* MI Register 2: Physical Identifier 1 */
typedef union _MI_IDR1_t {
u16 value;
struct {
u16 ieee_address:16; // 0x0282 default(bits 0-15)
} bits;
} MI_IDR1_t, *PMI_IDR1_t;
/* MI Register 3: Physical Identifier 2 */
typedef union _MI_IDR2_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 ieee_address:6; // 111100 default(bits 10-15)
u16 model_no:6; // 000001 default(bits 4-9)
u16 rev_no:4; // 0010 default(bits 0-3)
#else
u16 rev_no:4; // 0010 default(bits 0-3)
u16 model_no:6; // 000001 default(bits 4-9)
u16 ieee_address:6; // 111100 default(bits 10-15)
#endif
} bits;
} MI_IDR2_t, *PMI_IDR2_t;
/* MI Register 4: Auto-negotiation advertisement register */
typedef union _MI_ANAR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 np_indication:1; // bit 15
u16 res2:1; // bit 14
u16 remote_fault:1; // bit 13
u16 res1:1; // bit 12
u16 cap_asmpause:1; // bit 11
u16 cap_pause:1; // bit 10
u16 cap_100T4:1; // bit 9
u16 cap_100fdx:1; // bit 8
u16 cap_100hdx:1; // bit 7
u16 cap_10fdx:1; // bit 6
u16 cap_10hdx:1; // bit 5
u16 selector:5; // bits 0-4
#else
u16 selector:5; // bits 0-4
u16 cap_10hdx:1; // bit 5
u16 cap_10fdx:1; // bit 6
u16 cap_100hdx:1; // bit 7
u16 cap_100fdx:1; // bit 8
u16 cap_100T4:1; // bit 9
u16 cap_pause:1; // bit 10
u16 cap_asmpause:1; // bit 11
u16 res1:1; // bit 12
u16 remote_fault:1; // bit 13
u16 res2:1; // bit 14
u16 np_indication:1; // bit 15
#endif
} bits;
} MI_ANAR_t, *PMI_ANAR_t;
/* MI Register 5: Auto-negotiation link partner advertisement register */
typedef struct _MI_ANLPAR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 np_indication:1; // bit 15
u16 acknowledge:1; // bit 14
u16 remote_fault:1; // bit 13
u16 res1:1; // bit 12
u16 cap_asmpause:1; // bit 11
u16 cap_pause:1; // bit 10
u16 cap_100T4:1; // bit 9
u16 cap_100fdx:1; // bit 8
u16 cap_100hdx:1; // bit 7
u16 cap_10fdx:1; // bit 6
u16 cap_10hdx:1; // bit 5
u16 selector:5; // bits 0-4
#else
u16 selector:5; // bits 0-4
u16 cap_10hdx:1; // bit 5
u16 cap_10fdx:1; // bit 6
u16 cap_100hdx:1; // bit 7
u16 cap_100fdx:1; // bit 8
u16 cap_100T4:1; // bit 9
u16 cap_pause:1; // bit 10
u16 cap_asmpause:1; // bit 11
u16 res1:1; // bit 12
u16 remote_fault:1; // bit 13
u16 acknowledge:1; // bit 14
u16 np_indication:1; // bit 15
#endif
} bits;
} MI_ANLPAR_t, *PMI_ANLPAR_t;
/* MI Register 6: Auto-negotiation expansion register */
typedef union _MI_ANER_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res:11; // bits 5-15
u16 pdf:1; // bit 4
u16 lp_np_able:1; // bit 3
u16 np_able:1; // bit 2
u16 page_rx:1; // bit 1
u16 lp_an_able:1; // bit 0
#else
u16 lp_an_able:1; // bit 0
u16 page_rx:1; // bit 1
u16 np_able:1; // bit 2
u16 lp_np_able:1; // bit 3
u16 pdf:1; // bit 4
u16 res:11; // bits 5-15
#endif
} bits;
} MI_ANER_t, *PMI_ANER_t;
/* MI Register 7: Auto-negotiation next page transmit reg(0x07) */
typedef union _MI_ANNPTR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 np:1; // bit 15
u16 res1:1; // bit 14
u16 msg_page:1; // bit 13
u16 ack2:1; // bit 12
u16 toggle:1; // bit 11
u16 msg:11; // bits 0-10
#else
u16 msg:11; // bits 0-10
u16 toggle:1; // bit 11
u16 ack2:1; // bit 12
u16 msg_page:1; // bit 13
u16 res1:1; // bit 14
u16 np:1; // bit 15
#endif
} bits;
} MI_ANNPTR_t, *PMI_ANNPTR_t;
/* MI Register 8: Link Partner Next Page Reg(0x08) */
typedef union _MI_LPNPR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 np:1; // bit 15
u16 ack:1; // bit 14
u16 msg_page:1; // bit 13
u16 ack2:1; // bit 12
u16 toggle:1; // bit 11
u16 msg:11; // bits 0-10
#else
u16 msg:11; // bits 0-10
u16 toggle:1; // bit 11
u16 ack2:1; // bit 12
u16 msg_page:1; // bit 13
u16 ack:1; // bit 14
u16 np:1; // bit 15
#endif
} bits;
} MI_LPNPR_t, *PMI_LPNPR_t;
/* MI Register 9: 1000BaseT Control Reg(0x09) */
typedef union _MI_GCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 test_mode:3; // bits 13-15
u16 ms_config_en:1; // bit 12
u16 ms_value:1; // bit 11
u16 port_type:1; // bit 10
u16 link_1000fdx:1; // bit 9
u16 link_1000hdx:1; // bit 8
u16 res:8; // bit 0-7
#else
u16 res:8; // bit 0-7
u16 link_1000hdx:1; // bit 8
u16 link_1000fdx:1; // bit 9
u16 port_type:1; // bit 10
u16 ms_value:1; // bit 11
u16 ms_config_en:1; // bit 12
u16 test_mode:3; // bits 13-15
#endif
} bits;
} MI_GCR_t, *PMI_GCR_t;
/* MI Register 10: 1000BaseT Status Reg(0x0A) */
typedef union _MI_GSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 ms_config_fault:1; // bit 15
u16 ms_resolve:1; // bit 14
u16 local_rx_status:1; // bit 13
u16 remote_rx_status:1; // bit 12
u16 link_1000fdx:1; // bit 11
u16 link_1000hdx:1; // bit 10
u16 res:2; // bits 8-9
u16 idle_err_cnt:8; // bits 0-7
#else
u16 idle_err_cnt:8; // bits 0-7
u16 res:2; // bits 8-9
u16 link_1000hdx:1; // bit 10
u16 link_1000fdx:1; // bit 11
u16 remote_rx_status:1; // bit 12
u16 local_rx_status:1; // bit 13
u16 ms_resolve:1; // bit 14
u16 ms_config_fault:1; // bit 15
#endif
} bits;
} MI_GSR_t, *PMI_GSR_t;
/* MI Register 11 - 14: Reserved Regs(0x0B - 0x0E) */
typedef union _MI_RES_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res15:1; // bit 15
u16 res14:1; // bit 14
u16 res13:1; // bit 13
u16 res12:1; // bit 12
u16 res11:1; // bit 11
u16 res10:1; // bit 10
u16 res9:1; // bit 9
u16 res8:1; // bit 8
u16 res7:1; // bit 7
u16 res6:1; // bit 6
u16 res5:1; // bit 5
u16 res4:1; // bit 4
u16 res3:1; // bit 3
u16 res2:1; // bit 2
u16 res1:1; // bit 1
u16 res0:1; // bit 0
#else
u16 res0:1; // bit 0
u16 res1:1; // bit 1
u16 res2:1; // bit 2
u16 res3:1; // bit 3
u16 res4:1; // bit 4
u16 res5:1; // bit 5
u16 res6:1; // bit 6
u16 res7:1; // bit 7
u16 res8:1; // bit 8
u16 res9:1; // bit 9
u16 res10:1; // bit 10
u16 res11:1; // bit 11
u16 res12:1; // bit 12
u16 res13:1; // bit 13
u16 res14:1; // bit 14
u16 res15:1; // bit 15
#endif
} bits;
} MI_RES_t, *PMI_RES_t;
/* MI Register 15: Extended status Reg(0x0F) */
typedef union _MI_ESR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 link_1000Xfdx:1; // bit 15
u16 link_1000Xhdx:1; // bit 14
u16 link_1000fdx:1; // bit 13
u16 link_1000hdx:1; // bit 12
u16 res:12; // bit 0-11
#else
u16 res:12; // bit 0-11
u16 link_1000hdx:1; // bit 12
u16 link_1000fdx:1; // bit 13
u16 link_1000Xhdx:1; // bit 14
u16 link_1000Xfdx:1; // bit 15
#endif
} bits;
} MI_ESR_t, *PMI_ESR_t;
/* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
/* MI Register 19: Loopback Control Reg(0x13) */
typedef union _MI_LCR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 mii_en:1; // bit 15
u16 pcs_en:1; // bit 14
u16 pmd_en:1; // bit 13
u16 all_digital_en:1; // bit 12
u16 replica_en:1; // bit 11
u16 line_driver_en:1; // bit 10
u16 res:10; // bit 0-9
#else
u16 res:10; // bit 0-9
u16 line_driver_en:1; // bit 10
u16 replica_en:1; // bit 11
u16 all_digital_en:1; // bit 12
u16 pmd_en:1; // bit 13
u16 pcs_en:1; // bit 14
u16 mii_en:1; // bit 15
#endif
} bits;
} MI_LCR_t, *PMI_LCR_t;
/* MI Register 20: Reserved Reg(0x14) */
/* MI Register 21: Management Interface Control Reg(0x15) */
typedef union _MI_MICR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:5; // bits 11-15
u16 mi_error_count:7; // bits 4-10
u16 res2:1; // bit 3
u16 ignore_10g_fr:1; // bit 2
u16 res3:1; // bit 1
u16 preamble_supress_en:1; // bit 0
#else
u16 preamble_supress_en:1; // bit 0
u16 res3:1; // bit 1
u16 ignore_10g_fr:1; // bit 2
u16 res2:1; // bit 3
u16 mi_error_count:7; // bits 4-10
u16 res1:5; // bits 11-15
#endif
} bits;
} MI_MICR_t, *PMI_MICR_t;
/* MI Register 22: PHY Configuration Reg(0x16) */
typedef union _MI_PHY_CONFIG_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 crs_tx_en:1; // bit 15
u16 res1:1; // bit 14
u16 tx_fifo_depth:2; // bits 12-13
u16 speed_downshift:2; // bits 10-11
u16 pbi_detect:1; // bit 9
u16 tbi_rate:1; // bit 8
u16 alternate_np:1; // bit 7
u16 group_mdio_en:1; // bit 6
u16 tx_clock_en:1; // bit 5
u16 sys_clock_en:1; // bit 4
u16 res2:1; // bit 3
u16 mac_if_mode:3; // bits 0-2
#else
u16 mac_if_mode:3; // bits 0-2
u16 res2:1; // bit 3
u16 sys_clock_en:1; // bit 4
u16 tx_clock_en:1; // bit 5
u16 group_mdio_en:1; // bit 6
u16 alternate_np:1; // bit 7
u16 tbi_rate:1; // bit 8
u16 pbi_detect:1; // bit 9
u16 speed_downshift:2; // bits 10-11
u16 tx_fifo_depth:2; // bits 12-13
u16 res1:1; // bit 14
u16 crs_tx_en:1; // bit 15
#endif
} bits;
} MI_PHY_CONFIG_t, *PMI_PHY_CONFIG_t;
/* MI Register 23: PHY CONTROL Reg(0x17) */
typedef union _MI_PHY_CONTROL_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:1; // bit 15
u16 tdr_en:1; // bit 14
u16 res2:1; // bit 13
u16 downshift_attempts:2; // bits 11-12
u16 res3:5; // bit 6-10
u16 jabber_10baseT:1; // bit 5
u16 sqe_10baseT:1; // bit 4
u16 tp_loopback_10baseT:1; // bit 3
u16 preamble_gen_en:1; // bit 2
u16 res4:1; // bit 1
u16 force_int:1; // bit 0
#else
u16 force_int:1; // bit 0
u16 res4:1; // bit 1
u16 preamble_gen_en:1; // bit 2
u16 tp_loopback_10baseT:1; // bit 3
u16 sqe_10baseT:1; // bit 4
u16 jabber_10baseT:1; // bit 5
u16 res3:5; // bit 6-10
u16 downshift_attempts:2; // bits 11-12
u16 res2:1; // bit 13
u16 tdr_en:1; // bit 14
u16 res1:1; // bit 15
#endif
} bits;
} MI_PHY_CONTROL_t, *PMI_PHY_CONTROL_t;
/* MI Register 24: Interrupt Mask Reg(0x18) */
typedef union _MI_IMR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:6; // bits 10-15
u16 mdio_sync_lost:1; // bit 9
u16 autoneg_status:1; // bit 8
u16 hi_bit_err:1; // bit 7
u16 np_rx:1; // bit 6
u16 err_counter_full:1; // bit 5
u16 fifo_over_underflow:1; // bit 4
u16 rx_status:1; // bit 3
u16 link_status:1; // bit 2
u16 automatic_speed:1; // bit 1
u16 int_en:1; // bit 0
#else
u16 int_en:1; // bit 0
u16 automatic_speed:1; // bit 1
u16 link_status:1; // bit 2
u16 rx_status:1; // bit 3
u16 fifo_over_underflow:1; // bit 4
u16 err_counter_full:1; // bit 5
u16 np_rx:1; // bit 6
u16 hi_bit_err:1; // bit 7
u16 autoneg_status:1; // bit 8
u16 mdio_sync_lost:1; // bit 9
u16 res1:6; // bits 10-15
#endif
} bits;
} MI_IMR_t, *PMI_IMR_t;
/* MI Register 25: Interrupt Status Reg(0x19) */
typedef union _MI_ISR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:6; // bits 10-15
u16 mdio_sync_lost:1; // bit 9
u16 autoneg_status:1; // bit 8
u16 hi_bit_err:1; // bit 7
u16 np_rx:1; // bit 6
u16 err_counter_full:1; // bit 5
u16 fifo_over_underflow:1; // bit 4
u16 rx_status:1; // bit 3
u16 link_status:1; // bit 2
u16 automatic_speed:1; // bit 1
u16 int_en:1; // bit 0
#else
u16 int_en:1; // bit 0
u16 automatic_speed:1; // bit 1
u16 link_status:1; // bit 2
u16 rx_status:1; // bit 3
u16 fifo_over_underflow:1; // bit 4
u16 err_counter_full:1; // bit 5
u16 np_rx:1; // bit 6
u16 hi_bit_err:1; // bit 7
u16 autoneg_status:1; // bit 8
u16 mdio_sync_lost:1; // bit 9
u16 res1:6; // bits 10-15
#endif
} bits;
} MI_ISR_t, *PMI_ISR_t;
/* MI Register 26: PHY Status Reg(0x1A) */
typedef union _MI_PSR_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:1; // bit 15
u16 autoneg_fault:2; // bit 13-14
u16 autoneg_status:1; // bit 12
u16 mdi_x_status:1; // bit 11
u16 polarity_status:1; // bit 10
u16 speed_status:2; // bits 8-9
u16 duplex_status:1; // bit 7
u16 link_status:1; // bit 6
u16 tx_status:1; // bit 5
u16 rx_status:1; // bit 4
u16 collision_status:1; // bit 3
u16 autoneg_en:1; // bit 2
u16 pause_en:1; // bit 1
u16 asymmetric_dir:1; // bit 0
#else
u16 asymmetric_dir:1; // bit 0
u16 pause_en:1; // bit 1
u16 autoneg_en:1; // bit 2
u16 collision_status:1; // bit 3
u16 rx_status:1; // bit 4
u16 tx_status:1; // bit 5
u16 link_status:1; // bit 6
u16 duplex_status:1; // bit 7
u16 speed_status:2; // bits 8-9
u16 polarity_status:1; // bit 10
u16 mdi_x_status:1; // bit 11
u16 autoneg_status:1; // bit 12
u16 autoneg_fault:2; // bit 13-14
u16 res1:1; // bit 15
#endif
} bits;
} MI_PSR_t, *PMI_PSR_t;
/* MI Register 27: LED Control Reg 1(0x1B) */
typedef union _MI_LCR1_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 res1:2; // bits 14-15
u16 led_dup_indicate:2; // bits 12-13
u16 led_10baseT:2; // bits 10-11
u16 led_collision:2; // bits 8-9
u16 res2:2; // bits 6-7
u16 res3:2; // bits 4-5
u16 pulse_dur:2; // bits 2-3
u16 pulse_stretch1:1; // bit 1
u16 pulse_stretch0:1; // bit 0
#else
u16 pulse_stretch0:1; // bit 0
u16 pulse_stretch1:1; // bit 1
u16 pulse_dur:2; // bits 2-3
u16 res3:2; // bits 4-5
u16 res2:2; // bits 6-7
u16 led_collision:2; // bits 8-9
u16 led_10baseT:2; // bits 10-11
u16 led_dup_indicate:2; // bits 12-13
u16 res1:2; // bits 14-15
#endif
} bits;
} MI_LCR1_t, *PMI_LCR1_t;
/* MI Register 28: LED Control Reg 2(0x1C) */
typedef union _MI_LCR2_t {
u16 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u16 led_link:4; // bits 12-15
u16 led_tx_rx:4; // bits 8-11
u16 led_100BaseTX:4; // bits 4-7
u16 led_1000BaseT:4; // bits 0-3
#else
u16 led_1000BaseT:4; // bits 0-3
u16 led_100BaseTX:4; // bits 4-7
u16 led_tx_rx:4; // bits 8-11
u16 led_link:4; // bits 12-15
#endif
} bits;
} MI_LCR2_t, *PMI_LCR2_t;
/* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
/* TruePHY headers */
typedef struct _TRUEPHY_ACCESS_MI_REGS_ {
TRUEPHY_HANDLE hTruePhy;
int32_t nPhyId;
u8 bReadWrite;
u8 *pbyRegs;
u8 *pwData;
int32_t nRegCount;
} TRUEPHY_ACCESS_MI_REGS, *PTRUEPHY_ACCESS_MI_REGS;
/* TruePHY headers */
typedef struct _TAG_TPAL_ACCESS_MI_REGS_ {
u32 nPhyId;
u8 bReadWrite;
u32 nRegCount;
u16 Data[4096];
u8 Regs[4096];
} TPAL_ACCESS_MI_REGS, *PTPAL_ACCESS_MI_REGS;
typedef TRUEPHY_HANDLE TPAL_HANDLE;
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
/* OS Specific Functions*/
void TPAL_SetPhy10HalfDuplex(struct et131x_adapter *adapter);
void TPAL_SetPhy10FullDuplex(struct et131x_adapter *adapter);
void TPAL_SetPhy10Force(struct et131x_adapter *pAdapter);
void TPAL_SetPhy100HalfDuplex(struct et131x_adapter *adapter);
void TPAL_SetPhy100FullDuplex(struct et131x_adapter *adapter);
void TPAL_SetPhy100Force(struct et131x_adapter *pAdapter);
void TPAL_SetPhy1000FullDuplex(struct et131x_adapter *adapter);
void TPAL_SetPhyAutoNeg(struct et131x_adapter *adapter);
/* Prototypes for ET1310_phy.c */
int et131x_xcvr_find(struct et131x_adapter *adapter);
int et131x_setphy_normal(struct et131x_adapter *adapter);
int32_t PhyMiRead(struct et131x_adapter *adapter,
u8 xcvrAddr, u8 xcvrReg, u16 *value);
/* static inline function does not work because et131x_adapter is not always
* defined
*/
#define MiRead(adapter, xcvrReg, value) \
PhyMiRead((adapter), (adapter)->Stats.xcvr_addr, (xcvrReg), (value))
int32_t MiWrite(struct et131x_adapter *adapter,
u8 xcvReg, u16 value);
void et131x_Mii_check(struct et131x_adapter *pAdapter,
MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints);
/* This last is not strictly required (the driver could call the TPAL
* version instead), but this sets the adapter up correctly, and calls the
* access routine indirectly. This protects the driver from changes in TPAL.
*/
void SetPhy_10BaseTHalfDuplex(struct et131x_adapter *adapter);
/* Defines for PHY access routines */
// Define bit operation flags
#define TRUEPHY_BIT_CLEAR 0
#define TRUEPHY_BIT_SET 1
#define TRUEPHY_BIT_READ 2
// Define read/write operation flags
#ifndef TRUEPHY_READ
#define TRUEPHY_READ 0
#define TRUEPHY_WRITE 1
#define TRUEPHY_MASK 2
#endif
// Define speeds
#define TRUEPHY_SPEED_10MBPS 0
#define TRUEPHY_SPEED_100MBPS 1
#define TRUEPHY_SPEED_1000MBPS 2
// Define duplex modes
#define TRUEPHY_DUPLEX_HALF 0
#define TRUEPHY_DUPLEX_FULL 1
// Define master/slave configuration values
#define TRUEPHY_CFG_SLAVE 0
#define TRUEPHY_CFG_MASTER 1
// Define MDI/MDI-X settings
#define TRUEPHY_MDI 0
#define TRUEPHY_MDIX 1
#define TRUEPHY_AUTO_MDI_MDIX 2
// Define 10Base-T link polarities
#define TRUEPHY_POLARITY_NORMAL 0
#define TRUEPHY_POLARITY_INVERTED 1
// Define auto-negotiation results
#define TRUEPHY_ANEG_NOT_COMPLETE 0
#define TRUEPHY_ANEG_COMPLETE 1
#define TRUEPHY_ANEG_DISABLED 2
/* Define duplex advertisment flags */
#define TRUEPHY_ADV_DUPLEX_NONE 0x00
#define TRUEPHY_ADV_DUPLEX_FULL 0x01
#define TRUEPHY_ADV_DUPLEX_HALF 0x02
#define TRUEPHY_ADV_DUPLEX_BOTH \
(TRUEPHY_ADV_DUPLEX_FULL | TRUEPHY_ADV_DUPLEX_HALF)
#define PHY_CONTROL 0x00 //#define TRU_MI_CONTROL_REGISTER 0
#define PHY_STATUS 0x01 //#define TRU_MI_STATUS_REGISTER 1
#define PHY_ID_1 0x02 //#define TRU_MI_PHY_IDENTIFIER_1_REGISTER 2
#define PHY_ID_2 0x03 //#define TRU_MI_PHY_IDENTIFIER_2_REGISTER 3
#define PHY_AUTO_ADVERTISEMENT 0x04 //#define TRU_MI_ADVERTISEMENT_REGISTER 4
#define PHY_AUTO_LINK_PARTNER 0x05 //#define TRU_MI_LINK_PARTNER_ABILITY_REGISTER 5
#define PHY_AUTO_EXPANSION 0x06 //#define TRU_MI_EXPANSION_REGISTER 6
#define PHY_AUTO_NEXT_PAGE_TX 0x07 //#define TRU_MI_NEXT_PAGE_TRANSMIT_REGISTER 7
#define PHY_LINK_PARTNER_NEXT_PAGE 0x08 //#define TRU_MI_LINK_PARTNER_NEXT_PAGE_REGISTER 8
#define PHY_1000_CONTROL 0x09 //#define TRU_MI_1000BASET_CONTROL_REGISTER 9
#define PHY_1000_STATUS 0x0A //#define TRU_MI_1000BASET_STATUS_REGISTER 10
#define PHY_EXTENDED_STATUS 0x0F //#define TRU_MI_EXTENDED_STATUS_REGISTER 15
// some defines for modem registers that seem to be 'reserved'
#define PHY_INDEX_REG 0x10
#define PHY_DATA_REG 0x11
#define PHY_MPHY_CONTROL_REG 0x12 //#define TRU_VMI_MPHY_CONTROL_REGISTER 18
#define PHY_LOOPBACK_CONTROL 0x13 //#define TRU_VMI_LOOPBACK_CONTROL_1_REGISTER 19
//#define TRU_VMI_LOOPBACK_CONTROL_2_REGISTER 20
#define PHY_REGISTER_MGMT_CONTROL 0x15 //#define TRU_VMI_MI_SEQ_CONTROL_REGISTER 21
#define PHY_CONFIG 0x16 //#define TRU_VMI_CONFIGURATION_REGISTER 22
#define PHY_PHY_CONTROL 0x17 //#define TRU_VMI_PHY_CONTROL_REGISTER 23
#define PHY_INTERRUPT_MASK 0x18 //#define TRU_VMI_INTERRUPT_MASK_REGISTER 24
#define PHY_INTERRUPT_STATUS 0x19 //#define TRU_VMI_INTERRUPT_STATUS_REGISTER 25
#define PHY_PHY_STATUS 0x1A //#define TRU_VMI_PHY_STATUS_REGISTER 26
#define PHY_LED_1 0x1B //#define TRU_VMI_LED_CONTROL_1_REGISTER 27
#define PHY_LED_2 0x1C //#define TRU_VMI_LED_CONTROL_2_REGISTER 28
//#define TRU_VMI_LINK_CONTROL_REGISTER 29
//#define TRU_VMI_TIMING_CONTROL_REGISTER
/* Prototypes for PHY access routines */
void ET1310_PhyInit(struct et131x_adapter *adapter);
void ET1310_PhyReset(struct et131x_adapter *adapter);
void ET1310_PhyPowerDown(struct et131x_adapter *adapter, bool down);
void ET1310_PhyAutoNeg(struct et131x_adapter *adapter, bool enable);
void ET1310_PhyDuplexMode(struct et131x_adapter *adapter, u16 duplex);
void ET1310_PhySpeedSelect(struct et131x_adapter *adapter, u16 speed);
void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *adapter,
u16 duplex);
void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *adapter,
u16 duplex);
void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *adapter,
u16 duplex);
void ET1310_PhyLinkStatus(struct et131x_adapter *adapter,
u8 *ucLinkStatus,
u32 *uiAutoNeg,
u32 *uiLinkSpeed,
u32 *uiDuplexMode,
u32 *uiMdiMdix,
u32 *uiMasterSlave, u32 *uiPolarity);
void ET1310_PhyAndOrReg(struct et131x_adapter *adapter,
u16 regnum, u16 andMask, u16 orMask);
void ET1310_PhyAccessMiBit(struct et131x_adapter *adapter,
u16 action,
u16 regnum, u16 bitnum, u8 *value);
#endif /* _ET1310_PHY_H_ */

207
drivers/staging/et131x/et1310_pm.c Normal file
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@ -0,0 +1,207 @@
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_pm.c - All power management related code (not completely implemented)
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_mac.h"
#include "et1310_rx.h"
#include "et131x_adapter.h"
#include "et131x_initpci.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
/**
* EnablePhyComa - called when network cable is unplugged
* @pAdapter: pointer to our adapter structure
*
* driver receive an phy status change interrupt while in D0 and check that
* phy_status is down.
*
* -- gate off JAGCore;
* -- set gigE PHY in Coma mode
* -- wake on phy_interrupt; Perform software reset JAGCore,
* re-initialize jagcore and gigE PHY
*
* Add D0-ASPM-PhyLinkDown Support:
* -- while in D0, when there is a phy_interrupt indicating phy link
* down status, call the MPSetPhyComa routine to enter this active
* state power saving mode
* -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt
* indicating linkup status, call the MPDisablePhyComa routine to
* restore JAGCore and gigE PHY
*/
void EnablePhyComa(struct et131x_adapter *pAdapter)
{
unsigned long lockflags;
PM_CSR_t GlobalPmCSR;
int32_t LoopCounter = 10;
DBG_ENTER(et131x_dbginfo);
GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
/* Save the GbE PHY speed and duplex modes. Need to restore this
* when cable is plugged back in
*/
pAdapter->PoMgmt.PowerDownSpeed = pAdapter->AiForceSpeed;
pAdapter->PoMgmt.PowerDownDuplex = pAdapter->AiForceDpx;
/* Stop sending packets. */
spin_lock_irqsave(&pAdapter->SendHWLock, lockflags);
MP_SET_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
spin_unlock_irqrestore(&pAdapter->SendHWLock, lockflags);
/* Wait for outstanding Receive packets */
while ((MP_GET_RCV_REF(pAdapter) != 0) && (LoopCounter-- > 0)) {
mdelay(2);
}
/* Gate off JAGCore 3 clock domains */
GlobalPmCSR.bits.pm_sysclk_gate = 0;
GlobalPmCSR.bits.pm_txclk_gate = 0;
GlobalPmCSR.bits.pm_rxclk_gate = 0;
writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
/* Program gigE PHY in to Coma mode */
GlobalPmCSR.bits.pm_phy_sw_coma = 1;
writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
DBG_LEAVE(et131x_dbginfo);
}
/**
* DisablePhyComa - Disable the Phy Coma Mode
* @pAdapter: pointer to our adapter structure
*/
void DisablePhyComa(struct et131x_adapter *pAdapter)
{
PM_CSR_t GlobalPmCSR;
DBG_ENTER(et131x_dbginfo);
GlobalPmCSR.value = readl(&pAdapter->CSRAddress->global.pm_csr.value);
/* Disable phy_sw_coma register and re-enable JAGCore clocks */
GlobalPmCSR.bits.pm_sysclk_gate = 1;
GlobalPmCSR.bits.pm_txclk_gate = 1;
GlobalPmCSR.bits.pm_rxclk_gate = 1;
GlobalPmCSR.bits.pm_phy_sw_coma = 0;
writel(GlobalPmCSR.value, &pAdapter->CSRAddress->global.pm_csr.value);
/* Restore the GbE PHY speed and duplex modes;
* Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
*/
pAdapter->AiForceSpeed = pAdapter->PoMgmt.PowerDownSpeed;
pAdapter->AiForceDpx = pAdapter->PoMgmt.PowerDownDuplex;
/* Re-initialize the send structures */
et131x_init_send(pAdapter);
/* Reset the RFD list and re-start RU */
et131x_reset_recv(pAdapter);
/* Bring the device back to the state it was during init prior to
* autonegotiation being complete. This way, when we get the auto-neg
* complete interrupt, we can complete init by calling ConfigMacREGS2.
*/
et131x_soft_reset(pAdapter);
/* setup et1310 as per the documentation ?? */
et131x_adapter_setup(pAdapter);
/* Allow Tx to restart */
MP_CLEAR_FLAG(pAdapter, fMP_ADAPTER_LOWER_POWER);
/* Need to re-enable Rx. */
et131x_rx_dma_enable(pAdapter);
DBG_LEAVE(et131x_dbginfo);
}

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_pm.h - Defines, structs, enums, prototypes, etc. pertaining to power
* management.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef _ET1310_PM_H_
#define _ET1310_PM_H_
#include "et1310_address_map.h"
#define MAX_WOL_PACKET_SIZE 0x80
#define MAX_WOL_MASK_SIZE ( MAX_WOL_PACKET_SIZE / 8 )
#define NUM_WOL_PATTERNS 0x5
#define CRC16_POLY 0x1021
/* Definition of NDIS_DEVICE_POWER_STATE */
typedef enum {
NdisDeviceStateUnspecified = 0,
NdisDeviceStateD0,
NdisDeviceStateD1,
NdisDeviceStateD2,
NdisDeviceStateD3
} NDIS_DEVICE_POWER_STATE;
typedef struct _MP_POWER_MGMT {
/* variable putting the phy into coma mode when boot up with no cable
* plugged in after 5 seconds
*/
u8 TransPhyComaModeOnBoot;
/* Array holding the five CRC values that the device is currently
* using for WOL. This will be queried when a pattern is to be
* removed.
*/
u32 localWolAndCrc0;
u16 WOLPatternList[NUM_WOL_PATTERNS];
u8 WOLMaskList[NUM_WOL_PATTERNS][MAX_WOL_MASK_SIZE];
u32 WOLMaskSize[NUM_WOL_PATTERNS];
/* IP address */
union {
u32 u32;
u8 u8[4];
} IPAddress;
/* Current Power state of the adapter. */
NDIS_DEVICE_POWER_STATE PowerState;
bool WOLState;
bool WOLEnabled;
bool Failed10Half;
bool bFailedStateTransition;
/* Next two used to save power information at power down. This
* information will be used during power up to set up parts of Power
* Management in JAGCore
*/
u32 tx_en;
u32 rx_en;
u16 PowerDownSpeed;
u8 PowerDownDuplex;
} MP_POWER_MGMT, *PMP_POWER_MGMT;
/* Forward declaration of the private adapter structure
* ( IS THERE A WAY TO DO THIS WITH A TYPEDEF??? )
*/
struct et131x_adapter;
u16 CalculateCCITCRC16(u8 *Pattern, u8 *Mask, u32 MaskSize);
void EnablePhyComa(struct et131x_adapter *adapter);
void DisablePhyComa(struct et131x_adapter *adapter);
#endif /* _ET1310_PM_H_ */

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_rx.h - Defines, structs, enums, prototypes, etc. pertaining to data
* reception.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET1310_RX_H__
#define __ET1310_RX_H__
#include "et1310_address_map.h"
#define USE_FBR0 true
#ifdef USE_FBR0
//#define FBR0_BUFFER_SIZE 256
#endif
//#define FBR1_BUFFER_SIZE 2048
#define FBR_CHUNKS 32
#define MAX_DESC_PER_RING_RX 1024
/* number of RFDs - default and min */
#ifdef USE_FBR0
#define RFD_LOW_WATER_MARK 40
#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 1024
#else
#define RFD_LOW_WATER_MARK 20
#define NIC_MIN_NUM_RFD 64
#define NIC_DEFAULT_NUM_RFD 256
#endif
#define NUM_PACKETS_HANDLED 256
#define ALCATEL_BAD_STATUS 0xe47f0000
#define ALCATEL_MULTICAST_PKT 0x01000000
#define ALCATEL_BROADCAST_PKT 0x02000000
/* typedefs for Free Buffer Descriptors */
typedef union _FBR_WORD2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 reserved:22; // bits 10-31
u32 bi:10; // bits 0-9(Buffer Index)
#else
u32 bi:10; // bits 0-9(Buffer Index)
u32 reserved:22; // bit 10-31
#endif
} bits;
} FBR_WORD2_t, *PFBR_WORD2_t;
typedef struct _FBR_DESC_t {
u32 addr_lo;
u32 addr_hi;
FBR_WORD2_t word2;
} FBR_DESC_t, *PFBR_DESC_t;
/* Typedefs for Packet Status Ring Descriptors */
typedef union _PKT_STAT_DESC_WORD0_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
// top 16 bits are from the Alcatel Status Word as enumerated in
// PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
#if 0
u32 asw_trunc:1; // bit 31(Rx frame truncated)
#endif
u32 asw_long_evt:1; // bit 31(Rx long event)
u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
u32 asw_pause_frame:1; // bit 28(is a pause frame)
u32 asw_control_frame:1; // bit 27(is a control frame)
u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
u32 asw_broadcast:1; // bit 25(has a broadcast address)
u32 asw_multicast:1; // bit 24(has a multicast address)
u32 asw_OK:1; // bit 23(valid CRC + no code error)
u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
u32 asw_CRC_err:1; // bit 20(CRC error)
u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
u32 unused:5; // bits 11-15
u32 vp:1; // bit 10(VLAN Packet)
u32 jp:1; // bit 9(Jumbo Packet)
u32 ft:1; // bit 8(Frame Truncated)
u32 drop:1; // bit 7(Drop packet)
u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
u32 wol:1; // bit 5(WOL Event)
u32 tcpp:1; // bit 4(TCP checksum pass)
u32 tcpa:1; // bit 3(TCP checksum assist)
u32 ipp:1; // bit 2(IP checksum pass)
u32 ipa:1; // bit 1(IP checksum assist)
u32 hp:1; // bit 0(hash pass)
#else
u32 hp:1; // bit 0(hash pass)
u32 ipa:1; // bit 1(IP checksum assist)
u32 ipp:1; // bit 2(IP checksum pass)
u32 tcpa:1; // bit 3(TCP checksum assist)
u32 tcpp:1; // bit 4(TCP checksum pass)
u32 wol:1; // bit 5(WOL Event)
u32 rxmac_error:1; // bit 6(RXMAC Error Indicator)
u32 drop:1; // bit 7(Drop packet)
u32 ft:1; // bit 8(Frame Truncated)
u32 jp:1; // bit 9(Jumbo Packet)
u32 vp:1; // bit 10(VLAN Packet)
u32 unused:5; // bits 11-15
u32 asw_prev_pkt_dropped:1;// bit 16(e.g. IFG too small on previous)
u32 asw_RX_DV_event:1; // bit 17(short receive event detected)
u32 asw_false_carrier_event:1; // bit 18(bad carrier since last good packet)
u32 asw_code_err:1; // bit 19(one or more nibbles signalled as errors)
u32 asw_CRC_err:1; // bit 20(CRC error)
u32 asw_len_chk_err:1; // bit 21(frame length field incorrect)
u32 asw_too_long:1; // bit 22(frame length > 1518 bytes)
u32 asw_OK:1; // bit 23(valid CRC + no code error)
u32 asw_multicast:1; // bit 24(has a multicast address)
u32 asw_broadcast:1; // bit 25(has a broadcast address)
u32 asw_dribble_nibble:1; // bit 26(spurious bits after EOP)
u32 asw_control_frame:1; // bit 27(is a control frame)
u32 asw_pause_frame:1; // bit 28(is a pause frame)
u32 asw_unsupported_op:1; // bit 29(unsupported OP code)
u32 asw_VLAN_tag:1; // bit 30(VLAN tag detected)
u32 asw_long_evt:1; // bit 31(Rx long event)
#if 0
u32 asw_trunc:1; // bit 31(Rx frame truncated)
#endif
#endif
} bits;
} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
typedef union _PKT_STAT_DESC_WORD1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:4; // bits 28-31
u32 ri:2; // bits 26-27(Ring Index)
u32 bi:10; // bits 16-25(Buffer Index)
u32 length:16; // bit 0-15(length in bytes)
#else
u32 length:16; // bit 0-15(length in bytes)
u32 bi:10; // bits 16-25(Buffer Index)
u32 ri:2; // bits 26-27(Ring Index)
u32 unused:4; // bits 28-31
#endif
} bits;
} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
typedef struct _PKT_STAT_DESC_t {
PKT_STAT_DESC_WORD0_t word0;
PKT_STAT_DESC_WORD1_t word1;
} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
/* Typedefs for the RX DMA status word */
/*
* RXSTAT_WORD0_t structure holds part of the status bits of the Rx DMA engine
* that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
* whichcontains Free Buffer ring 0 and 1 available offset.
*/
typedef union _rxstat_word0_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 FBR1unused:5; // bits 27-31
u32 FBR1wrap:1; // bit 26
u32 FBR1offset:10; // bits 16-25
u32 FBR0unused:5; // bits 11-15
u32 FBR0wrap:1; // bit 10
u32 FBR0offset:10; // bits 0-9
#else
u32 FBR0offset:10; // bits 0-9
u32 FBR0wrap:1; // bit 10
u32 FBR0unused:5; // bits 11-15
u32 FBR1offset:10; // bits 16-25
u32 FBR1wrap:1; // bit 26
u32 FBR1unused:5; // bits 27-31
#endif
} bits;
} RXSTAT_WORD0_t, *PRXSTAT_WORD0_t;
/*
* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
* that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
* which contains the Packet Status Ring available offset.
*/
typedef union _rxstat_word1_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 PSRunused:3; // bits 29-31
u32 PSRwrap:1; // bit 28
u32 PSRoffset:12; // bits 16-27
u32 reserved:16; // bits 0-15
#else
u32 reserved:16; // bits 0-15
u32 PSRoffset:12; // bits 16-27
u32 PSRwrap:1; // bit 28
u32 PSRunused:3; // bits 29-31
#endif
} bits;
} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
/*
* RX_STATUS_BLOCK_t is sructure representing the status of the Rx DMA engine
* it sits in free memory, and is pointed to by 0x101c / 0x1020
*/
typedef struct _rx_status_block_t {
RXSTAT_WORD0_t Word0;
RXSTAT_WORD1_t Word1;
} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
/*
* Structure for look-up table holding free buffer ring pointers
*/
typedef struct _FbrLookupTable {
void *Va[MAX_DESC_PER_RING_RX];
void *Buffer1[MAX_DESC_PER_RING_RX];
void *Buffer2[MAX_DESC_PER_RING_RX];
u32 PAHigh[MAX_DESC_PER_RING_RX];
u32 PALow[MAX_DESC_PER_RING_RX];
} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
typedef enum {
ONE_PACKET_INTERRUPT,
FOUR_PACKET_INTERRUPT
} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
/*
* Structure to hold the skb's in a list
*/
typedef struct rx_skb_list_elem {
struct list_head skb_list_elem;
dma_addr_t dma_addr;
struct sk_buff *skb;
} RX_SKB_LIST_ELEM, *PRX_SKB_LIST_ELEM;
/*
* RX_RING_t is sructure representing the adaptor's local reference(s) to the
* rings
*/
typedef struct _rx_ring_t {
#ifdef USE_FBR0
void *pFbr0RingVa;
dma_addr_t pFbr0RingPa;
void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
uint64_t Fbr0Realpa;
uint64_t Fbr0offset;
DMA10W_t local_Fbr0_full;
u32 Fbr0NumEntries;
u32 Fbr0BufferSize;
#endif
void *pFbr1RingVa;
dma_addr_t pFbr1RingPa;
void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
uint64_t Fbr1Realpa;
uint64_t Fbr1offset;
FBRLOOKUPTABLE *Fbr[2];
DMA10W_t local_Fbr1_full;
u32 Fbr1NumEntries;
u32 Fbr1BufferSize;
void *pPSRingVa;
dma_addr_t pPSRingPa;
uint64_t pPSRingRealPa;
uint64_t pPSRingOffset;
RXDMA_PSR_FULL_OFFSET_t local_psr_full;
u32 PsrNumEntries;
void *pRxStatusVa;
dma_addr_t pRxStatusPa;
uint64_t RxStatusRealPA;
uint64_t RxStatusOffset;
struct list_head RecvBufferPool;
/* RECV */
struct list_head RecvList;
struct list_head RecvPendingList;
u32 nReadyRecv;
u32 NumRfd;
bool UnfinishedReceives;
struct list_head RecvPacketPool;
/* lookaside lists */
struct kmem_cache *RecvLookaside;
} RX_RING_t, *PRX_RING_t;
/* Forward reference of RFD */
struct _MP_RFD;
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
/* PROTOTYPES for Initialization */
int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
struct _MP_RFD *pMpRfd);
void et131x_rfd_resources_free(struct et131x_adapter *adapter,
struct _MP_RFD *pMpRfd);
int et131x_init_recv(struct et131x_adapter *adapter);
void ConfigRxDmaRegs(struct et131x_adapter *adapter);
void SetRxDmaTimer(struct et131x_adapter *adapter);
void et131x_rx_dma_disable(struct et131x_adapter *adapter);
void et131x_rx_dma_enable(struct et131x_adapter *adapter);
void et131x_reset_recv(struct et131x_adapter *adapter);
void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
#endif /* __ET1310_RX_H__ */

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et1310_tx.h - Defines, structs, enums, prototypes, etc. pertaining to data
* transmission.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET1310_TX_H__
#define __ET1310_TX_H__
/* Typedefs for Tx Descriptor Ring */
/*
* TXDESC_WORD2_t structure holds part of the control bits in the Tx Descriptor
* ring for the ET-1310
*/
typedef union _txdesc_word2_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 vlan_prio:3; // bits 29-31(VLAN priority)
u32 vlan_cfi:1; // bit 28(cfi)
u32 vlan_tag:12; // bits 16-27(VLAN tag)
u32 length_in_bytes:16; // bits 0-15(packet length)
#else
u32 length_in_bytes:16; // bits 0-15(packet length)
u32 vlan_tag:12; // bits 16-27(VLAN tag)
u32 vlan_cfi:1; // bit 28(cfi)
u32 vlan_prio:3; // bits 29-31(VLAN priority)
#endif /* _BIT_FIELDS_HTOL */
} bits;
} TXDESC_WORD2_t, *PTXDESC_WORD2_t;
/*
* TXDESC_WORD3_t structure holds part of the control bits in the Tx Descriptor
* ring for the ET-1310
*/
typedef union _txdesc_word3_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:17; // bits 15-31
u32 udpa:1; // bit 14(UDP checksum assist)
u32 tcpa:1; // bit 13(TCP checksum assist)
u32 ipa:1; // bit 12(IP checksum assist)
u32 vlan:1; // bit 11(append VLAN tag)
u32 hp:1; // bit 10(Packet is a Huge packet)
u32 pp:1; // bit 9(pad packet)
u32 mac:1; // bit 8(MAC override)
u32 crc:1; // bit 7(append CRC)
u32 e:1; // bit 6(Tx frame has error)
u32 pf:1; // bit 5(send pause frame)
u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
u32 cw:1; // bit 3(Control word - no packet data)
u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
u32 f:1; // bit 1(first packet in the sequence)
u32 l:1; // bit 0(last packet in the sequence)
#else
u32 l:1; // bit 0(last packet in the sequence)
u32 f:1; // bit 1(first packet in the sequence)
u32 ir:1; // bit 2(interrupt the processor when this pkt sent)
u32 cw:1; // bit 3(Control word - no packet data)
u32 bp:1; // bit 4(Issue half-duplex backpressure (XON/XOFF)
u32 pf:1; // bit 5(send pause frame)
u32 e:1; // bit 6(Tx frame has error)
u32 crc:1; // bit 7(append CRC)
u32 mac:1; // bit 8(MAC override)
u32 pp:1; // bit 9(pad packet)
u32 hp:1; // bit 10(Packet is a Huge packet)
u32 vlan:1; // bit 11(append VLAN tag)
u32 ipa:1; // bit 12(IP checksum assist)
u32 tcpa:1; // bit 13(TCP checksum assist)
u32 udpa:1; // bit 14(UDP checksum assist)
u32 unused:17; // bits 15-31
#endif /* _BIT_FIELDS_HTOL */
} bits;
} TXDESC_WORD3_t, *PTXDESC_WORD3_t;
/* TX_DESC_ENTRY_t is sructure representing each descriptor on the ring */
typedef struct _tx_desc_entry_t {
u32 DataBufferPtrHigh;
u32 DataBufferPtrLow;
TXDESC_WORD2_t word2; // control words how to xmit the
TXDESC_WORD3_t word3; // data (detailed above)
} TX_DESC_ENTRY_t, *PTX_DESC_ENTRY_t;
/* Typedefs for Tx DMA engine status writeback */
/*
* TX_STATUS_BLOCK_t is sructure representing the status of the Tx DMA engine
* it sits in free memory, and is pointed to by 0x101c / 0x1020
*/
typedef union _tx_status_block_t {
u32 value;
struct {
#ifdef _BIT_FIELDS_HTOL
u32 unused:21; // bits 11-31
u32 serv_cpl_wrap:1; // bit 10
u32 serv_cpl:10; // bits 0-9
#else
u32 serv_cpl:10; // bits 0-9
u32 serv_cpl_wrap:1; // bit 10
u32 unused:21; // bits 11-31
#endif
} bits;
} TX_STATUS_BLOCK_t, *PTX_STATUS_BLOCK_t;
/* TCB (Transmit Control Block) */
typedef struct _MP_TCB {
struct _MP_TCB *Next;
u32 Flags;
u32 Count;
u32 PacketStaleCount;
struct sk_buff *Packet;
u32 PacketLength;
DMA10W_t WrIndex;
DMA10W_t WrIndexStart;
} MP_TCB, *PMP_TCB;
/* Structure to hold the skb's in a list */
typedef struct tx_skb_list_elem {
struct list_head skb_list_elem;
struct sk_buff *skb;
} TX_SKB_LIST_ELEM, *PTX_SKB_LIST_ELEM;
/* TX_RING_t is sructure representing our local reference(s) to the ring */
typedef struct _tx_ring_t {
/* TCB (Transmit Control Block) memory and lists */
PMP_TCB MpTcbMem;
/* List of TCBs that are ready to be used */
PMP_TCB TCBReadyQueueHead;
PMP_TCB TCBReadyQueueTail;
/* list of TCBs that are currently being sent. NOTE that access to all
* three of these (including nBusySend) are controlled via the
* TCBSendQLock. This lock should be secured prior to incementing /
* decrementing nBusySend, or any queue manipulation on CurrSendHead /
* Tail
*/
PMP_TCB CurrSendHead;
PMP_TCB CurrSendTail;
int32_t nBusySend;
/* List of packets (not TCBs) that were queued for lack of resources */
struct list_head SendWaitQueue;
int32_t nWaitSend;
/* The actual descriptor ring */
PTX_DESC_ENTRY_t pTxDescRingVa;
dma_addr_t pTxDescRingPa;
uint64_t pTxDescRingAdjustedPa;
uint64_t TxDescOffset;
/* ReadyToSend indicates where we last wrote to in the descriptor ring. */
DMA10W_t txDmaReadyToSend;
/* The location of the write-back status block */
PTX_STATUS_BLOCK_t pTxStatusVa;
dma_addr_t pTxStatusPa;
/* A Block of zeroes used to pad packets that are less than 60 bytes */
void *pTxDummyBlkVa;
dma_addr_t pTxDummyBlkPa;
TXMAC_ERR_t TxMacErr;
/* Variables to track the Tx interrupt coalescing features */
int32_t TxPacketsSinceLastinterrupt;
} TX_RING_t, *PTX_RING_t;
/* Forward declaration of the frag-list for the following prototypes */
typedef struct _MP_FRAG_LIST MP_FRAG_LIST, *PMP_FRAG_LIST;
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
/* PROTOTYPES for et1310_tx.c */
int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter);
void et131x_tx_dma_memory_free(struct et131x_adapter *adapter);
void ConfigTxDmaRegs(struct et131x_adapter *pAdapter);
void et131x_init_send(struct et131x_adapter *adapter);
void et131x_tx_dma_disable(struct et131x_adapter *pAdapter);
void et131x_tx_dma_enable(struct et131x_adapter *pAdapter);
void et131x_handle_send_interrupt(struct et131x_adapter *pAdapter);
void et131x_free_busy_send_packets(struct et131x_adapter *pAdapter);
int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev);
#endif /* __ET1310_TX_H__ */

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_adapter.h - Header which includes the private adapter structure, along
* with related support structures, macros, definitions, etc.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_ADAPTER_H__
#define __ET131X_ADAPTER_H__
#include "et1310_address_map.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
/*
* Do not change these values: if changed, then change also in respective
* TXdma and Rxdma engines
*/
#define NUM_DESC_PER_RING_TX 512 // TX Do not change these values
#define NUM_TCB 64
/*
* These values are all superseded by registry entries to facilitate tuning.
* Once the desired performance has been achieved, the optimal registry values
* should be re-populated to these #defines:
*/
#define NUM_TRAFFIC_CLASSES 1
/*
* There are three ways of counting errors - if there are more than X errors
* in Y packets (represented by the "SAMPLE" macros), if there are more than
* N errors in a S mSec time period (the "PERIOD" macros), or if there are
* consecutive packets with errors (CONSEC_ERRORED_THRESH). This last covers
* for "Bursty" errors, and the errored packets may well not be contiguous,
* but several errors where the packet counter has changed by less than a
* small amount will cause this count to increment.
*/
#define TX_PACKETS_IN_SAMPLE 10000
#define TX_MAX_ERRORS_IN_SAMPLE 50
#define TX_ERROR_PERIOD 1000
#define TX_MAX_ERRORS_IN_PERIOD 10
#define LINK_DETECTION_TIMER 5000
#define TX_CONSEC_RANGE 5
#define TX_CONSEC_ERRORED_THRESH 10
#define LO_MARK_PERCENT_FOR_PSR 15
#define LO_MARK_PERCENT_FOR_RX 15
/* Macros for flag and ref count operations */
#define MP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
#define MP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
#define MP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
#define MP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
#define MP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
#define MP_IS_FLAG_CLEAR(_M, _F) (((_M)->Flags & (_F)) == 0)
#define MP_INC_RCV_REF(_A) atomic_inc(&(_A)->RcvRefCount)
#define MP_DEC_RCV_REF(_A) atomic_dec(&(_A)->RcvRefCount)
#define MP_GET_RCV_REF(_A) atomic_read(&(_A)->RcvRefCount)
/* Macros specific to the private adapter structure */
#define MP_TCB_RESOURCES_AVAILABLE(_M) ((_M)->TxRing.nBusySend < NUM_TCB)
#define MP_TCB_RESOURCES_NOT_AVAILABLE(_M) ((_M)->TxRing.nBusySend >= NUM_TCB)
#define MP_SHOULD_FAIL_SEND(_M) ((_M)->Flags & fMP_ADAPTER_FAIL_SEND_MASK)
#define MP_IS_NOT_READY(_M) ((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
#define MP_IS_READY(_M) !((_M)->Flags & fMP_ADAPTER_NOT_READY_MASK)
#define MP_HAS_CABLE(_M) !((_M)->Flags & fMP_ADAPTER_NO_CABLE)
#define MP_LINK_DETECTED(_M) !((_M)->Flags & fMP_ADAPTER_LINK_DETECTION)
/* Counters for error rate monitoring */
typedef struct _MP_ERR_COUNTERS {
u32 PktCountTxPackets;
u32 PktCountTxErrors;
u32 TimerBasedTxErrors;
u32 PktCountLastError;
u32 ErredConsecPackets;
} MP_ERR_COUNTERS, *PMP_ERR_COUNTERS;
/* RFD (Receive Frame Descriptor) */
typedef struct _MP_RFD {
struct list_head list_node;
struct sk_buff *Packet;
u32 PacketSize; // total size of receive frame
u16 iBufferIndex;
u8 iRingIndex;
} MP_RFD, *PMP_RFD;
/* Enum for Flow Control */
typedef enum _eflow_control_t {
Both = 0,
TxOnly = 1,
RxOnly = 2,
None = 3
} eFLOW_CONTROL_t, *PeFLOW_CONTROL_t;
/* Struct to define some device statistics */
typedef struct _ce_stats_t {
/* Link Input/Output stats */
uint64_t ipackets; // # of in packets
uint64_t opackets; // # of out packets
/* MIB II variables
*
* NOTE: atomic_t types are only guaranteed to store 24-bits; if we
* MUST have 32, then we'll need another way to perform atomic
* operations
*/
u32 unircv; // # multicast packets received
atomic_t unixmt; // # multicast packets for Tx
u32 multircv; // # multicast packets received
atomic_t multixmt; // # multicast packets for Tx
u32 brdcstrcv; // # broadcast packets received
atomic_t brdcstxmt; // # broadcast packets for Tx
u32 norcvbuf; // # Rx packets discarded
u32 noxmtbuf; // # Tx packets discarded
/* Transciever state informations. */
u8 xcvr_addr;
u32 xcvr_id;
/* Tx Statistics. */
u32 tx_uflo; // Tx Underruns
u32 collisions;
u32 excessive_collisions;
u32 first_collision;
u32 late_collisions;
u32 max_pkt_error;
u32 tx_deferred;
/* Rx Statistics. */
u32 rx_ov_flow; // Rx Over Flow
u32 length_err;
u32 alignment_err;
u32 crc_err;
u32 code_violations;
u32 other_errors;
#ifdef CONFIG_ET131X_DEBUG
u32 UnhandledInterruptsPerSec;
u32 RxDmaInterruptsPerSec;
u32 TxDmaInterruptsPerSec;
u32 WatchDogInterruptsPerSec;
#endif /* CONFIG_ET131X_DEBUG */
u32 SynchrounousIterations;
INTERRUPT_t InterruptStatus;
} CE_STATS_t, *PCE_STATS_t;
/* The private adapter structure */
struct et131x_adapter {
struct net_device *netdev;
struct pci_dev *pdev;
struct work_struct task;
/* Flags that indicate current state of the adapter */
u32 Flags;
u32 HwErrCount;
/* Configuration */
u8 PermanentAddress[ETH_ALEN];
u8 CurrentAddress[ETH_ALEN];
bool bOverrideAddress;
bool bEepromPresent;
u8 eepromData[2];
/* Spinlocks */
spinlock_t Lock;
spinlock_t TCBSendQLock;
spinlock_t TCBReadyQLock;
spinlock_t SendHWLock;
spinlock_t SendWaitLock;
spinlock_t RcvLock;
spinlock_t RcvPendLock;
spinlock_t FbrLock;
spinlock_t PHYLock;
/* Packet Filter and look ahead size */
u32 PacketFilter;
u32 ulLookAhead;
u32 uiLinkSpeed;
u32 uiDuplexMode;
u32 uiAutoNegStatus;
u8 ucLinkStatus;
/* multicast list */
u32 MCAddressCount;
u8 MCList[NIC_MAX_MCAST_LIST][ETH_ALEN];
/* MAC test */
TXMAC_TXTEST_t TxMacTest;
/* Pointer to the device's PCI register space */
ADDRESS_MAP_t __iomem *CSRAddress;
/* PCI config space info, for debug purposes only. */
u8 RevisionID;
u16 VendorID;
u16 DeviceID;
u16 SubVendorID;
u16 SubSystemID;
u32 CacheFillSize;
u16 PciXDevCtl;
u8 pci_lat_timer;
u8 pci_hdr_type;
u8 pci_bist;
u32 pci_cfg_state[64 / sizeof(u32)];
/* Registry parameters */
u8 SpeedDuplex; // speed/duplex
eFLOW_CONTROL_t RegistryFlowControl; // for 802.3x flow control
u8 RegistryWOLMatch; // Enable WOL pattern-matching
u8 RegistryWOLLink; // Link state change is independant
u8 RegistryPhyComa; // Phy Coma mode enable/disable
u32 RegistryRxMemEnd; // Size of internal rx memory
u8 RegistryMACStat; // If set, read MACSTAT, else don't
u32 RegistryVlanTag; // 802.1q Vlan TAG
u32 RegistryJumboPacket; // Max supported ethernet packet size
u32 RegistryTxNumBuffers;
u32 RegistryTxTimeInterval;
u32 RegistryRxNumBuffers;
u32 RegistryRxTimeInterval;
/* Validation helpers */
u8 RegistryPMWOL;
u8 RegistryNMIDisable;
u32 RegistryDMACache;
u32 RegistrySCGain;
u8 RegistryPhyLoopbk; // Enable Phy loopback
/* Derived from the registry: */
u8 AiForceDpx; // duplex setting
u16 AiForceSpeed; // 'Speed', user over-ride of line speed
eFLOW_CONTROL_t FlowControl; // flow control validated by the far-end
enum {
NETIF_STATUS_INVALID = 0,
NETIF_STATUS_MEDIA_CONNECT,
NETIF_STATUS_MEDIA_DISCONNECT,
NETIF_STATUS_MAX
} MediaState;
u8 DriverNoPhyAccess;
/* Minimize init-time */
bool bQueryPending;
bool bSetPending;
bool bResetPending;
struct timer_list ErrorTimer;
bool bLinkTimerActive;
MP_POWER_MGMT PoMgmt;
INTERRUPT_t CachedMaskValue;
atomic_t RcvRefCount; // Num packets not yet returned
/* Xcvr status at last poll */
MI_BMSR_t Bmsr;
/* Tx Memory Variables */
TX_RING_t TxRing;
/* Rx Memory Variables */
RX_RING_t RxRing;
/* ET1310 register Access */
JAGCORE_ACCESS_REGS JagCoreRegs;
PCI_CFG_SPACE_REGS PciCfgRegs;
/* Loopback specifics */
u8 ReplicaPhyLoopbk; // Replica Enable
u8 ReplicaPhyLoopbkPF; // Replica Enable Pass/Fail
/* Stats */
CE_STATS_t Stats;
struct net_device_stats net_stats;
struct net_device_stats net_stats_prev;
};
#define MPSendPacketsHandler MPSendPackets
#define MP_FREE_SEND_PACKET_FUN(Adapter, pMpTcb) \
et131x_free_send_packet(Adapter, pMpTcb)
#define MpSendPacketFun(Adapter, Packet) MpSendPacket(Adapter, Packet)
#endif /* __ET131X_ADAPTER_H__ */

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_config.c - Handles parsing of configuration data during
* initialization.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et131x_adapter.h"
#include "et131x_initpci.h"
#include "et131x_config.h"
#include "et1310_tx.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
/* Defines for Parameter Default/Min/Max vaules */
#define PARM_SPEED_DUPLEX_DEF 0
#define PARM_SPEED_DUPLEX_MIN 0
#define PARM_SPEED_DUPLEX_MAX 5
#define PARM_VLAN_TAG_DEF 0
#define PARM_VLAN_TAG_MIN 0
#define PARM_VLAN_TAG_MAX 4095
#define PARM_FLOW_CTL_DEF 0
#define PARM_FLOW_CTL_MIN 0
#define PARM_FLOW_CTL_MAX 3
#define PARM_WOL_LINK_DEF 3
#define PARM_WOL_LINK_MIN 0
#define PARM_WOL_LINK_MAX 3
#define PARM_WOL_MATCH_DEF 7
#define PARM_WOL_MATCH_MIN 0
#define PARM_WOL_MATCH_MAX 7
#define PARM_JUMBO_PKT_DEF 1514
#define PARM_JUMBO_PKT_MIN 1514
#define PARM_JUMBO_PKT_MAX 9216
#define PARM_PHY_COMA_DEF 0
#define PARM_PHY_COMA_MIN 0
#define PARM_PHY_COMA_MAX 1
#define PARM_RX_NUM_BUFS_DEF 4
#define PARM_RX_NUM_BUFS_MIN 1
#define PARM_RX_NUM_BUFS_MAX 64
#define PARM_RX_TIME_INT_DEF 10
#define PARM_RX_TIME_INT_MIN 2
#define PARM_RX_TIME_INT_MAX 320
#define PARM_TX_NUM_BUFS_DEF 4
#define PARM_TX_NUM_BUFS_MIN 1
#define PARM_TX_NUM_BUFS_MAX 40
#define PARM_TX_TIME_INT_DEF 40
#define PARM_TX_TIME_INT_MIN 1
#define PARM_TX_TIME_INT_MAX 140
#define PARM_RX_MEM_END_DEF 0x2bc
#define PARM_RX_MEM_END_MIN 0
#define PARM_RX_MEM_END_MAX 0x3ff
#define PARM_MAC_STAT_DEF 1
#define PARM_MAC_STAT_MIN 0
#define PARM_MAC_STAT_MAX 1
#define PARM_SC_GAIN_DEF 7
#define PARM_SC_GAIN_MIN 0
#define PARM_SC_GAIN_MAX 7
#define PARM_PM_WOL_DEF 0
#define PARM_PM_WOL_MIN 0
#define PARM_PM_WOL_MAX 1
#define PARM_NMI_DISABLE_DEF 0
#define PARM_NMI_DISABLE_MIN 0
#define PARM_NMI_DISABLE_MAX 2
#define PARM_DMA_CACHE_DEF 0
#define PARM_DMA_CACHE_MIN 0
#define PARM_DMA_CACHE_MAX 15
#define PARM_PHY_LOOPBK_DEF 0
#define PARM_PHY_LOOPBK_MIN 0
#define PARM_PHY_LOOPBK_MAX 1
#define PARM_MAC_ADDRESS_DEF { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 }
/* Module parameter for disabling NMI
* et131x_speed_set :
* Set Link speed and dublex manually (0-5) [0]
* 1 : 10Mb Half-Duplex
* 2 : 10Mb Full-Duplex
* 3 : 100Mb Half-Duplex
* 4 : 100Mb Full-Duplex
* 5 : 1000Mb Full-Duplex
* 0 : Auto Speed Auto Dublex // default
*/
static u32 et131x_nmi_disable = PARM_NMI_DISABLE_DEF;
module_param(et131x_nmi_disable, uint, 0);
MODULE_PARM_DESC(et131x_nmi_disable, "Disable NMI (0-2) [0]");
/* Module parameter for manual speed setting
* et131x_nmi_disable :
* Disable NMI (0-2) [0]
* 0 :
* 1 :
* 2 :
*/
static u32 et131x_speed_set = PARM_SPEED_DUPLEX_DEF;
module_param(et131x_speed_set, uint, 0);
MODULE_PARM_DESC(et131x_speed_set,
"Set Link speed and dublex manually (0-5) [0] \n 1 : 10Mb Half-Duplex \n 2 : 10Mb Full-Duplex \n 3 : 100Mb Half-Duplex \n 4 : 100Mb Full-Duplex \n 5 : 1000Mb Full-Duplex \n 0 : Auto Speed Auto Dublex");
/**
* et131x_config_parse
* @pAdapter: pointer to the private adapter struct
*
* Parses a configuration from some location (module parameters, for example)
* into the private adapter struct
*/
void et131x_config_parse(struct et131x_adapter *pAdapter)
{
uint8_t macAddrDef[] = PARM_MAC_ADDRESS_DEF;
DBG_ENTER(et131x_dbginfo);
/*
* The NDIS driver uses the registry to store persistent per-device
* configuration, and reads this configuration into the appropriate
* elements of the private adapter structure on initialization.
* Because Linux has no analog to the registry, use this function to
* initialize the private adapter structure with a default
* configuration.
*
* One other possibility is to use a series of module parameters which
* can be passed in by the caller when the module is initialized.
* However, this implementation does not allow for seperate
* configurations in the event multiple devices are present, and hence
* will not suffice.
*
* If another method is derived which addresses this problem, this is
* where it should be implemented.
*/
/* Set the private adapter struct with default values for the
* corresponding parameters
*/
if (et131x_speed_set != PARM_SPEED_DUPLEX_DEF) {
DBG_VERBOSE(et131x_dbginfo, "Speed set manually to : %d \n",
et131x_speed_set);
pAdapter->SpeedDuplex = et131x_speed_set;
} else {
pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
}
// pAdapter->SpeedDuplex = PARM_SPEED_DUPLEX_DEF;
pAdapter->RegistryVlanTag = PARM_VLAN_TAG_DEF;
pAdapter->RegistryFlowControl = PARM_FLOW_CTL_DEF;
pAdapter->RegistryWOLLink = PARM_WOL_LINK_DEF;
pAdapter->RegistryWOLMatch = PARM_WOL_MATCH_DEF;
pAdapter->RegistryJumboPacket = PARM_JUMBO_PKT_DEF;
pAdapter->RegistryPhyComa = PARM_PHY_COMA_DEF;
pAdapter->RegistryRxNumBuffers = PARM_RX_NUM_BUFS_DEF;
pAdapter->RegistryRxTimeInterval = PARM_RX_TIME_INT_DEF;
pAdapter->RegistryTxNumBuffers = PARM_TX_NUM_BUFS_DEF;
pAdapter->RegistryTxTimeInterval = PARM_TX_TIME_INT_DEF;
pAdapter->RegistryRxMemEnd = PARM_RX_MEM_END_DEF;
pAdapter->RegistryMACStat = PARM_MAC_STAT_DEF;
pAdapter->RegistrySCGain = PARM_SC_GAIN_DEF;
pAdapter->RegistryPMWOL = PARM_PM_WOL_DEF;
if (et131x_nmi_disable != PARM_NMI_DISABLE_DEF) {
pAdapter->RegistryNMIDisable = et131x_nmi_disable;
} else {
pAdapter->RegistryNMIDisable = PARM_NMI_DISABLE_DEF;
}
pAdapter->RegistryDMACache = PARM_DMA_CACHE_DEF;
pAdapter->RegistryPhyLoopbk = PARM_PHY_LOOPBK_DEF;
/* Set the MAC address to a default */
memcpy(pAdapter->CurrentAddress, macAddrDef, ETH_ALEN);
pAdapter->bOverrideAddress = false;
DBG_TRACE(et131x_dbginfo,
"Default MAC Address : %02x:%02x:%02x:%02x:%02x:%02x\n",
pAdapter->CurrentAddress[0], pAdapter->CurrentAddress[1],
pAdapter->CurrentAddress[2], pAdapter->CurrentAddress[3],
pAdapter->CurrentAddress[4], pAdapter->CurrentAddress[5]);
/* Decode SpeedDuplex
*
* Set up as if we are auto negotiating always and then change if we
* go into force mode
*/
pAdapter->AiForceSpeed = 0; // Auto speed
pAdapter->AiForceDpx = 0; // Auto FDX
/* If we are the 10/100 device, and gigabit is somehow requested then
* knock it down to 100 full.
*/
if ((pAdapter->DeviceID == ET131X_PCI_DEVICE_ID_FAST) &&
(pAdapter->SpeedDuplex == 5)) {
pAdapter->SpeedDuplex = 4;
}
switch (pAdapter->SpeedDuplex) {
case 1: // 10Mb Half-Duplex
pAdapter->AiForceSpeed = 10;
pAdapter->AiForceDpx = 1;
break;
case 2: // 10Mb Full-Duplex
pAdapter->AiForceSpeed = 10;
pAdapter->AiForceDpx = 2;
break;
case 3: // 100Mb Half-Duplex
pAdapter->AiForceSpeed = 100;
pAdapter->AiForceDpx = 1;
break;
case 4: // 100Mb Full-Duplex
pAdapter->AiForceSpeed = 100;
pAdapter->AiForceDpx = 2;
break;
case 5: // 1000Mb Full-Duplex
pAdapter->AiForceSpeed = 1000;
pAdapter->AiForceDpx = 2;
break;
}
DBG_LEAVE(et131x_dbginfo);
}

67
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_config.h - Defines, structs, enums, prototypes, etc. to support
* et131x_config.c
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_CONFIG_H__
#define __ET131X_CONFIG_H__
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
void et131x_config_parse(struct et131x_adapter *adapter);
#endif /* __ET131X_CONFIG_H__ */

218
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_debug.c - Routines used for debugging.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifdef CONFIG_ET131X_DEBUG
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include <linux/random.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et131x_adapter.h"
#include "et131x_netdev.h"
#include "et131x_config.h"
#include "et131x_isr.h"
#include "et1310_address_map.h"
#include "et1310_jagcore.h"
#include "et1310_tx.h"
#include "et1310_rx.h"
#include "et1310_mac.h"
/* Data for debugging facilities */
extern dbg_info_t *et131x_dbginfo;
/**
* DumpTxQueueContents - Dump out the tx queue and the shadow pointers
* @pAdapter: pointer to our adapter structure
*/
void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *pAdapter)
{
MMC_t __iomem *mmc = &pAdapter->CSRAddress->mmc;
uint32_t TxQueueAddr;
if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
for (TxQueueAddr = 0x200; TxQueueAddr < 0x3ff; TxQueueAddr++) {
MMC_SRAM_ACCESS_t sram_access;
sram_access.value = readl(&mmc->sram_access.value);
sram_access.bits.req_addr = TxQueueAddr;
sram_access.bits.req_access = 1;
writel(sram_access.value, &mmc->sram_access.value);
DBG_PRINT("Addr 0x%x, Access 0x%08x\t"
"Value 1 0x%08x, Value 2 0x%08x, "
"Value 3 0x%08x, Value 4 0x%08x, \n",
TxQueueAddr,
readl(&mmc->sram_access.value),
readl(&mmc->sram_word1),
readl(&mmc->sram_word2),
readl(&mmc->sram_word3),
readl(&mmc->sram_word4));
}
DBG_PRINT("Shadow Pointers 0x%08x\n",
readl(&pAdapter->CSRAddress->txmac.shadow_ptr.value));
}
}
/**
* DumpDeviceBlock
* @pAdapter: pointer to our adapter
*
* Dumps the first 64 regs of each block of the et-1310 (each block is
* mapped to a new page, each page is 4096 bytes).
*/
#define NUM_BLOCKS 8
void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *pAdapter,
uint32_t Block)
{
uint32_t Address1, Address2;
uint32_t __iomem *BigDevicePointer =
(uint32_t __iomem *) pAdapter->CSRAddress;
const char *BlockNames[NUM_BLOCKS] = {
"Global", "Tx DMA", "Rx DMA", "Tx MAC",
"Rx MAC", "MAC", "MAC Stat", "MMC"
};
/* Output the debug counters to the debug terminal */
if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
DBG_PRINT("%s block\n", BlockNames[Block]);
BigDevicePointer += Block * 1024;
for (Address1 = 0; Address1 < 8; Address1++) {
for (Address2 = 0; Address2 < 8; Address2++) {
if (Block == 0 &&
(Address1 * 8 + Address2) == 6) {
DBG_PRINT(" ISR , ");
} else {
DBG_PRINT("0x%08x, ",
readl(BigDevicePointer++));
}
}
DBG_PRINT("\n");
}
DBG_PRINT("\n");
}
}
/**
* DumpDeviceReg
* @pAdapter: pointer to our adapter
*
* Dumps the first 64 regs of each block of the et-1310 (each block is
* mapped to a new page, each page is 4096 bytes).
*/
void DumpDeviceReg(int dbgLvl, struct et131x_adapter *pAdapter)
{
uint32_t Address1, Address2;
uint32_t Block;
uint32_t __iomem *BigDevicePointer =
(uint32_t __iomem *) pAdapter->CSRAddress;
uint32_t __iomem *Pointer;
const char *BlockNames[NUM_BLOCKS] = {
"Global", "Tx DMA", "Rx DMA", "Tx MAC",
"Rx MAC", "MAC", "MAC Stat", "MMC"
};
/* Output the debug counters to the debug terminal */
if (DBG_FLAGS(et131x_dbginfo) & dbgLvl) {
for (Block = 0; Block < NUM_BLOCKS; Block++) {
DBG_PRINT("%s block\n", BlockNames[Block]);
Pointer = BigDevicePointer + (Block * 1024);
for (Address1 = 0; Address1 < 8; Address1++) {
for (Address2 = 0; Address2 < 8; Address2++) {
DBG_PRINT("0x%08x, ",
readl(Pointer++));
}
DBG_PRINT("\n");
}
DBG_PRINT("\n");
}
}
}
#endif // CONFIG_ET131X_DEBUG

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_debug.h - Defines, structs, enums, prototypes, etc. used for
* outputting debug messages to the system logging facility
* (ksyslogd)
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_DBG_H__
#define __ET131X_DBG_H__
/* Define Masks for debugging types/levels */
#define DBG_ERROR_ON 0x00000001L
#define DBG_WARNING_ON 0x00000002L
#define DBG_NOTICE_ON 0x00000004L
#define DBG_TRACE_ON 0x00000008L
#define DBG_VERBOSE_ON 0x00000010L
#define DBG_PARAM_ON 0x00000020L
#define DBG_BREAK_ON 0x00000040L
#define DBG_RX_ON 0x00000100L
#define DBG_TX_ON 0x00000200L
#ifdef CONFIG_ET131X_DEBUG
/*
* Set the level of debugging if not done with a preprocessor define. See
* et131x_main.c, function et131x_init_module() for how the debug level
* translates into the types of messages displayed.
*/
#ifndef DBG_LVL
#define DBG_LVL 3
#endif /* DBG_LVL */
#define DBG_DEFAULTS (DBG_ERROR_ON | DBG_WARNING_ON | DBG_BREAK_ON )
#define DBG_FLAGS(A) (A)->dbgFlags
#define DBG_NAME(A) (A)->dbgName
#define DBG_LEVEL(A) (A)->dbgLevel
#ifndef DBG_PRINT
#define DBG_PRINT(S...) printk(KERN_DEBUG S)
#endif /* DBG_PRINT */
#ifndef DBG_PRINTC
#define DBG_PRINTC(S...) printk(S)
#endif /* DBG_PRINTC */
#ifndef DBG_TRAP
#define DBG_TRAP {} /* BUG() */
#endif /* DBG_TRAP */
#define _ENTER_STR ">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>"
#define _LEAVE_STR "<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<"
#define _DBG_ENTER(A) printk(KERN_DEBUG "%s:%.*s:%s\n", DBG_NAME(A), \
++DBG_LEVEL(A), _ENTER_STR, __func__)
#define _DBG_LEAVE(A) printk(KERN_DEBUG "%s:%.*s:%s\n", DBG_NAME(A), \
DBG_LEVEL(A)--, _LEAVE_STR, __func__)
#define DBG_ENTER(A) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
_DBG_ENTER(A);}
#define DBG_LEAVE(A) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
_DBG_LEAVE(A);}
#define DBG_PARAM(A,N,F,S...) {if (DBG_FLAGS(A) & DBG_PARAM_ON) \
DBG_PRINT(" %s -- "F"\n",N,S);}
#define DBG_ERROR(A,S...) \
if (DBG_FLAGS(A) & DBG_ERROR_ON) { \
DBG_PRINT("%s:ERROR:%s ",DBG_NAME(A), __func__); \
DBG_PRINTC(S); \
DBG_TRAP; \
}
#define DBG_WARNING(A,S...) {if (DBG_FLAGS(A) & DBG_WARNING_ON) \
{DBG_PRINT("%s:WARNING:%s ",DBG_NAME(A),__func__);DBG_PRINTC(S);}}
#define DBG_NOTICE(A,S...) {if (DBG_FLAGS(A) & DBG_NOTICE_ON) \
{DBG_PRINT("%s:NOTICE:%s ",DBG_NAME(A),__func__);DBG_PRINTC(S);}}
#define DBG_TRACE(A,S...) {if (DBG_FLAGS(A) & DBG_TRACE_ON) \
{DBG_PRINT("%s:TRACE:%s ",DBG_NAME(A), __func__);DBG_PRINTC(S);}}
#define DBG_VERBOSE(A,S...) {if (DBG_FLAGS(A) & DBG_VERBOSE_ON) \
{DBG_PRINT("%s:VERBOSE:%s ",DBG_NAME(A), __func__);DBG_PRINTC(S);}}
#define DBG_RX(A,S...) {if (DBG_FLAGS(A) & DBG_RX_ON) \
{DBG_PRINT(S);}}
#define DBG_RX_ENTER(A) {if (DBG_FLAGS(A) & DBG_RX_ON) \
_DBG_ENTER(A);}
#define DBG_RX_LEAVE(A) {if (DBG_FLAGS(A) & DBG_RX_ON) \
_DBG_LEAVE(A);}
#define DBG_TX(A,S...) {if (DBG_FLAGS(A) & DBG_TX_ON) \
{DBG_PRINT(S);}}
#define DBG_TX_ENTER(A) {if (DBG_FLAGS(A) & DBG_TX_ON) \
_DBG_ENTER(A);}
#define DBG_TX_LEAVE(A) {if (DBG_FLAGS(A) & DBG_TX_ON) \
_DBG_LEAVE(A);}
#define DBG_ASSERT(C) {if (!(C)) \
{DBG_PRINT("ASSERT(%s) -- %s#%d (%s)\n", \
#C,__FILE__,__LINE__,__func__); \
DBG_TRAP;}}
#define STATIC
typedef struct {
char *dbgName;
int dbgLevel;
unsigned long dbgFlags;
} dbg_info_t;
#else /* CONFIG_ET131X_DEBUG */
#define DBG_DEFN
#define DBG_TRAP
#define DBG_PRINT(S...)
#define DBG_ENTER(A)
#define DBG_LEAVE(A)
#define DBG_PARAM(A,N,F,S...)
#define DBG_ERROR(A,S...)
#define DBG_WARNING(A,S...)
#define DBG_NOTICE(A,S...)
#define DBG_TRACE(A,S...)
#define DBG_VERBOSE(A,S...)
#define DBG_RX(A,S...)
#define DBG_RX_ENTER(A)
#define DBG_RX_LEAVE(A)
#define DBG_TX(A,S...)
#define DBG_TX_ENTER(A)
#define DBG_TX_LEAVE(A)
#define DBG_ASSERT(C)
#define STATIC static
#endif /* CONFIG_ET131X_DEBUG */
/* Forward declaration of the private adapter structure */
struct et131x_adapter;
void DumpTxQueueContents(int dbgLvl, struct et131x_adapter *adapter);
void DumpDeviceBlock(int dbgLvl, struct et131x_adapter *adapter,
unsigned int Block);
void DumpDeviceReg(int dbgLvl, struct et131x_adapter *adapter);
#endif /* __ET131X_DBG_H__ */

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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_defs.h - Defines, structs, enums, prototypes, etc. to assist with OS
* compatibility
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_DEFS_H__
#define __ET131X_DEFS_H__
/* Packet and header sizes */
#define NIC_MIN_PACKET_SIZE 60
#define NIC_HEADER_SIZE ETH_HLEN /* 14 */
/* Multicast list size */
#define NIC_MAX_MCAST_LIST 128
/* Supported Filters */
#define ET131X_PACKET_TYPE_DIRECTED 0x0001
#define ET131X_PACKET_TYPE_MULTICAST 0x0002
#define ET131X_PACKET_TYPE_BROADCAST 0x0004
#define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
#define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
/* Tx Timeout */
#define ET131X_TX_TIMEOUT (1 * HZ)
#define NIC_SEND_HANG_THRESHOLD 0
/* MP_TCB flags */
#define fMP_DEST_MULTI 0x00000001
#define fMP_DEST_BROAD 0x00000002
/* MP_ADAPTER flags */
#define fMP_ADAPTER_RECV_LOOKASIDE 0x00000004
#define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
#define fMP_ADAPTER_SECONDARY 0x00000010
/* MP_SHARED flags */
#define fMP_ADAPTER_SHUTDOWN 0x00100000
#define fMP_ADAPTER_LOWER_POWER 0x00200000
#define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
#define fMP_ADAPTER_RESET_IN_PROGRESS 0x01000000
#define fMP_ADAPTER_NO_CABLE 0x02000000
#define fMP_ADAPTER_HARDWARE_ERROR 0x04000000
#define fMP_ADAPTER_REMOVE_IN_PROGRESS 0x08000000
#define fMP_ADAPTER_HALT_IN_PROGRESS 0x10000000
#define fMP_ADAPTER_LINK_DETECTION 0x20000000
#define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
#define fMP_ADAPTER_NOT_READY_MASK 0x3ff00000
/* Some offsets in PCI config space that are actually used. */
#define ET1310_PCI_PM_CAPABILITY 0x40
#define ET1310_PCI_PM_CSR 0x44
#define ET1310_PCI_MAX_PYLD 0x4C
#define ET1310_PCI_DEV_CTRL 0x50
#define ET1310_PCI_DEV_STAT 0x52
#define ET1310_NMI_DISABLE 0x61
#define ET1310_PCI_MAC_ADDRESS 0xA4
#define ET1310_PCI_EEPROM_STATUS 0xB2
#define ET1310_PCI_PHY_INDEX_REG 0xB4
#define ET1310_PCI_ACK_NACK 0xC0
#define ET1310_PCI_REPLAY 0xC2
#define ET1310_PCI_L0L1LATENCY 0xCF
#define ET1310_PCI_SEL_PHY_CTRL 0xE4
#define ET1310_PCI_ADVANCED_ERR 0x100
/* PCI Vendor/Product IDs */
#define ET131X_PCI_VENDOR_ID 0x11C1 // Agere Systems
#define ET131X_PCI_DEVICE_ID_GIG 0xED00 // ET1310 1000 Base-T
#define ET131X_PCI_DEVICE_ID_FAST 0xED01 // ET1310 100 Base-T
/* Define order of magnitude converter */
#define NANO_IN_A_MICRO 1000
#endif /* __ET131X_DEFS_H__ */

1046
drivers/staging/et131x/et131x_initpci.c Normal file
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_initpci.h - Header which includes common data and function prototypes
* related to the driver's PCI (and PCI Express) information.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_INITPCI_H__
#define __ET131X_INITPCI_H__
/* Function Prototypes */
void et131x_align_allocated_memory(struct et131x_adapter *adapter,
u64 *phys_addr,
u64 *offset, u64 mask);
int et131x_adapter_setup(struct et131x_adapter *adapter);
int et131x_adapter_memory_alloc(struct et131x_adapter *adapter);
void et131x_adapter_memory_free(struct et131x_adapter *adapter);
void et131x_setup_hardware_properties(struct et131x_adapter *adapter);
void et131x_soft_reset(struct et131x_adapter *adapter);
#endif /* __ET131X_INITPCI_H__ */

488
drivers/staging/et131x/et131x_isr.c Normal file
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@ -0,0 +1,488 @@
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_isr.c - File which contains the ISR, ISR handler, and related routines
* for processing interrupts from the device.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_mac.h"
#include "et131x_adapter.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
/**
* et131x_isr - The Interrupt Service Routine for the driver.
* @irq: the IRQ on which the interrupt was received.
* @dev_id: device-specific info (here a pointer to a net_device struct)
*
* Returns a value indicating if the interrupt was handled.
*/
irqreturn_t et131x_isr(int irq, void *dev_id)
{
bool handled = true;
struct net_device *netdev = (struct net_device *)dev_id;
struct et131x_adapter *adapter = NULL;
INTERRUPT_t status;
if (netdev == NULL || !netif_device_present(netdev)) {
DBG_WARNING(et131x_dbginfo,
"No net_device struct or device not present\n");
handled = false;
goto out;
}
adapter = netdev_priv(netdev);
/* If the adapter is in low power state, then it should not
* recognize any interrupt
*/
/* Disable Device Interrupts */
et131x_disable_interrupts(adapter);
/* Get a copy of the value in the interrupt status register
* so we can process the interrupting section
*/
status.value = readl(&adapter->CSRAddress->global.int_status.value);
if (adapter->FlowControl == TxOnly ||
adapter->FlowControl == Both) {
status.value &= ~INT_MASK_ENABLE;
} else {
status.value &= ~INT_MASK_ENABLE_NO_FLOW;
}
/* Make sure this is our interrupt */
if (!status.value) {
#ifdef CONFIG_ET131X_DEBUG
adapter->Stats.UnhandledInterruptsPerSec++;
#endif
handled = false;
DBG_VERBOSE(et131x_dbginfo, "NOT OUR INTERRUPT\n");
et131x_enable_interrupts(adapter);
goto out;
}
/* This is our interrupt, so process accordingly */
#ifdef CONFIG_ET131X_DEBUG
if (status.bits.rxdma_xfr_done) {
adapter->Stats.RxDmaInterruptsPerSec++;
}
if (status.bits.txdma_isr) {
adapter->Stats.TxDmaInterruptsPerSec++;
}
#endif
if (status.bits.watchdog_interrupt) {
PMP_TCB pMpTcb = adapter->TxRing.CurrSendHead;
if (pMpTcb) {
if (++pMpTcb->PacketStaleCount > 1) {
status.bits.txdma_isr = 1;
}
}
if (adapter->RxRing.UnfinishedReceives) {
status.bits.rxdma_xfr_done = 1;
} else if (pMpTcb == NULL) {
writel(0, &adapter->CSRAddress->global.watchdog_timer);
}
status.bits.watchdog_interrupt = 0;
#ifdef CONFIG_ET131X_DEBUG
adapter->Stats.WatchDogInterruptsPerSec++;
#endif
}
if (status.value == 0) {
/* This interrupt has in some way been "handled" by
* the ISR. Either it was a spurious Rx interrupt, or
* it was a Tx interrupt that has been filtered by
* the ISR.
*/
et131x_enable_interrupts(adapter);
goto out;
}
/* We need to save the interrupt status value for use in our
* DPC. We will clear the software copy of that in that
* routine.
*/
adapter->Stats.InterruptStatus = status;
/* Schedule the ISR handler as a bottom-half task in the
* kernel's tq_immediate queue, and mark the queue for
* execution
*/
schedule_work(&adapter->task);
out:
return IRQ_RETVAL(handled);
}
/**
* et131x_isr_handler - The ISR handler
* @p_adapter, a pointer to the device's private adapter structure
*
* scheduled to run in a deferred context by the ISR. This is where the ISR's
* work actually gets done.
*/
void et131x_isr_handler(struct work_struct *work)
{
struct et131x_adapter *pAdapter =
container_of(work, struct et131x_adapter, task);
INTERRUPT_t GlobStatus = pAdapter->Stats.InterruptStatus;
ADDRESS_MAP_t __iomem *iomem = pAdapter->CSRAddress;
/*
* These first two are by far the most common. Once handled, we clear
* their two bits in the status word. If the word is now zero, we
* exit.
*/
/* Handle all the completed Transmit interrupts */
if (GlobStatus.bits.txdma_isr) {
DBG_TX(et131x_dbginfo, "TXDMA_ISR interrupt\n");
et131x_handle_send_interrupt(pAdapter);
}
/* Handle all the completed Receives interrupts */
if (GlobStatus.bits.rxdma_xfr_done) {
DBG_RX(et131x_dbginfo, "RXDMA_XFR_DONE interrupt\n");
et131x_handle_recv_interrupt(pAdapter);
}
GlobStatus.value &= 0xffffffd7;
if (GlobStatus.value) {
/* Handle the TXDMA Error interrupt */
if (GlobStatus.bits.txdma_err) {
TXDMA_ERROR_t TxDmaErr;
/* Following read also clears the register (COR) */
TxDmaErr.value = readl(&iomem->txdma.TxDmaError.value);
DBG_WARNING(et131x_dbginfo,
"TXDMA_ERR interrupt, error = %d\n",
TxDmaErr.value);
}
/* Handle Free Buffer Ring 0 and 1 Low interrupt */
if (GlobStatus.bits.rxdma_fb_ring0_low ||
GlobStatus.bits.rxdma_fb_ring1_low) {
/*
* This indicates the number of unused buffers in
* RXDMA free buffer ring 0 is <= the limit you
* programmed. Free buffer resources need to be
* returned. Free buffers are consumed as packets
* are passed from the network to the host. The host
* becomes aware of the packets from the contents of
* the packet status ring. This ring is queried when
* the packet done interrupt occurs. Packets are then
* passed to the OS. When the OS is done with the
* packets the resources can be returned to the
* ET1310 for re-use. This interrupt is one method of
* returning resources.
*/
DBG_WARNING(et131x_dbginfo,
"RXDMA_FB_RING0_LOW or "
"RXDMA_FB_RING1_LOW interrupt\n");
/* If the user has flow control on, then we will
* send a pause packet, otherwise just exit
*/
if (pAdapter->FlowControl == TxOnly ||
pAdapter->FlowControl == Both) {
PM_CSR_t pm_csr;
/* Tell the device to send a pause packet via
* the back pressure register
*/
pm_csr.value = readl(&iomem->global.pm_csr.value);
if (pm_csr.bits.pm_phy_sw_coma == 0) {
TXMAC_BP_CTRL_t bp_ctrl = { 0 };
bp_ctrl.bits.bp_req = 1;
bp_ctrl.bits.bp_xonxoff = 1;
writel(bp_ctrl.value,
&iomem->txmac.bp_ctrl.value);
}
}
}
/* Handle Packet Status Ring Low Interrupt */
if (GlobStatus.bits.rxdma_pkt_stat_ring_low) {
DBG_WARNING(et131x_dbginfo,
"RXDMA_PKT_STAT_RING_LOW interrupt\n");
/*
* Same idea as with the two Free Buffer Rings.
* Packets going from the network to the host each
* consume a free buffer resource and a packet status
* resource. These resoures are passed to the OS.
* When the OS is done with the resources, they need
* to be returned to the ET1310. This is one method
* of returning the resources.
*/
}
/* Handle RXDMA Error Interrupt */
if (GlobStatus.bits.rxdma_err) {
/*
* The rxdma_error interrupt is sent when a time-out
* on a request issued by the JAGCore has occurred or
* a completion is returned with an un-successful
* status. In both cases the request is considered
* complete. The JAGCore will automatically re-try the
* request in question. Normally information on events
* like these are sent to the host using the "Advanced
* Error Reporting" capability. This interrupt is
* another way of getting similar information. The
* only thing required is to clear the interrupt by
* reading the ISR in the global resources. The
* JAGCore will do a re-try on the request. Normally
* you should never see this interrupt. If you start
* to see this interrupt occurring frequently then
* something bad has occurred. A reset might be the
* thing to do.
*/
// TRAP();
pAdapter->TxMacTest.value =
readl(&iomem->txmac.tx_test.value);
DBG_WARNING(et131x_dbginfo,
"RxDMA_ERR interrupt, error %x\n",
pAdapter->TxMacTest.value);
}
/* Handle the Wake on LAN Event */
if (GlobStatus.bits.wake_on_lan) {
/*
* This is a secondary interrupt for wake on LAN.
* The driver should never see this, if it does,
* something serious is wrong. We will TRAP the
* message when we are in DBG mode, otherwise we
* will ignore it.
*/
DBG_ERROR(et131x_dbginfo, "WAKE_ON_LAN interrupt\n");
}
/* Handle the PHY interrupt */
if (GlobStatus.bits.phy_interrupt) {
PM_CSR_t pm_csr;
MI_BMSR_t BmsrInts, BmsrData;
MI_ISR_t myIsr;
DBG_VERBOSE(et131x_dbginfo, "PHY interrupt\n");
/* If we are in coma mode when we get this interrupt,
* we need to disable it.
*/
pm_csr.value = readl(&iomem->global.pm_csr.value);
if (pm_csr.bits.pm_phy_sw_coma == 1) {
/*
* Check to see if we are in coma mode and if
* so, disable it because we will not be able
* to read PHY values until we are out.
*/
DBG_VERBOSE(et131x_dbginfo,
"Device is in COMA mode, "
"need to wake up\n");
DisablePhyComa(pAdapter);
}
/* Read the PHY ISR to clear the reason for the
* interrupt.
*/
MiRead(pAdapter, (uint8_t) offsetof(MI_REGS_t, isr),
&myIsr.value);
if (!pAdapter->ReplicaPhyLoopbk) {
MiRead(pAdapter,
(uint8_t) offsetof(MI_REGS_t, bmsr),
&BmsrData.value);
BmsrInts.value =
pAdapter->Bmsr.value ^ BmsrData.value;
pAdapter->Bmsr.value = BmsrData.value;
DBG_VERBOSE(et131x_dbginfo,
"Bmsr.value = 0x%04x,"
"Bmsr_ints.value = 0x%04x\n",
BmsrData.value, BmsrInts.value);
/* Do all the cable in / cable out stuff */
et131x_Mii_check(pAdapter, BmsrData, BmsrInts);
}
}
/* Let's move on to the TxMac */
if (GlobStatus.bits.txmac_interrupt) {
pAdapter->TxRing.TxMacErr.value =
readl(&iomem->txmac.err.value);
/*
* When any of the errors occur and TXMAC generates
* an interrupt to report these errors, it usually
* means that TXMAC has detected an error in the data
* stream retrieved from the on-chip Tx Q. All of
* these errors are catastrophic and TXMAC won't be
* able to recover data when these errors occur. In
* a nutshell, the whole Tx path will have to be reset
* and re-configured afterwards.
*/
DBG_WARNING(et131x_dbginfo,
"TXMAC interrupt, error 0x%08x\n",
pAdapter->TxRing.TxMacErr.value);
/* If we are debugging, we want to see this error,
* otherwise we just want the device to be reset and
* continue
*/
//DBG_TRAP();
}
/* Handle RXMAC Interrupt */
if (GlobStatus.bits.rxmac_interrupt) {
/*
* These interrupts are catastrophic to the device,
* what we need to do is disable the interrupts and
* set the flag to cause us to reset so we can solve
* this issue.
*/
// MP_SET_FLAG( pAdapter, fMP_ADAPTER_HARDWARE_ERROR );
DBG_WARNING(et131x_dbginfo,
"RXMAC interrupt, error 0x%08x. Requesting reset\n",
readl(&iomem->rxmac.err_reg.value));
DBG_WARNING(et131x_dbginfo,
"Enable 0x%08x, Diag 0x%08x\n",
readl(&iomem->rxmac.ctrl.value),
readl(&iomem->rxmac.rxq_diag.value));
/*
* If we are debugging, we want to see this error,
* otherwise we just want the device to be reset and
* continue
*/
// TRAP();
}
/* Handle MAC_STAT Interrupt */
if (GlobStatus.bits.mac_stat_interrupt) {
/*
* This means at least one of the un-masked counters
* in the MAC_STAT block has rolled over. Use this
* to maintain the top, software managed bits of the
* counter(s).
*/
DBG_VERBOSE(et131x_dbginfo, "MAC_STAT interrupt\n");
HandleMacStatInterrupt(pAdapter);
}
/* Handle SLV Timeout Interrupt */
if (GlobStatus.bits.slv_timeout) {
/*
* This means a timeout has occured on a read or
* write request to one of the JAGCore registers. The
* Global Resources block has terminated the request
* and on a read request, returned a "fake" value.
* The most likely reasons are: Bad Address or the
* addressed module is in a power-down state and
* can't respond.
*/
DBG_VERBOSE(et131x_dbginfo, "SLV_TIMEOUT interrupt\n");
}
}
if (pAdapter->PoMgmt.PowerState == NdisDeviceStateD0) {
et131x_enable_interrupts(pAdapter);
}
}

65
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_isr.h - Defines, structs, enums, prototypes, etc. pertaining to the
* ISR processing code.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_ISR_H__
#define __ET131X_ISR_H__
irqreturn_t et131x_isr(int irq, void *dev_id);
void et131x_isr_handler(struct work_struct *work);
#endif /* __ET131X_ISR_H__ */

856
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/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_netdev.c - Routines and data required by all Linux network devices.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#include "et131x_version.h"
#include "et131x_debug.h"
#include "et131x_defs.h"
#include <linux/init.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/ptrace.h>
#include <linux/slab.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/timer.h>
#include <linux/interrupt.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/bitops.h>
#include <linux/mii.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/skbuff.h>
#include <linux/if_arp.h>
#include <linux/ioport.h>
#include "et1310_phy.h"
#include "et1310_pm.h"
#include "et1310_jagcore.h"
#include "et1310_mac.h"
#include "et1310_tx.h"
#include "et131x_adapter.h"
#include "et131x_isr.h"
#include "et131x_initpci.h"
/* Data for debugging facilities */
#ifdef CONFIG_ET131X_DEBUG
extern dbg_info_t *et131x_dbginfo;
#endif /* CONFIG_ET131X_DEBUG */
struct net_device_stats *et131x_stats(struct net_device *netdev);
int et131x_open(struct net_device *netdev);
int et131x_close(struct net_device *netdev);
int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd);
void et131x_multicast(struct net_device *netdev);
int et131x_tx(struct sk_buff *skb, struct net_device *netdev);
void et131x_tx_timeout(struct net_device *netdev);
int et131x_change_mtu(struct net_device *netdev, int new_mtu);
int et131x_set_mac_addr(struct net_device *netdev, void *new_mac);
void et131x_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp);
void et131x_vlan_rx_add_vid(struct net_device *netdev, uint16_t vid);
void et131x_vlan_rx_kill_vid(struct net_device *netdev, uint16_t vid);
/**
* et131x_device_alloc
*
* Returns pointer to the allocated and initialized net_device struct for
* this device.
*
* Create instances of net_device and wl_private for the new adapter and
* register the device's entry points in the net_device structure.
*/
struct net_device *et131x_device_alloc(void)
{
struct net_device *netdev;
DBG_ENTER(et131x_dbginfo);
/* Alloc net_device and adapter structs */
netdev = alloc_etherdev(sizeof(struct et131x_adapter));
if (netdev == NULL) {
DBG_ERROR(et131x_dbginfo,
"Alloc of net_device struct failed\n");
DBG_LEAVE(et131x_dbginfo);
return NULL;
}
/* Setup the function registration table (and other data) for a
* net_device
*/
//netdev->init = &et131x_init;
//netdev->set_config = &et131x_config;
netdev->get_stats = &et131x_stats;
netdev->open = &et131x_open;
netdev->stop = &et131x_close;
netdev->do_ioctl = &et131x_ioctl;
netdev->set_multicast_list = &et131x_multicast;
netdev->hard_start_xmit = &et131x_tx;
netdev->tx_timeout = &et131x_tx_timeout;
netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
netdev->change_mtu = &et131x_change_mtu;
netdev->set_mac_address = &et131x_set_mac_addr;
//netdev->ethtool_ops = &et131x_ethtool_ops;
// Poll?
//netdev->poll = &et131x_poll;
//netdev->poll_controller = &et131x_poll_controller;
DBG_LEAVE(et131x_dbginfo);
return netdev;
}
/**
* et131x_stats - Return the current device statistics.
* @netdev: device whose stats are being queried
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
struct net_device_stats *et131x_stats(struct net_device *netdev)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
struct net_device_stats *stats = &adapter->net_stats;
CE_STATS_t *devstat = &adapter->Stats;
DBG_ENTER(et131x_dbginfo);
stats->rx_packets = devstat->ipackets;
stats->tx_packets = devstat->opackets;
stats->rx_errors = devstat->length_err + devstat->alignment_err +
devstat->crc_err + devstat->code_violations + devstat->other_errors;
stats->tx_errors = devstat->max_pkt_error;
stats->multicast = devstat->multircv;
stats->collisions = devstat->collisions;
stats->rx_length_errors = devstat->length_err;
stats->rx_over_errors = devstat->rx_ov_flow;
stats->rx_crc_errors = devstat->crc_err;
// NOTE: These stats don't have corresponding values in CE_STATS, so we're
// going to have to update these directly from within the TX/RX code
//stats->rx_bytes = 20; //devstat->;
//stats->tx_bytes = 20; //devstat->;
//stats->rx_dropped = devstat->;
//stats->tx_dropped = devstat->;
// NOTE: Not used, can't find analogous statistics
//stats->rx_frame_errors = devstat->;
//stats->rx_fifo_errors = devstat->;
//stats->rx_missed_errors = devstat->;
//stats->tx_aborted_errors = devstat->;
//stats->tx_carrier_errors = devstat->;
//stats->tx_fifo_errors = devstat->;
//stats->tx_heartbeat_errors = devstat->;
//stats->tx_window_errors = devstat->;
DBG_LEAVE(et131x_dbginfo);
return stats;
}
/**
* et131x_open - Open the device for use.
* @netdev: device to be opened
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_open(struct net_device *netdev)
{
int result = 0;
struct et131x_adapter *adapter = netdev_priv(netdev);
DBG_ENTER(et131x_dbginfo);
/* Start the timer to track NIC errors */
add_timer(&adapter->ErrorTimer);
/* Register our ISR */
DBG_TRACE(et131x_dbginfo, "Registering ISR...\n");
result =
request_irq(netdev->irq, et131x_isr, IRQF_SHARED, netdev->name,
netdev);
if (result) {
DBG_ERROR(et131x_dbginfo, "Could not register ISR\n");
DBG_LEAVE(et131x_dbginfo);
return result;
}
/* Enable the Tx and Rx DMA engines (if not already enabled) */
et131x_rx_dma_enable(adapter);
et131x_tx_dma_enable(adapter);
/* Enable device interrupts */
et131x_enable_interrupts(adapter);
MP_SET_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE);
/* We're ready to move some data, so start the queue */
netif_start_queue(netdev);
DBG_LEAVE(et131x_dbginfo);
return result;
}
/**
* et131x_close - Close the device
* @netdev: device to be closed
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_close(struct net_device *netdev)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
DBG_ENTER(et131x_dbginfo);
/* First thing is to stop the queue */
netif_stop_queue(netdev);
/* Stop the Tx and Rx DMA engines */
et131x_rx_dma_disable(adapter);
et131x_tx_dma_disable(adapter);
/* Disable device interrupts */
et131x_disable_interrupts(adapter);
/* Deregistering ISR */
MP_CLEAR_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE);
DBG_TRACE(et131x_dbginfo, "Deregistering ISR...\n");
free_irq(netdev->irq, netdev);
/* Stop the error timer */
del_timer_sync(&adapter->ErrorTimer);
DBG_LEAVE(et131x_dbginfo);
return 0;
}
/**
* et131x_ioctl_mii - The function which handles MII IOCTLs
* @netdev: device on which the query is being made
* @reqbuf: the request-specific data buffer
* @cmd: the command request code
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_ioctl_mii(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
{
int status = 0;
struct et131x_adapter *pAdapter = netdev_priv(netdev);
struct mii_ioctl_data *data = if_mii(reqbuf);
DBG_ENTER(et131x_dbginfo);
switch (cmd) {
case SIOCGMIIPHY:
DBG_VERBOSE(et131x_dbginfo, "SIOCGMIIPHY\n");
data->phy_id = pAdapter->Stats.xcvr_addr;
break;
case SIOCGMIIREG:
DBG_VERBOSE(et131x_dbginfo, "SIOCGMIIREG\n");
if (!capable(CAP_NET_ADMIN)) {
status = -EPERM;
} else {
status = MiRead(pAdapter,
data->reg_num, &data->val_out);
}
break;
case SIOCSMIIREG:
DBG_VERBOSE(et131x_dbginfo, "SIOCSMIIREG\n");
if (!capable(CAP_NET_ADMIN)) {
status = -EPERM;
} else {
status = MiWrite(pAdapter, data->reg_num,
data->val_in);
}
break;
default:
status = -EOPNOTSUPP;
}
DBG_LEAVE(et131x_dbginfo);
return status;
}
/**
* et131x_ioctl - The I/O Control handler for the driver
* @netdev: device on which the control request is being made
* @reqbuf: a pointer to the IOCTL request buffer
* @cmd: the IOCTL command code
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, int cmd)
{
int status = 0;
DBG_ENTER(et131x_dbginfo);
switch (cmd) {
case SIOCGMIIPHY:
case SIOCGMIIREG:
case SIOCSMIIREG:
status = et131x_ioctl_mii(netdev, reqbuf, cmd);
break;
default:
DBG_WARNING(et131x_dbginfo, "Unhandled IOCTL Code: 0x%04x\n",
cmd);
status = -EOPNOTSUPP;
}
DBG_LEAVE(et131x_dbginfo);
return status;
}
/**
* et131x_set_packet_filter - Configures the Rx Packet filtering on the device
* @adapter: pointer to our private adapter structure
*
* Returns 0 on success, errno on failure
*/
int et131x_set_packet_filter(struct et131x_adapter *adapter)
{
int status = 0;
uint32_t filter = adapter->PacketFilter;
RXMAC_CTRL_t ctrl;
RXMAC_PF_CTRL_t pf_ctrl;
DBG_ENTER(et131x_dbginfo);
ctrl.value = readl(&adapter->CSRAddress->rxmac.ctrl.value);
pf_ctrl.value = readl(&adapter->CSRAddress->rxmac.pf_ctrl.value);
/* Default to disabled packet filtering. Enable it in the individual
* case statements that require the device to filter something
*/
ctrl.bits.pkt_filter_disable = 1;
/* Set us to be in promiscuous mode so we receive everything, this
* is also true when we get a packet filter of 0
*/
if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) {
pf_ctrl.bits.filter_broad_en = 0;
pf_ctrl.bits.filter_multi_en = 0;
pf_ctrl.bits.filter_uni_en = 0;
} else {
/*
* Set us up with Multicast packet filtering. Three cases are
* possible - (1) we have a multi-cast list, (2) we receive ALL
* multicast entries or (3) we receive none.
*/
if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) {
DBG_VERBOSE(et131x_dbginfo,
"Multicast filtering OFF (Rx ALL MULTICAST)\n");
pf_ctrl.bits.filter_multi_en = 0;
} else {
DBG_VERBOSE(et131x_dbginfo, "Multicast filtering ON\n");
SetupDeviceForMulticast(adapter);
pf_ctrl.bits.filter_multi_en = 1;
ctrl.bits.pkt_filter_disable = 0;
}
/* Set us up with Unicast packet filtering */
if (filter & ET131X_PACKET_TYPE_DIRECTED) {
DBG_VERBOSE(et131x_dbginfo, "Unicast Filtering ON\n");
SetupDeviceForUnicast(adapter);
pf_ctrl.bits.filter_uni_en = 1;
ctrl.bits.pkt_filter_disable = 0;
}
/* Set us up with Broadcast packet filtering */
if (filter & ET131X_PACKET_TYPE_BROADCAST) {
DBG_VERBOSE(et131x_dbginfo, "Broadcast Filtering ON\n");
pf_ctrl.bits.filter_broad_en = 1;
ctrl.bits.pkt_filter_disable = 0;
} else {
DBG_VERBOSE(et131x_dbginfo,
"Broadcast Filtering OFF\n");
pf_ctrl.bits.filter_broad_en = 0;
}
/* Setup the receive mac configuration registers - Packet
* Filter control + the enable / disable for packet filter
* in the control reg.
*/
writel(pf_ctrl.value,
&adapter->CSRAddress->rxmac.pf_ctrl.value);
writel(ctrl.value, &adapter->CSRAddress->rxmac.ctrl.value);
}
DBG_LEAVE(et131x_dbginfo);
return status;
}
/**
* et131x_multicast - The handler to configure multicasting on the interface
* @netdev: a pointer to a net_device struct representing the device
*/
void et131x_multicast(struct net_device *netdev)
{
struct et131x_adapter *adapter = netdev_priv(netdev);
uint32_t PacketFilter = 0;
uint32_t count;
unsigned long lockflags;
struct dev_mc_list *mclist = netdev->mc_list;
DBG_ENTER(et131x_dbginfo);
spin_lock_irqsave(&adapter->Lock, lockflags);
/* Before we modify the platform-independent filter flags, store them
* locally. This allows us to determine if anything's changed and if
* we even need to bother the hardware
*/
PacketFilter = adapter->PacketFilter;
/* Clear the 'multicast' flag locally; becuase we only have a single
* flag to check multicast, and multiple multicast addresses can be
* set, this is the easiest way to determine if more than one
* multicast address is being set.
*/
PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
/* Check the net_device flags and set the device independent flags
* accordingly
*/
DBG_VERBOSE(et131x_dbginfo,
"MULTICAST ADDR COUNT: %d\n", netdev->mc_count);
if (netdev->flags & IFF_PROMISC) {
DBG_VERBOSE(et131x_dbginfo, "Request: PROMISCUOUS MODE ON\n");
adapter->PacketFilter |= ET131X_PACKET_TYPE_PROMISCUOUS;
} else {
DBG_VERBOSE(et131x_dbginfo, "Request: PROMISCUOUS MODE OFF\n");
adapter->PacketFilter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
}
if (netdev->flags & IFF_ALLMULTI) {
DBG_VERBOSE(et131x_dbginfo, "Request: ACCEPT ALL MULTICAST\n");
adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
}
if (netdev->mc_count > NIC_MAX_MCAST_LIST) {
DBG_WARNING(et131x_dbginfo,
"ACCEPT ALL MULTICAST for now, as there's more Multicast "
"addresses than the HW supports\n");
adapter->PacketFilter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
}
if (netdev->mc_count < 1) {
DBG_VERBOSE(et131x_dbginfo, "Request: REJECT ALL MULTICAST\n");
adapter->PacketFilter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
adapter->PacketFilter &= ~ET131X_PACKET_TYPE_MULTICAST;
} else {
DBG_VERBOSE(et131x_dbginfo,
"Request: SET MULTICAST FILTER(S)\n");
adapter->PacketFilter |= ET131X_PACKET_TYPE_MULTICAST;
}
/* Set values in the private adapter struct */
adapter->MCAddressCount = netdev->mc_count;
if (netdev->mc_count) {
if (mclist->dmi_addrlen != ETH_ALEN) {
DBG_WARNING(et131x_dbginfo,
"Multicast addrs are not ETH_ALEN in size\n");
} else {
count = netdev->mc_count - 1;
memcpy(adapter->MCList[count], mclist->dmi_addr,
ETH_ALEN);
}
}
/* Are the new flags different from the previous ones? If not, then no
* action is required
*
* NOTE - This block will always update the MCList with the hardware,
* even if the addresses aren't the same.
*/
if (PacketFilter != adapter->PacketFilter) {
/* Call the device's filter function */
DBG_VERBOSE(et131x_dbginfo, "UPDATE REQUIRED, FLAGS changed\n");
et131x_set_packet_filter(adapter);
} else {
DBG_VERBOSE(et131x_dbginfo,
"NO UPDATE REQUIRED, FLAGS didn't change\n");
}
spin_unlock_irqrestore(&adapter->Lock, lockflags);
DBG_LEAVE(et131x_dbginfo);
}
/**
* et131x_tx - The handler to tx a packet on the device
* @skb: data to be Tx'd
* @netdev: device on which data is to be Tx'd
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_tx(struct sk_buff *skb, struct net_device *netdev)
{
int status = 0;
DBG_TX_ENTER(et131x_dbginfo);
/* Save the timestamp for the TX timeout watchdog */
netdev->trans_start = jiffies;
/* Call the device-specific data Tx routine */
status = et131x_send_packets(skb, netdev);
/* Check status and manage the netif queue if necessary */
if (status != 0) {
if (status == -ENOMEM) {
DBG_VERBOSE(et131x_dbginfo,
"OUT OF TCBs; STOP NETIF QUEUE\n");
/* Put the queue to sleep until resources are
* available
*/
netif_stop_queue(netdev);
status = 1;
} else {
DBG_WARNING(et131x_dbginfo,
"Misc error; drop packet\n");
status = 0;
}
}
DBG_TX_LEAVE(et131x_dbginfo);
return status;
}
/**
* et131x_tx_timeout - Timeout handler
* @netdev: a pointer to a net_device struct representing the device
*
* The handler called when a Tx request times out. The timeout period is
* specified by the 'tx_timeo" element in the net_device structure (see
* et131x_alloc_device() to see how this value is set).
*/
void et131x_tx_timeout(struct net_device *netdev)
{
struct et131x_adapter *pAdapter = netdev_priv(netdev);
PMP_TCB pMpTcb;
unsigned long lockflags;
DBG_WARNING(et131x_dbginfo, "TX TIMEOUT\n");
/* Just skip this part if the adapter is doing link detection */
if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_LINK_DETECTION)) {
DBG_ERROR(et131x_dbginfo, "Still doing link detection\n");
return;
}
/* Any nonrecoverable hardware error?
* Checks adapter->flags for any failure in phy reading
*/
if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_NON_RECOVER_ERROR)) {
DBG_WARNING(et131x_dbginfo, "Non recoverable error - remove\n");
return;
}
/* Hardware failure? */
if (MP_TEST_FLAG(pAdapter, fMP_ADAPTER_HARDWARE_ERROR)) {
DBG_WARNING(et131x_dbginfo, "hardware error - reset\n");
return;
}
/* Is send stuck? */
spin_lock_irqsave(&pAdapter->TCBSendQLock, lockflags);
pMpTcb = pAdapter->TxRing.CurrSendHead;
if (pMpTcb != NULL) {
pMpTcb->Count++;
if (pMpTcb->Count > NIC_SEND_HANG_THRESHOLD) {
#ifdef CONFIG_ET131X_DEBUG
TX_STATUS_BLOCK_t txDmaComplete =
*(pAdapter->TxRing.pTxStatusVa);
PTX_DESC_ENTRY_t pDesc =
pAdapter->TxRing.pTxDescRingVa +
pMpTcb->WrIndex.bits.val;
#endif
TX_DESC_ENTRY_t StuckDescriptors[10];
if (pMpTcb->WrIndex.bits.val > 7) {
memcpy(StuckDescriptors,
pAdapter->TxRing.pTxDescRingVa +
pMpTcb->WrIndex.bits.val - 6,
sizeof(TX_DESC_ENTRY_t) * 10);
}
spin_unlock_irqrestore(&pAdapter->TCBSendQLock,
lockflags);
DBG_WARNING(et131x_dbginfo,
"Send stuck - reset. pMpTcb->WrIndex %x, Flags 0x%08x\n",
pMpTcb->WrIndex.bits.val,
pMpTcb->Flags);
DBG_WARNING(et131x_dbginfo,
"pDesc 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
pDesc->DataBufferPtrHigh,
pDesc->DataBufferPtrLow, pDesc->word2.value,
pDesc->word3.value);
DBG_WARNING(et131x_dbginfo,
"WbStatus 0x%08x\n", txDmaComplete.value);
#ifdef CONFIG_ET131X_DEBUG
DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 0);
DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 1);
DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 3);
DumpDeviceBlock(DBG_WARNING_ON, pAdapter, 5);
#endif
et131x_close(netdev);
et131x_open(netdev);
return;
}
}
spin_unlock_irqrestore(&pAdapter->TCBSendQLock, lockflags);
}
/**
* et131x_change_mtu - The handler called to change the MTU for the device
* @netdev: device whose MTU is to be changed
* @new_mtu: the desired MTU
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*/
int et131x_change_mtu(struct net_device *netdev, int new_mtu)
{
int result = 0;
struct et131x_adapter *adapter = netdev_priv(netdev);
DBG_ENTER(et131x_dbginfo);
/* Make sure the requested MTU is valid */
if (new_mtu == 0 || new_mtu > 9216) {
DBG_LEAVE(et131x_dbginfo);
return -EINVAL;
}
/* Stop the netif queue */
netif_stop_queue(netdev);
/* Stop the Tx and Rx DMA engines */
et131x_rx_dma_disable(adapter);
et131x_tx_dma_disable(adapter);
/* Disable device interrupts */
et131x_disable_interrupts(adapter);
et131x_handle_send_interrupt(adapter);
et131x_handle_recv_interrupt(adapter);
/* Set the new MTU */
netdev->mtu = new_mtu;
/* Free Rx DMA memory */
et131x_adapter_memory_free(adapter);
/* Set the config parameter for Jumbo Packet support */
adapter->RegistryJumboPacket = new_mtu + 14;
et131x_soft_reset(adapter);
/* Alloc and init Rx DMA memory */
result = et131x_adapter_memory_alloc(adapter);
if (result != 0) {
DBG_WARNING(et131x_dbginfo,
"Change MTU failed; couldn't re-alloc DMA memory\n");
return result;
}
et131x_init_send(adapter);
et131x_setup_hardware_properties(adapter);
memcpy(netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN);
/* Init the device with the new settings */
et131x_adapter_setup(adapter);
/* Enable interrupts */
if (MP_TEST_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE)) {
et131x_enable_interrupts(adapter);
}
/* Restart the Tx and Rx DMA engines */
et131x_rx_dma_enable(adapter);
et131x_tx_dma_enable(adapter);
/* Restart the netif queue */
netif_wake_queue(netdev);
DBG_LEAVE(et131x_dbginfo);
return result;
}
/**
* et131x_set_mac_addr - handler to change the MAC address for the device
* @netdev: device whose MAC is to be changed
* @new_mac: the desired MAC address
*
* Returns 0 on success, errno on failure (as defined in errno.h)
*
* IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14
*/
int et131x_set_mac_addr(struct net_device *netdev, void *new_mac)
{
int result = 0;
struct et131x_adapter *adapter = netdev_priv(netdev);
struct sockaddr *address = new_mac;
DBG_ENTER(et131x_dbginfo);
// begin blux
// DBG_VERBOSE( et131x_dbginfo, "Function not implemented!!\n" );
if (adapter == NULL) {
DBG_LEAVE(et131x_dbginfo);
return -ENODEV;
}
/* Make sure the requested MAC is valid */
if (!is_valid_ether_addr(address->sa_data)) {
DBG_LEAVE(et131x_dbginfo);
return -EINVAL;
}
/* Stop the netif queue */
netif_stop_queue(netdev);
/* Stop the Tx and Rx DMA engines */
et131x_rx_dma_disable(adapter);
et131x_tx_dma_disable(adapter);
/* Disable device interrupts */
et131x_disable_interrupts(adapter);
et131x_handle_send_interrupt(adapter);
et131x_handle_recv_interrupt(adapter);
/* Set the new MAC */
// netdev->set_mac_address = &new_mac;
// netdev->mtu = new_mtu;
memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len);
printk("%s: Setting MAC address to %02x:%02x:%02x:%02x:%02x:%02x\n",
netdev->name, netdev->dev_addr[0], netdev->dev_addr[1],
netdev->dev_addr[2], netdev->dev_addr[3], netdev->dev_addr[4],
netdev->dev_addr[5]);
/* Free Rx DMA memory */
et131x_adapter_memory_free(adapter);
/* Set the config parameter for Jumbo Packet support */
// adapter->RegistryJumboPacket = new_mtu + 14;
// blux: not needet here, w'll change the MAC
et131x_soft_reset(adapter);
/* Alloc and init Rx DMA memory */
result = et131x_adapter_memory_alloc(adapter);
if (result != 0) {
DBG_WARNING(et131x_dbginfo,
"Change MAC failed; couldn't re-alloc DMA memory\n");
return result;
}
et131x_init_send(adapter);
et131x_setup_hardware_properties(adapter);
// memcpy( netdev->dev_addr, adapter->CurrentAddress, ETH_ALEN );
// blux: no, do not override our nice address
/* Init the device with the new settings */
et131x_adapter_setup(adapter);
/* Enable interrupts */
if (MP_TEST_FLAG(adapter, fMP_ADAPTER_INTERRUPT_IN_USE)) {
et131x_enable_interrupts(adapter);
}
/* Restart the Tx and Rx DMA engines */
et131x_rx_dma_enable(adapter);
et131x_tx_dma_enable(adapter);
/* Restart the netif queue */
netif_wake_queue(netdev);
DBG_LEAVE(et131x_dbginfo);
return result;
}

64
drivers/staging/et131x/et131x_netdev.h Normal file
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@ -0,0 +1,64 @@
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_netdev.h - Defines, structs, enums, prototypes, etc. related to the
* driver's net_device support.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_NETDEV_H__
#define __ET131X_NETDEV_H__
struct net_device *et131x_device_alloc(void);
#endif /* __ET131X_NETDEV_H__ */

81
drivers/staging/et131x/et131x_version.h Normal file
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@ -0,0 +1,81 @@
/*
* Agere Systems Inc.
* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
* http://www.agere.com
*
*------------------------------------------------------------------------------
*
* et131x_version.h - This file provides system and device version information.
*
*------------------------------------------------------------------------------
*
* SOFTWARE LICENSE
*
* This software is provided subject to the following terms and conditions,
* which you should read carefully before using the software. Using this
* software indicates your acceptance of these terms and conditions. If you do
* not agree with these terms and conditions, do not use the software.
*
* Copyright © 2005 Agere Systems Inc.
* All rights reserved.
*
* Redistribution and use in source or binary forms, with or without
* modifications, are permitted provided that the following conditions are met:
*
* . Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following Disclaimer as comments in the code as
* well as in the documentation and/or other materials provided with the
* distribution.
*
* . Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following Disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* . Neither the name of Agere Systems Inc. nor the names of the contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* Disclaimer
*
* THIS SOFTWARE IS PROVIDED “AS IS” AND ANY EXPRESS OR IMPLIED WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
*/
#ifndef __ET131X_VERSION_H__
#define __ET131X_VERSION_H__
#define DRIVER_AUTHOR "Victor Soriano (vjsoriano@agere.com)"
#define DRIVER_LICENSE "Dual BSD/GPL"
#define DRIVER_DEVICE_STRING "ET1310"
#define DRIVER_NAME "et131x"
#define DRIVER_MAJOR_VERSION 1
#define DRIVER_MINOR_VERSION 2
#define DRIVER_PATCH_VERSION 3
#define DRIVER_VERSION_STRING "1.2.3"
#define DRIVER_VENDOR "Agere Systems, http://www.agere.com"
#define DRIVER_DESC "10/100/1000 Base-T Ethernet Driver"
#define STRUCT_MODULE "net" /* blux: missed by the kernel */
#define DRIVER_INFO DRIVER_DESC " for the "\
DRIVER_DEVICE_STRING ", v" \
DRIVER_VERSION_STRING " by " \
DRIVER_VENDOR
#define DRIVER_NAME_EXT "et131x.ko"
#endif /* __ET131X_VERSION_H__ */

25
drivers/staging/go7007/Kconfig Normal file
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config VIDEO_GO7007
tristate "Go 7007 support"
depends on VIDEO_DEV && PCI && I2C && INPUT
select VIDEOBUF_DMA_SG
select VIDEO_IR
select VIDEO_TUNER
select VIDEO_TVEEPROM
select CRC32
default N
---help---
This is a video4linux driver for some wierd device...
To compile this driver as a module, choose M here: the
module will be called go7007
config VIDEO_GO7007_USB
tristate "Go 7007 USB support"
depends on VIDEO_GO7007 && USB
default N
---help---
This is a video4linux driver for some wierd device...
To compile this driver as a module, choose M here: the
module will be called go7007-usb

18
drivers/staging/go7007/Makefile Normal file
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@ -0,0 +1,18 @@
#obj-m += go7007.o go7007-usb.o snd-go7007.o wis-saa7115.o wis-tw9903.o \
wis-uda1342.o wis-sony-tuner.o wis-saa7113.o wis-ov7640.o \
wis-tw2804.o
obj-$(CONFIG_VIDEO_GO7007) += go7007.o
obj-$(CONFIG_VIDEO_GO7007_USB) += go7007-usb.o
go7007-objs += go7007-v4l2.o go7007-driver.o go7007-i2c.o go7007-fw.o snd-go7007.o
#ifneq ($(SAA7134_BUILD),)
#obj-m += saa7134-go7007.o
#endif
EXTRA_CFLAGS += -Idrivers/staging/saa7134
EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core

11
drivers/staging/go7007/README Normal file
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@ -0,0 +1,11 @@
Todo:
- checkpatch.pl cleanups
- sparse cleanups
- lots of little modules, should be merged together
and added to the build.
- testing?
- handle churn in v4l layer.
Please send patchs to Greg Kroah-Hartman <greg@kroah.com> and Cc: Ross
Cohen <rcohen@snurgle.org> as well.

688
drivers/staging/go7007/go7007-driver.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/version.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
#include <linux/unistd.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/vmalloc.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/firmware.h>
#include <linux/semaphore.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include <linux/videodev2.h>
#include <media/tuner.h>
#include <media/v4l2-common.h>
#include "go7007-priv.h"
#include "wis-i2c.h"
/*
* Wait for an interrupt to be delivered from the GO7007SB and return
* the associated value and data.
*
* Must be called with the hw_lock held.
*/
int go7007_read_interrupt(struct go7007 *go, u16 *value, u16 *data)
{
go->interrupt_available = 0;
go->hpi_ops->read_interrupt(go);
if (wait_event_timeout(go->interrupt_waitq,
go->interrupt_available, 5*HZ) < 0) {
printk(KERN_ERR "go7007: timeout waiting for read interrupt\n");
return -1;
}
if (!go->interrupt_available)
return -1;
go->interrupt_available = 0;
*value = go->interrupt_value & 0xfffe;
*data = go->interrupt_data;
return 0;
}
EXPORT_SYMBOL(go7007_read_interrupt);
/*
* Read a register/address on the GO7007SB.
*
* Must be called with the hw_lock held.
*/
int go7007_read_addr(struct go7007 *go, u16 addr, u16 *data)
{
int count = 100;
u16 value;
if (go7007_write_interrupt(go, 0x0010, addr) < 0)
return -EIO;
while (count-- > 0) {
if (go7007_read_interrupt(go, &value, data) == 0 &&
value == 0xa000)
return 0;
}
return -EIO;
}
EXPORT_SYMBOL(go7007_read_addr);
/*
* Send the boot firmware to the encoder, which just wakes it up and lets
* us talk to the GPIO pins and on-board I2C adapter.
*
* Must be called with the hw_lock held.
*/
static int go7007_load_encoder(struct go7007 *go)
{
const struct firmware *fw_entry;
char fw_name[] = "go7007fw.bin";
void *bounce;
int fw_len, rv = 0;
u16 intr_val, intr_data;
if (request_firmware(&fw_entry, fw_name, go->dev)) {
printk(KERN_ERR
"go7007: unable to load firmware from file \"%s\"\n",
fw_name);
return -1;
}
if (fw_entry->size < 16 || memcmp(fw_entry->data, "WISGO7007FW", 11)) {
printk(KERN_ERR "go7007: file \"%s\" does not appear to be "
"go7007 firmware\n", fw_name);
release_firmware(fw_entry);
return -1;
}
fw_len = fw_entry->size - 16;
bounce = kmalloc(fw_len, GFP_KERNEL);
if (bounce == NULL) {
printk(KERN_ERR "go7007: unable to allocate %d bytes for "
"firmware transfer\n", fw_len);
release_firmware(fw_entry);
return -1;
}
memcpy(bounce, fw_entry->data + 16, fw_len);
release_firmware(fw_entry);
if (go7007_interface_reset(go) < 0 ||
go7007_send_firmware(go, bounce, fw_len) < 0 ||
go7007_read_interrupt(go, &intr_val, &intr_data) < 0 ||
(intr_val & ~0x1) != 0x5a5a) {
printk(KERN_ERR "go7007: error transferring firmware\n");
rv = -1;
}
kfree(bounce);
return rv;
}
/*
* Boot the encoder and register the I2C adapter if requested. Do the
* minimum initialization necessary, since the board-specific code may
* still need to probe the board ID.
*
* Must NOT be called with the hw_lock held.
*/
int go7007_boot_encoder(struct go7007 *go, int init_i2c)
{
int ret;
down(&go->hw_lock);
ret = go7007_load_encoder(go);
up(&go->hw_lock);
if (ret < 0)
return -1;
if (!init_i2c)
return 0;
if (go7007_i2c_init(go) < 0)
return -1;
go->i2c_adapter_online = 1;
return 0;
}
EXPORT_SYMBOL(go7007_boot_encoder);
/*
* Configure any hardware-related registers in the GO7007, such as GPIO
* pins and bus parameters, which are board-specific. This assumes
* the boot firmware has already been downloaded.
*
* Must be called with the hw_lock held.
*/
static int go7007_init_encoder(struct go7007 *go)
{
if (go->board_info->audio_flags & GO7007_AUDIO_I2S_MASTER) {
go7007_write_addr(go, 0x1000, 0x0811);
go7007_write_addr(go, 0x1000, 0x0c11);
}
if (go->board_id == GO7007_BOARDID_MATRIX_REV) {
/* Set GPIO pin 0 to be an output (audio clock control) */
go7007_write_addr(go, 0x3c82, 0x0001);
go7007_write_addr(go, 0x3c80, 0x00fe);
}
return 0;
}
/*
* Send the boot firmware to the GO7007 and configure the registers. This
* is the only way to stop the encoder once it has started streaming video.
*
* Must be called with the hw_lock held.
*/
int go7007_reset_encoder(struct go7007 *go)
{
if (go7007_load_encoder(go) < 0)
return -1;
return go7007_init_encoder(go);
}
/*
* Attempt to instantiate an I2C client by ID, probably loading a module.
*/
static int init_i2c_module(struct i2c_adapter *adapter, int id, int addr)
{
char *modname;
switch (id) {
case I2C_DRIVERID_WIS_SAA7115:
modname = "wis-saa7115";
break;
case I2C_DRIVERID_WIS_SAA7113:
modname = "wis-saa7113";
break;
case I2C_DRIVERID_WIS_UDA1342:
modname = "wis-uda1342";
break;
case I2C_DRIVERID_WIS_SONY_TUNER:
modname = "wis-sony-tuner";
break;
case I2C_DRIVERID_WIS_TW9903:
modname = "wis-tw9903";
break;
case I2C_DRIVERID_WIS_TW2804:
modname = "wis-tw2804";
break;
case I2C_DRIVERID_WIS_OV7640:
modname = "wis-ov7640";
break;
default:
modname = NULL;
break;
}
if (modname != NULL)
request_module(modname);
if (wis_i2c_probe_device(adapter, id, addr) == 1)
return 0;
if (modname != NULL)
printk(KERN_INFO
"go7007: probing for module %s failed", modname);
else
printk(KERN_INFO
"go7007: sensor %u seems to be unsupported!\n", id);
return -1;
}
/*
* Finalize the GO7007 hardware setup, register the on-board I2C adapter
* (if used on this board), load the I2C client driver for the sensor
* (SAA7115 or whatever) and other devices, and register the ALSA and V4L2
* interfaces.
*
* Must NOT be called with the hw_lock held.
*/
int go7007_register_encoder(struct go7007 *go)
{
int i, ret;
printk(KERN_INFO "go7007: registering new %s\n", go->name);
down(&go->hw_lock);
ret = go7007_init_encoder(go);
up(&go->hw_lock);
if (ret < 0)
return -1;
if (!go->i2c_adapter_online &&
go->board_info->flags & GO7007_BOARD_USE_ONBOARD_I2C) {
if (go7007_i2c_init(go) < 0)
return -1;
go->i2c_adapter_online = 1;
}
if (go->i2c_adapter_online) {
for (i = 0; i < go->board_info->num_i2c_devs; ++i)
init_i2c_module(&go->i2c_adapter,
go->board_info->i2c_devs[i].id,
go->board_info->i2c_devs[i].addr);
#ifdef TUNER_SET_TYPE_ADDR
if (go->tuner_type >= 0) {
struct tuner_setup tun_setup = {
.mode_mask = T_ANALOG_TV,
.addr = ADDR_UNSET,
.type = go->tuner_type
};
i2c_clients_command(&go->i2c_adapter,
TUNER_SET_TYPE_ADDR, &tun_setup);
}
#else
if (go->tuner_type >= 0)
i2c_clients_command(&go->i2c_adapter,
TUNER_SET_TYPE, &go->tuner_type);
#endif
if (go->board_id == GO7007_BOARDID_ADLINK_MPG24)
i2c_clients_command(&go->i2c_adapter,
DECODER_SET_CHANNEL, &go->channel_number);
}
if (go->board_info->flags & GO7007_BOARD_HAS_AUDIO) {
go->audio_enabled = 1;
go7007_snd_init(go);
}
return go7007_v4l2_init(go);
}
EXPORT_SYMBOL(go7007_register_encoder);
/*
* Send the encode firmware to the encoder, which will cause it
* to immediately start delivering the video and audio streams.
*
* Must be called with the hw_lock held.
*/
int go7007_start_encoder(struct go7007 *go)
{
u8 *fw;
int fw_len, rv = 0, i;
u16 intr_val, intr_data;
go->modet_enable = 0;
if (!go->dvd_mode)
for (i = 0; i < 4; ++i) {
if (go->modet[i].enable) {
go->modet_enable = 1;
continue;
}
go->modet[i].pixel_threshold = 32767;
go->modet[i].motion_threshold = 32767;
go->modet[i].mb_threshold = 32767;
}
if (go7007_construct_fw_image(go, &fw, &fw_len) < 0)
return -1;
if (go7007_send_firmware(go, fw, fw_len) < 0 ||
go7007_read_interrupt(go, &intr_val, &intr_data) < 0) {
printk(KERN_ERR "go7007: error transferring firmware\n");
rv = -1;
goto start_error;
}
go->state = STATE_DATA;
go->parse_length = 0;
go->seen_frame = 0;
if (go7007_stream_start(go) < 0) {
printk(KERN_ERR "go7007: error starting stream transfer\n");
rv = -1;
goto start_error;
}
start_error:
kfree(fw);
return rv;
}
/*
* Store a byte in the current video buffer, if there is one.
*/
static inline void store_byte(struct go7007_buffer *gobuf, u8 byte)
{
if (gobuf != NULL && gobuf->bytesused < GO7007_BUF_SIZE) {
unsigned int pgidx = gobuf->offset >> PAGE_SHIFT;
unsigned int pgoff = gobuf->offset & ~PAGE_MASK;
*((u8 *)page_address(gobuf->pages[pgidx]) + pgoff) = byte;
++gobuf->offset;
++gobuf->bytesused;
}
}
/*
* Deliver the last video buffer and get a new one to start writing to.
*/
static void frame_boundary(struct go7007 *go)
{
struct go7007_buffer *gobuf;
int i;
if (go->active_buf) {
if (go->active_buf->modet_active) {
if (go->active_buf->bytesused + 216 < GO7007_BUF_SIZE) {
for (i = 0; i < 216; ++i)
store_byte(go->active_buf,
go->active_map[i]);
go->active_buf->bytesused -= 216;
} else
go->active_buf->modet_active = 0;
}
go->active_buf->state = BUF_STATE_DONE;
wake_up_interruptible(&go->frame_waitq);
go->active_buf = NULL;
}
list_for_each_entry(gobuf, &go->stream, stream)
if (gobuf->state == BUF_STATE_QUEUED) {
gobuf->seq = go->next_seq;
do_gettimeofday(&gobuf->timestamp);
go->active_buf = gobuf;
break;
}
++go->next_seq;
}
static void write_bitmap_word(struct go7007 *go)
{
int x, y, i, stride = ((go->width >> 4) + 7) >> 3;
for (i = 0; i < 16; ++i) {
y = (((go->parse_length - 1) << 3) + i) / (go->width >> 4);
x = (((go->parse_length - 1) << 3) + i) % (go->width >> 4);
go->active_map[stride * y + (x >> 3)] |=
(go->modet_word & 1) << (x & 0x7);
go->modet_word >>= 1;
}
}
/*
* Parse a chunk of the video stream into frames. The frames are not
* delimited by the hardware, so we have to parse the frame boundaries
* based on the type of video stream we're receiving.
*/
void go7007_parse_video_stream(struct go7007 *go, u8 *buf, int length)
{
int i, seq_start_code = -1, frame_start_code = -1;
spin_lock(&go->spinlock);
switch (go->format) {
case GO7007_FORMAT_MPEG4:
seq_start_code = 0xB0;
frame_start_code = 0xB6;
break;
case GO7007_FORMAT_MPEG1:
case GO7007_FORMAT_MPEG2:
seq_start_code = 0xB3;
frame_start_code = 0x00;
break;
}
for (i = 0; i < length; ++i) {
if (go->active_buf != NULL &&
go->active_buf->bytesused >= GO7007_BUF_SIZE - 3) {
printk(KERN_DEBUG "go7007: dropping oversized frame\n");
go->active_buf->offset -= go->active_buf->bytesused;
go->active_buf->bytesused = 0;
go->active_buf->modet_active = 0;
go->active_buf = NULL;
}
switch (go->state) {
case STATE_DATA:
switch (buf[i]) {
case 0x00:
go->state = STATE_00;
break;
case 0xFF:
go->state = STATE_FF;
break;
default:
store_byte(go->active_buf, buf[i]);
break;
}
break;
case STATE_00:
switch (buf[i]) {
case 0x00:
go->state = STATE_00_00;
break;
case 0xFF:
store_byte(go->active_buf, 0x00);
go->state = STATE_FF;
break;
default:
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, buf[i]);
go->state = STATE_DATA;
break;
}
break;
case STATE_00_00:
switch (buf[i]) {
case 0x00:
store_byte(go->active_buf, 0x00);
/* go->state remains STATE_00_00 */
break;
case 0x01:
go->state = STATE_00_00_01;
break;
case 0xFF:
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x00);
go->state = STATE_FF;
break;
default:
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, buf[i]);
go->state = STATE_DATA;
break;
}
break;
case STATE_00_00_01:
/* If this is the start of a new MPEG frame,
* get a new buffer */
if ((go->format == GO7007_FORMAT_MPEG1 ||
go->format == GO7007_FORMAT_MPEG2 ||
go->format == GO7007_FORMAT_MPEG4) &&
(buf[i] == seq_start_code ||
buf[i] == 0xB8 || /* GOP code */
buf[i] == frame_start_code)) {
if (go->active_buf == NULL || go->seen_frame)
frame_boundary(go);
if (buf[i] == frame_start_code) {
if (go->active_buf != NULL)
go->active_buf->frame_offset =
go->active_buf->offset;
go->seen_frame = 1;
} else {
go->seen_frame = 0;
}
}
/* Handle any special chunk types, or just write the
* start code to the (potentially new) buffer */
switch (buf[i]) {
case 0xF5: /* timestamp */
go->parse_length = 12;
go->state = STATE_UNPARSED;
break;
case 0xF6: /* vbi */
go->state = STATE_VBI_LEN_A;
break;
case 0xF8: /* MD map */
go->parse_length = 0;
memset(go->active_map, 0,
sizeof(go->active_map));
go->state = STATE_MODET_MAP;
break;
case 0xFF: /* Potential JPEG start code */
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x01);
go->state = STATE_FF;
break;
default:
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x00);
store_byte(go->active_buf, 0x01);
store_byte(go->active_buf, buf[i]);
go->state = STATE_DATA;
break;
}
break;
case STATE_FF:
switch (buf[i]) {
case 0x00:
store_byte(go->active_buf, 0xFF);
go->state = STATE_00;
break;
case 0xFF:
store_byte(go->active_buf, 0xFF);
/* go->state remains STATE_FF */
break;
case 0xD8:
if (go->format == GO7007_FORMAT_MJPEG)
frame_boundary(go);
/* fall through */
default:
store_byte(go->active_buf, 0xFF);
store_byte(go->active_buf, buf[i]);
go->state = STATE_DATA;
break;
}
break;
case STATE_VBI_LEN_A:
go->parse_length = buf[i] << 8;
go->state = STATE_VBI_LEN_B;
break;
case STATE_VBI_LEN_B:
go->parse_length |= buf[i];
if (go->parse_length > 0)
go->state = STATE_UNPARSED;
else
go->state = STATE_DATA;
break;
case STATE_MODET_MAP:
if (go->parse_length < 204) {
if (go->parse_length & 1) {
go->modet_word |= buf[i];
write_bitmap_word(go);
} else
go->modet_word = buf[i] << 8;
} else if (go->parse_length == 207 && go->active_buf) {
go->active_buf->modet_active = buf[i];
}
if (++go->parse_length == 208)
go->state = STATE_DATA;
break;
case STATE_UNPARSED:
if (--go->parse_length == 0)
go->state = STATE_DATA;
break;
}
}
spin_unlock(&go->spinlock);
}
EXPORT_SYMBOL(go7007_parse_video_stream);
/*
* Allocate a new go7007 struct. Used by the hardware-specific probe.
*/
struct go7007 *go7007_alloc(struct go7007_board_info *board, struct device *dev)
{
struct go7007 *go;
int i;
go = kmalloc(sizeof(struct go7007), GFP_KERNEL);
if (go == NULL)
return NULL;
go->dev = dev;
go->board_info = board;
go->board_id = 0;
go->tuner_type = -1;
go->channel_number = 0;
go->name[0] = 0;
init_MUTEX(&go->hw_lock);
init_waitqueue_head(&go->frame_waitq);
spin_lock_init(&go->spinlock);
go->video_dev = NULL;
go->ref_count = 0;
go->status = STATUS_INIT;
memset(&go->i2c_adapter, 0, sizeof(go->i2c_adapter));
go->i2c_adapter_online = 0;
go->interrupt_available = 0;
init_waitqueue_head(&go->interrupt_waitq);
go->in_use = 0;
go->input = 0;
if (board->sensor_flags & GO7007_SENSOR_TV) {
go->standard = GO7007_STD_NTSC;
go->width = 720;
go->height = 480;
go->sensor_framerate = 30000;
} else {
go->standard = GO7007_STD_OTHER;
go->width = board->sensor_width;
go->height = board->sensor_height;
go->sensor_framerate = board->sensor_framerate;
}
go->encoder_v_offset = board->sensor_v_offset;
go->encoder_h_offset = board->sensor_h_offset;
go->encoder_h_halve = 0;
go->encoder_v_halve = 0;
go->encoder_subsample = 0;
go->streaming = 0;
go->format = GO7007_FORMAT_MJPEG;
go->bitrate = 1500000;
go->fps_scale = 1;
go->pali = 0;
go->aspect_ratio = GO7007_RATIO_1_1;
go->gop_size = 0;
go->ipb = 0;
go->closed_gop = 0;
go->repeat_seqhead = 0;
go->seq_header_enable = 0;
go->gop_header_enable = 0;
go->dvd_mode = 0;
go->interlace_coding = 0;
for (i = 0; i < 4; ++i)
go->modet[i].enable = 0;;
for (i = 0; i < 1624; ++i)
go->modet_map[i] = 0;
go->audio_deliver = NULL;
go->audio_enabled = 0;
INIT_LIST_HEAD(&go->stream);
return go;
}
EXPORT_SYMBOL(go7007_alloc);
/*
* Detach and unregister the encoder. The go7007 struct won't be freed
* until v4l2 finishes releasing its resources and all associated fds are
* closed by applications.
*/
void go7007_remove(struct go7007 *go)
{
if (go->i2c_adapter_online) {
if (i2c_del_adapter(&go->i2c_adapter) == 0)
go->i2c_adapter_online = 0;
else
printk(KERN_ERR
"go7007: error removing I2C adapter!\n");
}
if (go->audio_enabled)
go7007_snd_remove(go);
go7007_v4l2_remove(go);
}
EXPORT_SYMBOL(go7007_remove);
MODULE_LICENSE("GPL v2");

1639
drivers/staging/go7007/go7007-fw.c Normal file
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309
drivers/staging/go7007/go7007-i2c.c Normal file
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@ -0,0 +1,309 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/list.h>
#include <linux/unistd.h>
#include <linux/time.h>
#include <linux/device.h>
#include <linux/i2c.h>
#include <linux/semaphore.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include "go7007-priv.h"
#include "wis-i2c.h"
/************** Registration interface for I2C client drivers **************/
/* Since there's no way to auto-probe the I2C devices connected to the I2C
* bus on the go7007, we have this silly little registration system that
* client drivers can use to register their I2C driver ID and their
* detect_client function (the one that's normally passed to i2c_probe).
*
* When a new go7007 device is connected, we can look up in a board info
* table by the USB or PCI vendor/product/revision ID to determine
* which I2C client module to load. The client driver module will register
* itself here, and then we can call the registered detect_client function
* to force-load a new client at the address listed in the board info table.
*
* Really the I2C subsystem should have a way to force-load I2C client
* drivers when we have a priori knowledge of what's on the bus, especially
* since the existing I2C auto-probe mechanism is so hokey, but we'll use
* our own mechanism for the time being. */
struct wis_i2c_client_driver {
unsigned int id;
found_proc found_proc;
struct list_head list;
};
static LIST_HEAD(i2c_client_drivers);
static DECLARE_MUTEX(i2c_client_driver_list_lock);
/* Client drivers register here by their I2C driver ID */
int wis_i2c_add_driver(unsigned int id, found_proc found_proc)
{
struct wis_i2c_client_driver *driver;
driver = kmalloc(sizeof(struct wis_i2c_client_driver), GFP_KERNEL);
if (driver == NULL)
return -ENOMEM;
driver->id = id;
driver->found_proc = found_proc;
down(&i2c_client_driver_list_lock);
list_add_tail(&driver->list, &i2c_client_drivers);
up(&i2c_client_driver_list_lock);
return 0;
}
EXPORT_SYMBOL(wis_i2c_add_driver);
void wis_i2c_del_driver(found_proc found_proc)
{
struct wis_i2c_client_driver *driver, *next;
down(&i2c_client_driver_list_lock);
list_for_each_entry_safe(driver, next, &i2c_client_drivers, list)
if (driver->found_proc == found_proc) {
list_del(&driver->list);
kfree(driver);
}
up(&i2c_client_driver_list_lock);
}
EXPORT_SYMBOL(wis_i2c_del_driver);
/* The main go7007 driver calls this to instantiate a client by driver
* ID and bus address, which are both stored in the board info table */
int wis_i2c_probe_device(struct i2c_adapter *adapter,
unsigned int id, int addr)
{
struct wis_i2c_client_driver *driver;
int found = 0;
if (addr < 0 || addr > 0x7f)
return -1;
down(&i2c_client_driver_list_lock);
list_for_each_entry(driver, &i2c_client_drivers, list)
if (driver->id == id) {
if (driver->found_proc(adapter, addr, 0) == 0)
found = 1;
break;
}
up(&i2c_client_driver_list_lock);
return found;
}
/********************* Driver for on-board I2C adapter *********************/
/* #define GO7007_I2C_DEBUG */
#define SPI_I2C_ADDR_BASE 0x1400
#define STATUS_REG_ADDR (SPI_I2C_ADDR_BASE + 0x2)
#define I2C_CTRL_REG_ADDR (SPI_I2C_ADDR_BASE + 0x6)
#define I2C_DEV_UP_ADDR_REG_ADDR (SPI_I2C_ADDR_BASE + 0x7)
#define I2C_LO_ADDR_REG_ADDR (SPI_I2C_ADDR_BASE + 0x8)
#define I2C_DATA_REG_ADDR (SPI_I2C_ADDR_BASE + 0x9)
#define I2C_CLKFREQ_REG_ADDR (SPI_I2C_ADDR_BASE + 0xa)
#define I2C_STATE_MASK 0x0007
#define I2C_READ_READY_MASK 0x0008
/* There is only one I2C port on the TW2804 that feeds all four GO7007 VIPs
* on the Adlink PCI-MPG24, so access is shared between all of them. */
static DECLARE_MUTEX(adlink_mpg24_i2c_lock);
static int go7007_i2c_xfer(struct go7007 *go, u16 addr, int read,
u16 command, int flags, u8 *data)
{
int i, ret = -1;
u16 val;
if (go->status == STATUS_SHUTDOWN)
return -1;
#ifdef GO7007_I2C_DEBUG
if (read)
printk(KERN_DEBUG "go7007-i2c: reading 0x%02x on 0x%02x\n",
command, addr);
else
printk(KERN_DEBUG
"go7007-i2c: writing 0x%02x to 0x%02x on 0x%02x\n",
*data, command, addr);
#endif
down(&go->hw_lock);
if (go->board_id == GO7007_BOARDID_ADLINK_MPG24) {
/* Bridge the I2C port on this GO7007 to the shared bus */
down(&adlink_mpg24_i2c_lock);
go7007_write_addr(go, 0x3c82, 0x0020);
}
/* Wait for I2C adapter to be ready */
for (i = 0; i < 10; ++i) {
if (go7007_read_addr(go, STATUS_REG_ADDR, &val) < 0)
goto i2c_done;
if (!(val & I2C_STATE_MASK))
break;
msleep(100);
}
if (i == 10) {
printk(KERN_ERR "go7007-i2c: I2C adapter is hung\n");
goto i2c_done;
}
/* Set target register (command) */
go7007_write_addr(go, I2C_CTRL_REG_ADDR, flags);
go7007_write_addr(go, I2C_LO_ADDR_REG_ADDR, command);
/* If we're writing, send the data and target address and we're done */
if (!read) {
go7007_write_addr(go, I2C_DATA_REG_ADDR, *data);
go7007_write_addr(go, I2C_DEV_UP_ADDR_REG_ADDR,
(addr << 9) | (command >> 8));
ret = 0;
goto i2c_done;
}
/* Otherwise, we're reading. First clear i2c_rx_data_rdy. */
if (go7007_read_addr(go, I2C_DATA_REG_ADDR, &val) < 0)
goto i2c_done;
/* Send the target address plus read flag */
go7007_write_addr(go, I2C_DEV_UP_ADDR_REG_ADDR,
(addr << 9) | 0x0100 | (command >> 8));
/* Wait for i2c_rx_data_rdy */
for (i = 0; i < 10; ++i) {
if (go7007_read_addr(go, STATUS_REG_ADDR, &val) < 0)
goto i2c_done;
if (val & I2C_READ_READY_MASK)
break;
msleep(100);
}
if (i == 10) {
printk(KERN_ERR "go7007-i2c: I2C adapter is hung\n");
goto i2c_done;
}
/* Retrieve the read byte */
if (go7007_read_addr(go, I2C_DATA_REG_ADDR, &val) < 0)
goto i2c_done;
*data = val;
ret = 0;
i2c_done:
if (go->board_id == GO7007_BOARDID_ADLINK_MPG24) {
/* Isolate the I2C port on this GO7007 from the shared bus */
go7007_write_addr(go, 0x3c82, 0x0000);
up(&adlink_mpg24_i2c_lock);
}
up(&go->hw_lock);
return ret;
}
static int go7007_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
unsigned short flags, char read_write,
u8 command, int size, union i2c_smbus_data *data)
{
struct go7007 *go = i2c_get_adapdata(adapter);
if (size != I2C_SMBUS_BYTE_DATA)
return -1;
return go7007_i2c_xfer(go, addr, read_write == I2C_SMBUS_READ, command,
flags & I2C_CLIENT_SCCB ? 0x10 : 0x00, &data->byte);
}
/* VERY LIMITED I2C master xfer function -- only needed because the
* SMBus functions only support 8-bit commands and the SAA7135 uses
* 16-bit commands. The I2C interface on the GO7007, as limited as
* it is, does support this mode. */
static int go7007_i2c_master_xfer(struct i2c_adapter *adapter,
struct i2c_msg msgs[], int num)
{
struct go7007 *go = i2c_get_adapdata(adapter);
int i;
for (i = 0; i < num; ++i) {
/* We can only do two things here -- write three bytes, or
* write two bytes and read one byte. */
if (msgs[i].len == 2) {
if (i + 1 == num || msgs[i].addr != msgs[i + 1].addr ||
(msgs[i].flags & I2C_M_RD) ||
!(msgs[i + 1].flags & I2C_M_RD) ||
msgs[i + 1].len != 1)
return -1;
if (go7007_i2c_xfer(go, msgs[i].addr, 1,
(msgs[i].buf[0] << 8) | msgs[i].buf[1],
0x01, &msgs[i + 1].buf[0]) < 0)
return -1;
++i;
} else if (msgs[i].len == 3) {
if (msgs[i].flags & I2C_M_RD)
return -1;
if (msgs[i].len != 3)
return -1;
if (go7007_i2c_xfer(go, msgs[i].addr, 0,
(msgs[i].buf[0] << 8) | msgs[i].buf[1],
0x01, &msgs[i].buf[2]) < 0)
return -1;
} else
return -1;
}
return 0;
}
static u32 go7007_functionality(struct i2c_adapter *adapter)
{
return I2C_FUNC_SMBUS_BYTE_DATA;
}
static struct i2c_algorithm go7007_algo = {
.smbus_xfer = go7007_smbus_xfer,
.master_xfer = go7007_i2c_master_xfer,
.functionality = go7007_functionality,
};
static struct i2c_adapter go7007_adap_templ = {
.owner = THIS_MODULE,
.class = I2C_CLASS_TV_ANALOG,
.name = "WIS GO7007SB",
.id = I2C_ALGO_GO7007,
.algo = &go7007_algo,
};
int go7007_i2c_init(struct go7007 *go)
{
memcpy(&go->i2c_adapter, &go7007_adap_templ,
sizeof(go7007_adap_templ));
go->i2c_adapter.dev.parent = go->dev;
i2c_set_adapdata(&go->i2c_adapter, go);
if (i2c_add_adapter(&go->i2c_adapter) < 0) {
printk(KERN_ERR
"go7007-i2c: error: i2c_add_adapter failed\n");
return -1;
}
return 0;
}

279
drivers/staging/go7007/go7007-priv.h Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
/*
* This is the private include file for the go7007 driver. It should not
* be included by anybody but the driver itself, and especially not by
* user-space applications.
*/
struct go7007;
/* IDs to activate board-specific support code */
#define GO7007_BOARDID_MATRIX_II 0
#define GO7007_BOARDID_MATRIX_RELOAD 1
#define GO7007_BOARDID_STAR_TREK 2
#define GO7007_BOARDID_PCI_VOYAGER 3
#define GO7007_BOARDID_XMEN 4
#define GO7007_BOARDID_XMEN_II 5
#define GO7007_BOARDID_XMEN_III 6
#define GO7007_BOARDID_MATRIX_REV 7
#define GO7007_BOARDID_PX_M402U 16
#define GO7007_BOARDID_PX_TV402U_ANY 17 /* need to check tuner model */
#define GO7007_BOARDID_PX_TV402U_NA 18 /* detected NTSC tuner */
#define GO7007_BOARDID_PX_TV402U_EU 19 /* detected PAL tuner */
#define GO7007_BOARDID_PX_TV402U_JP 20 /* detected NTSC-J tuner */
#define GO7007_BOARDID_LIFEVIEW_LR192 21 /* TV Walker Ultra */
#define GO7007_BOARDID_ENDURA 22
#define GO7007_BOARDID_ADLINK_MPG24 23
/* Various characteristics of each board */
#define GO7007_BOARD_HAS_AUDIO (1<<0)
#define GO7007_BOARD_USE_ONBOARD_I2C (1<<1)
#define GO7007_BOARD_HAS_TUNER (1<<2)
/* Characteristics of sensor devices */
#define GO7007_SENSOR_VALID_POLAR (1<<0)
#define GO7007_SENSOR_HREF_POLAR (1<<1)
#define GO7007_SENSOR_VREF_POLAR (1<<2)
#define GO7007_SENSOR_FIELD_ID_POLAR (1<<3)
#define GO7007_SENSOR_BIT_WIDTH (1<<4)
#define GO7007_SENSOR_VALID_ENABLE (1<<5)
#define GO7007_SENSOR_656 (1<<6)
#define GO7007_SENSOR_CONFIG_MASK 0x7f
#define GO7007_SENSOR_TV (1<<7)
#define GO7007_SENSOR_VBI (1<<8)
#define GO7007_SENSOR_SCALING (1<<9)
/* Characteristics of audio sensor devices */
#define GO7007_AUDIO_I2S_MODE_1 (1)
#define GO7007_AUDIO_I2S_MODE_2 (2)
#define GO7007_AUDIO_I2S_MODE_3 (3)
#define GO7007_AUDIO_BCLK_POLAR (1<<2)
#define GO7007_AUDIO_WORD_14 (14<<4)
#define GO7007_AUDIO_WORD_16 (16<<4)
#define GO7007_AUDIO_ONE_CHANNEL (1<<11)
#define GO7007_AUDIO_I2S_MASTER (1<<16)
#define GO7007_AUDIO_OKI_MODE (1<<17)
struct go7007_board_info {
char *firmware;
unsigned int flags;
int hpi_buffer_cap;
unsigned int sensor_flags;
int sensor_width;
int sensor_height;
int sensor_framerate;
int sensor_h_offset;
int sensor_v_offset;
unsigned int audio_flags;
int audio_rate;
int audio_bclk_div;
int audio_main_div;
int num_i2c_devs;
struct {
int id;
int addr;
} i2c_devs[4];
int num_inputs;
struct {
int video_input;
int audio_input;
char *name;
} inputs[4];
};
struct go7007_hpi_ops {
int (*interface_reset)(struct go7007 *go);
int (*write_interrupt)(struct go7007 *go, int addr, int data);
int (*read_interrupt)(struct go7007 *go);
int (*stream_start)(struct go7007 *go);
int (*stream_stop)(struct go7007 *go);
int (*send_firmware)(struct go7007 *go, u8 *data, int len);
};
/* The video buffer size must be a multiple of PAGE_SIZE */
#define GO7007_BUF_PAGES (128 * 1024 / PAGE_SIZE)
#define GO7007_BUF_SIZE (GO7007_BUF_PAGES << PAGE_SHIFT)
struct go7007_buffer {
struct go7007 *go; /* Reverse reference for VMA ops */
int index; /* Reverse reference for DQBUF */
enum { BUF_STATE_IDLE, BUF_STATE_QUEUED, BUF_STATE_DONE } state;
u32 seq;
struct timeval timestamp;
struct list_head stream;
struct page *pages[GO7007_BUF_PAGES + 1]; /* extra for straddling */
unsigned long user_addr;
unsigned int page_count;
unsigned int offset;
unsigned int bytesused;
unsigned int frame_offset;
u32 modet_active;
int mapped;
};
struct go7007_file {
struct go7007 *go;
struct semaphore lock;
int buf_count;
struct go7007_buffer *bufs;
};
#define GO7007_FORMAT_MJPEG 0
#define GO7007_FORMAT_MPEG4 1
#define GO7007_FORMAT_MPEG1 2
#define GO7007_FORMAT_MPEG2 3
#define GO7007_FORMAT_H263 4
#define GO7007_RATIO_1_1 0
#define GO7007_RATIO_4_3 1
#define GO7007_RATIO_16_9 2
enum go7007_parser_state {
STATE_DATA,
STATE_00,
STATE_00_00,
STATE_00_00_01,
STATE_FF,
STATE_VBI_LEN_A,
STATE_VBI_LEN_B,
STATE_MODET_MAP,
STATE_UNPARSED,
};
struct go7007 {
struct device *dev;
struct go7007_board_info *board_info;
unsigned int board_id;
int tuner_type;
int channel_number; /* for multi-channel boards like Adlink PCI-MPG24 */
char name[64];
struct video_device *video_dev;
int ref_count;
enum { STATUS_INIT, STATUS_ONLINE, STATUS_SHUTDOWN } status;
spinlock_t spinlock;
struct semaphore hw_lock;
int streaming;
int in_use;
int audio_enabled;
/* Video input */
int input;
enum { GO7007_STD_NTSC, GO7007_STD_PAL, GO7007_STD_OTHER } standard;
int sensor_framerate;
int width;
int height;
int encoder_h_offset;
int encoder_v_offset;
unsigned int encoder_h_halve:1;
unsigned int encoder_v_halve:1;
unsigned int encoder_subsample:1;
/* Encoder config */
int format;
int bitrate;
int fps_scale;
int pali;
int aspect_ratio;
int gop_size;
unsigned int ipb:1;
unsigned int closed_gop:1;
unsigned int repeat_seqhead:1;
unsigned int seq_header_enable:1;
unsigned int gop_header_enable:1;
unsigned int dvd_mode:1;
unsigned int interlace_coding:1;
/* Motion detection */
unsigned int modet_enable:1;
struct {
unsigned int enable:1;
int pixel_threshold;
int motion_threshold;
int mb_threshold;
} modet[4];
unsigned char modet_map[1624];
unsigned char active_map[216];
/* Video streaming */
struct go7007_buffer *active_buf;
enum go7007_parser_state state;
int parse_length;
u16 modet_word;
int seen_frame;
u32 next_seq;
struct list_head stream;
wait_queue_head_t frame_waitq;
/* Audio streaming */
void (*audio_deliver)(struct go7007 *go, u8 *buf, int length);
void *snd_context;
/* I2C */
int i2c_adapter_online;
struct i2c_adapter i2c_adapter;
/* HPI driver */
struct go7007_hpi_ops *hpi_ops;
void *hpi_context;
int interrupt_available;
wait_queue_head_t interrupt_waitq;
unsigned short interrupt_value;
unsigned short interrupt_data;
};
/* All of these must be called with the hpi_lock semaphore held! */
#define go7007_interface_reset(go) \
((go)->hpi_ops->interface_reset(go))
#define go7007_write_interrupt(go, x, y) \
((go)->hpi_ops->write_interrupt)((go), (x), (y))
#define go7007_stream_start(go) \
((go)->hpi_ops->stream_start(go))
#define go7007_stream_stop(go) \
((go)->hpi_ops->stream_stop(go))
#define go7007_send_firmware(go, x, y) \
((go)->hpi_ops->send_firmware)((go), (x), (y))
#define go7007_write_addr(go, x, y) \
((go)->hpi_ops->write_interrupt)((go), (x)|0x8000, (y))
/* go7007-driver.c */
int go7007_read_addr(struct go7007 *go, u16 addr, u16 *data);
int go7007_read_interrupt(struct go7007 *go, u16 *value, u16 *data);
int go7007_boot_encoder(struct go7007 *go, int init_i2c);
int go7007_reset_encoder(struct go7007 *go);
int go7007_register_encoder(struct go7007 *go);
int go7007_start_encoder(struct go7007 *go);
void go7007_parse_video_stream(struct go7007 *go, u8 *buf, int length);
struct go7007 *go7007_alloc(struct go7007_board_info *board,
struct device *dev);
void go7007_remove(struct go7007 *go);
/* go7007-fw.c */
int go7007_construct_fw_image(struct go7007 *go, u8 **fw, int *fwlen);
/* go7007-i2c.c */
int go7007_i2c_init(struct go7007 *go);
int go7007_i2c_remove(struct go7007 *go);
/* go7007-v4l2.c */
int go7007_v4l2_init(struct go7007 *go);
void go7007_v4l2_remove(struct go7007 *go);
/* snd-go7007.c */
int go7007_snd_init(struct go7007 *go);
int go7007_snd_remove(struct go7007 *go);

1229
drivers/staging/go7007/go7007-usb.c Normal file
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1499
drivers/staging/go7007/go7007-v4l2.c Normal file
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114
drivers/staging/go7007/go7007.h Normal file
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@ -0,0 +1,114 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and the associated README documentation file (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
/* DEPRECATED -- use V4L2_PIX_FMT_MPEG and then call GO7007IOC_S_MPEG_PARAMS
* to select between MPEG1, MPEG2, and MPEG4 */
#define V4L2_PIX_FMT_MPEG4 v4l2_fourcc('M', 'P', 'G', '4') /* MPEG4 */
/* These will be replaced with a better interface
* soon, so don't get too attached to them */
#define GO7007IOC_S_BITRATE _IOW('V', BASE_VIDIOC_PRIVATE + 0, int)
#define GO7007IOC_G_BITRATE _IOR('V', BASE_VIDIOC_PRIVATE + 1, int)
enum go7007_aspect_ratio {
GO7007_ASPECT_RATIO_1_1 = 0,
GO7007_ASPECT_RATIO_4_3_NTSC = 1,
GO7007_ASPECT_RATIO_4_3_PAL = 2,
GO7007_ASPECT_RATIO_16_9_NTSC = 3,
GO7007_ASPECT_RATIO_16_9_PAL = 4,
};
/* Used to set generic compression parameters */
struct go7007_comp_params {
__u32 gop_size;
__u32 max_b_frames;
enum go7007_aspect_ratio aspect_ratio;
__u32 flags;
__u32 reserved[8];
};
#define GO7007_COMP_CLOSED_GOP 0x00000001
#define GO7007_COMP_OMIT_SEQ_HEADER 0x00000002
enum go7007_mpeg_video_standard {
GO7007_MPEG_VIDEO_MPEG1 = 0,
GO7007_MPEG_VIDEO_MPEG2 = 1,
GO7007_MPEG_VIDEO_MPEG4 = 2,
};
/* Used to set parameters for V4L2_PIX_FMT_MPEG format */
struct go7007_mpeg_params {
enum go7007_mpeg_video_standard mpeg_video_standard;
__u32 flags;
__u32 pali;
__u32 reserved[8];
};
#define GO7007_MPEG_FORCE_DVD_MODE 0x00000001
#define GO7007_MPEG_OMIT_GOP_HEADER 0x00000002
#define GO7007_MPEG_REPEAT_SEQHEADER 0x00000004
#define GO7007_MPEG_PROFILE(format, pali) (((format)<<24)|(pali))
#define GO7007_MPEG2_PROFILE_MAIN_MAIN GO7007_MPEG_PROFILE(2, 0x48)
#define GO7007_MPEG4_PROFILE_S_L0 GO7007_MPEG_PROFILE(4, 0x08)
#define GO7007_MPEG4_PROFILE_S_L1 GO7007_MPEG_PROFILE(4, 0x01)
#define GO7007_MPEG4_PROFILE_S_L2 GO7007_MPEG_PROFILE(4, 0x02)
#define GO7007_MPEG4_PROFILE_S_L3 GO7007_MPEG_PROFILE(4, 0x03)
#define GO7007_MPEG4_PROFILE_ARTS_L1 GO7007_MPEG_PROFILE(4, 0x91)
#define GO7007_MPEG4_PROFILE_ARTS_L2 GO7007_MPEG_PROFILE(4, 0x92)
#define GO7007_MPEG4_PROFILE_ARTS_L3 GO7007_MPEG_PROFILE(4, 0x93)
#define GO7007_MPEG4_PROFILE_ARTS_L4 GO7007_MPEG_PROFILE(4, 0x94)
#define GO7007_MPEG4_PROFILE_AS_L0 GO7007_MPEG_PROFILE(4, 0xf0)
#define GO7007_MPEG4_PROFILE_AS_L1 GO7007_MPEG_PROFILE(4, 0xf1)
#define GO7007_MPEG4_PROFILE_AS_L2 GO7007_MPEG_PROFILE(4, 0xf2)
#define GO7007_MPEG4_PROFILE_AS_L3 GO7007_MPEG_PROFILE(4, 0xf3)
#define GO7007_MPEG4_PROFILE_AS_L4 GO7007_MPEG_PROFILE(4, 0xf4)
#define GO7007_MPEG4_PROFILE_AS_L5 GO7007_MPEG_PROFILE(4, 0xf5)
struct go7007_md_params {
__u16 region;
__u16 trigger;
__u16 pixel_threshold;
__u16 motion_threshold;
__u32 reserved[8];
};
struct go7007_md_region {
__u16 region;
__u16 flags;
struct v4l2_clip *clips;
__u32 reserved[8];
};
#define GO7007IOC_S_MPEG_PARAMS _IOWR('V', BASE_VIDIOC_PRIVATE + 2, \
struct go7007_mpeg_params)
#define GO7007IOC_G_MPEG_PARAMS _IOR('V', BASE_VIDIOC_PRIVATE + 3, \
struct go7007_mpeg_params)
#define GO7007IOC_S_COMP_PARAMS _IOWR('V', BASE_VIDIOC_PRIVATE + 4, \
struct go7007_comp_params)
#define GO7007IOC_G_COMP_PARAMS _IOR('V', BASE_VIDIOC_PRIVATE + 5, \
struct go7007_comp_params)
#define GO7007IOC_S_MD_PARAMS _IOWR('V', BASE_VIDIOC_PRIVATE + 6, \
struct go7007_md_params)
#define GO7007IOC_G_MD_PARAMS _IOR('V', BASE_VIDIOC_PRIVATE + 7, \
struct go7007_md_params)
#define GO7007IOC_S_MD_REGION _IOW('V', BASE_VIDIOC_PRIVATE + 8, \
struct go7007_md_region)

484
drivers/staging/go7007/saa7134-go7007.c Normal file
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@ -0,0 +1,484 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/usb.h>
#include <linux/i2c.h>
#include <asm/byteorder.h>
#include <media/audiochip.h>
#include "saa7134-reg.h"
#include "saa7134.h"
#include "go7007-priv.h"
#define GO7007_HPI_DEBUG
enum hpi_address {
HPI_ADDR_VIDEO_BUFFER = 0xe4,
HPI_ADDR_INIT_BUFFER = 0xea,
HPI_ADDR_INTR_RET_VALUE = 0xee,
HPI_ADDR_INTR_RET_DATA = 0xec,
HPI_ADDR_INTR_STATUS = 0xf4,
HPI_ADDR_INTR_WR_PARAM = 0xf6,
HPI_ADDR_INTR_WR_INDEX = 0xf8,
};
enum gpio_command {
GPIO_COMMAND_RESET = 0x00, /* 000b */
GPIO_COMMAND_REQ1 = 0x04, /* 001b */
GPIO_COMMAND_WRITE = 0x20, /* 010b */
GPIO_COMMAND_REQ2 = 0x24, /* 011b */
GPIO_COMMAND_READ = 0x80, /* 100b */
GPIO_COMMAND_VIDEO = 0x84, /* 101b */
GPIO_COMMAND_IDLE = 0xA0, /* 110b */
GPIO_COMMAND_ADDR = 0xA4, /* 111b */
};
struct saa7134_go7007 {
struct saa7134_dev *dev;
u8 *top;
u8 *bottom;
dma_addr_t top_dma;
dma_addr_t bottom_dma;
};
static struct go7007_board_info board_voyager = {
.firmware = "go7007tv.bin",
.flags = 0,
.sensor_flags = GO7007_SENSOR_656 |
GO7007_SENSOR_VALID_ENABLE |
GO7007_SENSOR_TV |
GO7007_SENSOR_VBI,
.audio_flags = GO7007_AUDIO_I2S_MODE_1 |
GO7007_AUDIO_WORD_16,
.audio_rate = 48000,
.audio_bclk_div = 8,
.audio_main_div = 2,
.hpi_buffer_cap = 7,
.num_inputs = 1,
.inputs = {
{
.name = "SAA7134",
},
},
};
/********************* Driver for GPIO HPI interface *********************/
static int gpio_write(struct saa7134_dev *dev, u8 addr, u16 data)
{
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
/* Write HPI address */
saa_writeb(SAA7134_GPIO_GPSTATUS0, addr);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Write low byte */
saa_writeb(SAA7134_GPIO_GPSTATUS0, data & 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Write high byte */
saa_writeb(SAA7134_GPIO_GPSTATUS0, data >> 8);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
return 0;
}
static int gpio_read(struct saa7134_dev *dev, u8 addr, u16 *data)
{
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
/* Write HPI address */
saa_writeb(SAA7134_GPIO_GPSTATUS0, addr);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
saa_writeb(SAA7134_GPIO_GPMODE0, 0x00);
/* Read low byte */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_READ);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
*data = saa_readb(SAA7134_GPIO_GPSTATUS0);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
/* Read high byte */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_READ);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
*data |= saa_readb(SAA7134_GPIO_GPSTATUS0) << 8;
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
return 0;
}
static int saa7134_go7007_interface_reset(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
u32 status;
u16 intr_val, intr_data;
int count = 20;
saa_clearb(SAA7134_TS_PARALLEL, 0x80); /* Disable TS interface */
saa_writeb(SAA7134_GPIO_GPMODE2, 0xa4);
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_RESET);
msleep(1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ2);
msleep(10);
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
status = saa_readb(SAA7134_GPIO_GPSTATUS2);
/*printk(KERN_DEBUG "status is %s\n", status & 0x40 ? "OK" : "not OK"); */
/* enter command mode...(?) */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ1);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_REQ2);
do {
saa_clearb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
saa_setb(SAA7134_GPIO_GPMODE3, SAA7134_GPIO_GPRESCAN);
status = saa_readb(SAA7134_GPIO_GPSTATUS2);
/*printk(KERN_INFO "gpio is %08x\n", saa_readl(SAA7134_GPIO_GPSTATUS0 >> 2)); */
} while (--count > 0);
/* Wait for an interrupt to indicate successful hardware reset */
if (go7007_read_interrupt(go, &intr_val, &intr_data) < 0 ||
(intr_val & ~0x1) != 0x55aa) {
printk(KERN_ERR
"saa7134-go7007: unable to reset the GO7007\n");
return -1;
}
return 0;
}
static int saa7134_go7007_write_interrupt(struct go7007 *go, int addr, int data)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
int i;
u16 status_reg;
#ifdef GO7007_HPI_DEBUG
printk(KERN_DEBUG
"saa7134-go7007: WriteInterrupt: %04x %04x\n", addr, data);
#endif
for (i = 0; i < 100; ++i) {
gpio_read(dev, HPI_ADDR_INTR_STATUS, &status_reg);
if (!(status_reg & 0x0010))
break;
msleep(10);
}
if (i == 100) {
printk(KERN_ERR
"saa7134-go7007: device is hung, status reg = 0x%04x\n",
status_reg);
return -1;
}
gpio_write(dev, HPI_ADDR_INTR_WR_PARAM, data);
gpio_write(dev, HPI_ADDR_INTR_WR_INDEX, addr);
return 0;
}
static int saa7134_go7007_read_interrupt(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
/* XXX we need to wait if there is no interrupt available */
go->interrupt_available = 1;
gpio_read(dev, HPI_ADDR_INTR_RET_VALUE, &go->interrupt_value);
gpio_read(dev, HPI_ADDR_INTR_RET_DATA, &go->interrupt_data);
#ifdef GO7007_HPI_DEBUG
printk(KERN_DEBUG "saa7134-go7007: ReadInterrupt: %04x %04x\n",
go->interrupt_value, go->interrupt_data);
#endif
return 0;
}
static void saa7134_go7007_irq_ts_done(struct saa7134_dev *dev,
unsigned long status)
{
struct go7007 *go = video_get_drvdata(dev->empress_dev);
struct saa7134_go7007 *saa = go->hpi_context;
if (!go->streaming)
return;
if (0 != (status & 0x000f0000))
printk(KERN_DEBUG "saa7134-go7007: irq: lost %ld\n",
(status >> 16) & 0x0f);
if (status & 0x100000) {
dma_sync_single(&dev->pci->dev,
saa->bottom_dma, PAGE_SIZE, DMA_FROM_DEVICE);
go7007_parse_video_stream(go, saa->bottom, PAGE_SIZE);
saa_writel(SAA7134_RS_BA2(5), cpu_to_le32(saa->bottom_dma));
} else {
dma_sync_single(&dev->pci->dev,
saa->top_dma, PAGE_SIZE, DMA_FROM_DEVICE);
go7007_parse_video_stream(go, saa->top, PAGE_SIZE);
saa_writel(SAA7134_RS_BA1(5), cpu_to_le32(saa->top_dma));
}
}
static int saa7134_go7007_stream_start(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
saa->top_dma = dma_map_page(&dev->pci->dev, virt_to_page(saa->top),
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (!saa->top_dma)
return -ENOMEM;
saa->bottom_dma = dma_map_page(&dev->pci->dev,
virt_to_page(saa->bottom),
0, PAGE_SIZE, DMA_FROM_DEVICE);
if (!saa->bottom_dma) {
dma_unmap_page(&dev->pci->dev, saa->top_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
return -ENOMEM;
}
saa_writel(SAA7134_VIDEO_PORT_CTRL0 >> 2, 0xA300B000);
saa_writel(SAA7134_VIDEO_PORT_CTRL4 >> 2, 0x40000200);
/* Set HPI interface for video */
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS0, HPI_ADDR_VIDEO_BUFFER);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPMODE0, 0x00);
/* Enable TS interface */
saa_writeb(SAA7134_TS_PARALLEL, 0xe6);
/* Reset TS interface */
saa_setb(SAA7134_TS_SERIAL1, 0x01);
saa_clearb(SAA7134_TS_SERIAL1, 0x01);
/* Set up transfer block size */
saa_writeb(SAA7134_TS_PARALLEL_SERIAL, 128 - 1);
saa_writeb(SAA7134_TS_DMA0, (PAGE_SIZE >> 7) - 1);
saa_writeb(SAA7134_TS_DMA1, 0);
saa_writeb(SAA7134_TS_DMA2, 0);
/* Enable video streaming mode */
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_VIDEO);
saa_writel(SAA7134_RS_BA1(5), cpu_to_le32(saa->top_dma));
saa_writel(SAA7134_RS_BA2(5), cpu_to_le32(saa->bottom_dma));
saa_writel(SAA7134_RS_PITCH(5), 128);
saa_writel(SAA7134_RS_CONTROL(5), SAA7134_RS_CONTROL_BURST_MAX);
/* Enable TS FIFO */
saa_setl(SAA7134_MAIN_CTRL, SAA7134_MAIN_CTRL_TE5);
/* Enable DMA IRQ */
saa_setl(SAA7134_IRQ1,
SAA7134_IRQ1_INTE_RA2_1 | SAA7134_IRQ1_INTE_RA2_0);
return 0;
}
static int saa7134_go7007_stream_stop(struct go7007 *go)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
/* Shut down TS FIFO */
saa_clearl(SAA7134_MAIN_CTRL, SAA7134_MAIN_CTRL_TE5);
/* Disable DMA IRQ */
saa_clearl(SAA7134_IRQ1,
SAA7134_IRQ1_INTE_RA2_1 | SAA7134_IRQ1_INTE_RA2_0);
/* Disable TS interface */
saa_clearb(SAA7134_TS_PARALLEL, 0x80);
dma_unmap_page(&dev->pci->dev, saa->top_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
dma_unmap_page(&dev->pci->dev, saa->bottom_dma, PAGE_SIZE,
DMA_FROM_DEVICE);
return 0;
}
static int saa7134_go7007_send_firmware(struct go7007 *go, u8 *data, int len)
{
struct saa7134_go7007 *saa = go->hpi_context;
struct saa7134_dev *dev = saa->dev;
u16 status_reg;
int i;
#ifdef GO7007_HPI_DEBUG
printk(KERN_DEBUG "saa7134-go7007: DownloadBuffer "
"sending %d bytes\n", len);
#endif
while (len > 0) {
i = len > 64 ? 64 : len;
saa_writeb(SAA7134_GPIO_GPMODE0, 0xff);
saa_writeb(SAA7134_GPIO_GPSTATUS0, HPI_ADDR_INIT_BUFFER);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_ADDR);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
while (i-- > 0) {
saa_writeb(SAA7134_GPIO_GPSTATUS0, *data);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_WRITE);
saa_writeb(SAA7134_GPIO_GPSTATUS2, GPIO_COMMAND_IDLE);
++data;
--len;
}
for (i = 0; i < 100; ++i) {
gpio_read(dev, HPI_ADDR_INTR_STATUS, &status_reg);
if (!(status_reg & 0x0002))
break;
}
if (i == 100) {
printk(KERN_ERR "saa7134-go7007: device is hung, "
"status reg = 0x%04x\n", status_reg);
return -1;
}
}
return 0;
}
static struct go7007_hpi_ops saa7134_go7007_hpi_ops = {
.interface_reset = saa7134_go7007_interface_reset,
.write_interrupt = saa7134_go7007_write_interrupt,
.read_interrupt = saa7134_go7007_read_interrupt,
.stream_start = saa7134_go7007_stream_start,
.stream_stop = saa7134_go7007_stream_stop,
.send_firmware = saa7134_go7007_send_firmware,
};
/********************* Add/remove functions *********************/
static int saa7134_go7007_init(struct saa7134_dev *dev)
{
struct go7007 *go;
struct saa7134_go7007 *saa;
printk(KERN_DEBUG "saa7134-go7007: probing new SAA713X board\n");
saa = kmalloc(sizeof(struct saa7134_go7007), GFP_KERNEL);
if (saa == NULL)
return -ENOMEM;
memset(saa, 0, sizeof(struct saa7134_go7007));
/* Allocate a couple pages for receiving the compressed stream */
saa->top = (u8 *)get_zeroed_page(GFP_KERNEL);
if (!saa->top)
goto allocfail;
saa->bottom = (u8 *)get_zeroed_page(GFP_KERNEL);
if (!saa->bottom)
goto allocfail;
go = go7007_alloc(&board_voyager, &dev->pci->dev);
if (go == NULL)
goto allocfail;
go->board_id = GO7007_BOARDID_PCI_VOYAGER;
strncpy(go->name, saa7134_boards[dev->board].name, sizeof(go->name));
go->hpi_ops = &saa7134_go7007_hpi_ops;
go->hpi_context = saa;
saa->dev = dev;
/* Boot the GO7007 */
if (go7007_boot_encoder(go, go->board_info->flags &
GO7007_BOARD_USE_ONBOARD_I2C) < 0)
goto initfail;
/* Do any final GO7007 initialization, then register the
* V4L2 and ALSA interfaces */
if (go7007_register_encoder(go) < 0)
goto initfail;
dev->empress_dev = go->video_dev;
video_set_drvdata(dev->empress_dev, go);
go->status = STATUS_ONLINE;
return 0;
initfail:
go->status = STATUS_SHUTDOWN;
return 0;
allocfail:
if (saa->top)
free_page((unsigned long)saa->top);
if (saa->bottom)
free_page((unsigned long)saa->bottom);
kfree(saa);
return -ENOMEM;
}
static int saa7134_go7007_fini(struct saa7134_dev *dev)
{
struct go7007 *go;
struct saa7134_go7007 *saa;
if (NULL == dev->empress_dev)
return 0;
go = video_get_drvdata(dev->empress_dev);
saa = go->hpi_context;
go->status = STATUS_SHUTDOWN;
free_page((unsigned long)saa->top);
free_page((unsigned long)saa->bottom);
kfree(saa);
go7007_remove(go);
dev->empress_dev = NULL;
return 0;
}
static struct saa7134_mpeg_ops saa7134_go7007_ops = {
.type = SAA7134_MPEG_GO7007,
.init = saa7134_go7007_init,
.fini = saa7134_go7007_fini,
.irq_ts_done = saa7134_go7007_irq_ts_done,
};
static int __init saa7134_go7007_mod_init(void)
{
return saa7134_ts_register(&saa7134_go7007_ops);
}
static void __exit saa7134_go7007_mod_cleanup(void)
{
saa7134_ts_unregister(&saa7134_go7007_ops);
}
module_init(saa7134_go7007_mod_init);
module_exit(saa7134_go7007_mod_cleanup);
MODULE_LICENSE("GPL v2");

305
drivers/staging/go7007/snd-go7007.c Normal file
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@ -0,0 +1,305 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/version.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/sched.h>
#include <linux/vmalloc.h>
#include <linux/time.h>
#include <linux/mm.h>
#include <linux/i2c.h>
#include <linux/semaphore.h>
#include <linux/uaccess.h>
#include <asm/system.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/initval.h>
#include "go7007-priv.h"
static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
module_param_array(index, int, NULL, 0444);
module_param_array(id, charp, NULL, 0444);
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for the go7007 audio driver");
MODULE_PARM_DESC(id, "ID string for the go7007 audio driver");
MODULE_PARM_DESC(enable, "Enable for the go7007 audio driver");
struct go7007_snd {
struct snd_card *card;
struct snd_pcm *pcm;
struct snd_pcm_substream *substream;
spinlock_t lock;
int w_idx;
int hw_ptr;
int avail;
int capturing;
};
static struct snd_pcm_hardware go7007_snd_capture_hw = {
.info = (SNDRV_PCM_INFO_MMAP |
SNDRV_PCM_INFO_INTERLEAVED |
SNDRV_PCM_INFO_BLOCK_TRANSFER |
SNDRV_PCM_INFO_MMAP_VALID),
.formats = SNDRV_PCM_FMTBIT_S16_LE,
.rates = SNDRV_PCM_RATE_48000,
.rate_min = 48000,
.rate_max = 48000,
.channels_min = 2,
.channels_max = 2,
.buffer_bytes_max = (128*1024),
.period_bytes_min = 4096,
.period_bytes_max = (128*1024),
.periods_min = 1,
.periods_max = 32,
};
static void parse_audio_stream_data(struct go7007 *go, u8 *buf, int length)
{
struct go7007_snd *gosnd = go->snd_context;
struct snd_pcm_runtime *runtime = gosnd->substream->runtime;
int frames = bytes_to_frames(runtime, length);
spin_lock(&gosnd->lock);
gosnd->hw_ptr += frames;
if (gosnd->hw_ptr >= runtime->buffer_size)
gosnd->hw_ptr -= runtime->buffer_size;
gosnd->avail += frames;
spin_unlock(&gosnd->lock);
if (gosnd->w_idx + length > runtime->dma_bytes) {
int cpy = runtime->dma_bytes - gosnd->w_idx;
memcpy(runtime->dma_area + gosnd->w_idx, buf, cpy);
length -= cpy;
buf += cpy;
gosnd->w_idx = 0;
}
memcpy(runtime->dma_area + gosnd->w_idx, buf, length);
gosnd->w_idx += length;
spin_lock(&gosnd->lock);
if (gosnd->avail < runtime->period_size) {
spin_unlock(&gosnd->lock);
return;
}
gosnd->avail -= runtime->period_size;
spin_unlock(&gosnd->lock);
if (gosnd->capturing)
snd_pcm_period_elapsed(gosnd->substream);
}
static int go7007_snd_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *hw_params)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
unsigned int bytes;
bytes = params_buffer_bytes(hw_params);
if (substream->runtime->dma_bytes > 0)
vfree(substream->runtime->dma_area);
substream->runtime->dma_bytes = 0;
substream->runtime->dma_area = vmalloc(bytes);
if (substream->runtime->dma_area == NULL)
return -ENOMEM;
substream->runtime->dma_bytes = bytes;
go->audio_deliver = parse_audio_stream_data;
return 0;
}
static int go7007_snd_hw_free(struct snd_pcm_substream *substream)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
go->audio_deliver = NULL;
if (substream->runtime->dma_bytes > 0)
vfree(substream->runtime->dma_area);
substream->runtime->dma_bytes = 0;
return 0;
}
static int go7007_snd_capture_open(struct snd_pcm_substream *substream)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
struct go7007_snd *gosnd = go->snd_context;
unsigned long flags;
int r;
spin_lock_irqsave(&gosnd->lock, flags);
if (gosnd->substream == NULL) {
gosnd->substream = substream;
substream->runtime->hw = go7007_snd_capture_hw;
r = 0;
} else
r = -EBUSY;
spin_unlock_irqrestore(&gosnd->lock, flags);
return r;
}
static int go7007_snd_capture_close(struct snd_pcm_substream *substream)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
struct go7007_snd *gosnd = go->snd_context;
gosnd->substream = NULL;
return 0;
}
static int go7007_snd_pcm_prepare(struct snd_pcm_substream *substream)
{
return 0;
}
static int go7007_snd_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
struct go7007_snd *gosnd = go->snd_context;
switch (cmd) {
case SNDRV_PCM_TRIGGER_START:
/* Just set a flag to indicate we should signal ALSA when
* sound comes in */
gosnd->capturing = 1;
return 0;
case SNDRV_PCM_TRIGGER_STOP:
gosnd->hw_ptr = gosnd->w_idx = gosnd->avail = 0;
gosnd->capturing = 0;
return 0;
default:
return -EINVAL;
}
}
static snd_pcm_uframes_t go7007_snd_pcm_pointer(struct snd_pcm_substream *substream)
{
struct go7007 *go = snd_pcm_substream_chip(substream);
struct go7007_snd *gosnd = go->snd_context;
return gosnd->hw_ptr;
}
static struct page *go7007_snd_pcm_page(struct snd_pcm_substream *substream,
unsigned long offset)
{
return vmalloc_to_page(substream->runtime->dma_area + offset);
}
static struct snd_pcm_ops go7007_snd_capture_ops = {
.open = go7007_snd_capture_open,
.close = go7007_snd_capture_close,
.ioctl = snd_pcm_lib_ioctl,
.hw_params = go7007_snd_hw_params,
.hw_free = go7007_snd_hw_free,
.prepare = go7007_snd_pcm_prepare,
.trigger = go7007_snd_pcm_trigger,
.pointer = go7007_snd_pcm_pointer,
.page = go7007_snd_pcm_page,
};
static int go7007_snd_free(struct snd_device *device)
{
struct go7007 *go = device->device_data;
kfree(go->snd_context);
go->snd_context = NULL;
if (--go->ref_count == 0)
kfree(go);
return 0;
}
static struct snd_device_ops go7007_snd_device_ops = {
.dev_free = go7007_snd_free,
};
int go7007_snd_init(struct go7007 *go)
{
static int dev;
struct go7007_snd *gosnd;
int ret = 0;
if (dev >= SNDRV_CARDS)
return -ENODEV;
if (!enable[dev]) {
dev++;
return -ENOENT;
}
gosnd = kmalloc(sizeof(struct go7007_snd), GFP_KERNEL);
if (gosnd == NULL)
return -ENOMEM;
spin_lock_init(&gosnd->lock);
gosnd->hw_ptr = gosnd->w_idx = gosnd->avail = 0;
gosnd->capturing = 0;
gosnd->card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
if (gosnd->card == NULL) {
kfree(gosnd);
return -ENOMEM;
}
ret = snd_device_new(gosnd->card, SNDRV_DEV_LOWLEVEL, go,
&go7007_snd_device_ops);
if (ret < 0) {
kfree(gosnd);
return ret;
}
snd_card_set_dev(gosnd->card, go->dev);
ret = snd_pcm_new(gosnd->card, "go7007", 0, 0, 1, &gosnd->pcm);
if (ret < 0) {
snd_card_free(gosnd->card);
kfree(gosnd);
return ret;
}
strncpy(gosnd->card->driver, "go7007", sizeof(gosnd->card->driver));
strncpy(gosnd->card->shortname, go->name, sizeof(gosnd->card->driver));
strncpy(gosnd->card->longname, gosnd->card->shortname,
sizeof(gosnd->card->longname));
gosnd->pcm->private_data = go;
snd_pcm_set_ops(gosnd->pcm, SNDRV_PCM_STREAM_CAPTURE,
&go7007_snd_capture_ops);
ret = snd_card_register(gosnd->card);
if (ret < 0) {
snd_card_free(gosnd->card);
kfree(gosnd);
return ret;
}
gosnd->substream = NULL;
go->snd_context = gosnd;
++dev;
++go->ref_count;
return 0;
}
EXPORT_SYMBOL(go7007_snd_init);
int go7007_snd_remove(struct go7007 *go)
{
struct go7007_snd *gosnd = go->snd_context;
snd_card_disconnect(gosnd->card);
snd_card_free_when_closed(gosnd->card);
return 0;
}
EXPORT_SYMBOL(go7007_snd_remove);
MODULE_LICENSE("GPL v2");

55
drivers/staging/go7007/wis-i2c.h Normal file
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@ -0,0 +1,55 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
/* Temporary I2C IDs -- these need to be replaced with real registered IDs */
#define I2C_DRIVERID_WIS_SAA7115 0xf0f0
#define I2C_DRIVERID_WIS_UDA1342 0xf0f1
#define I2C_DRIVERID_WIS_SONY_TUNER 0xf0f2
#define I2C_DRIVERID_WIS_TW9903 0xf0f3
#define I2C_DRIVERID_WIS_SAA7113 0xf0f4
#define I2C_DRIVERID_WIS_OV7640 0xf0f5
#define I2C_DRIVERID_WIS_TW2804 0xf0f6
#define I2C_ALGO_GO7007 0xf00000
#define I2C_ALGO_GO7007_USB 0xf10000
/* Flag to indicate that the client needs to be accessed with SCCB semantics */
/* We re-use the I2C_M_TEN value so the flag passes through the masks in the
* core I2C code. Major kludge, but the I2C layer ain't exactly flexible. */
#define I2C_CLIENT_SCCB 0x10
typedef int (*found_proc) (struct i2c_adapter *, int, int);
int wis_i2c_add_driver(unsigned int id, found_proc found_proc);
void wis_i2c_del_driver(found_proc found_proc);
int wis_i2c_probe_device(struct i2c_adapter *adapter,
unsigned int id, int addr);
/* Definitions for new video decoder commands */
struct video_decoder_resolution {
unsigned int width;
unsigned int height;
};
#define DECODER_SET_RESOLUTION _IOW('d', 200, struct video_decoder_resolution)
#define DECODER_SET_CHANNEL _IOW('d', 201, int)
/* Sony tuner types */
#define TUNER_SONY_BTF_PG472Z 200
#define TUNER_SONY_BTF_PK467Z 201
#define TUNER_SONY_BTF_PB463Z 202

130
drivers/staging/go7007/wis-ov7640.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include "wis-i2c.h"
struct wis_ov7640 {
int brightness;
int contrast;
int saturation;
int hue;
};
static u8 initial_registers[] =
{
0x12, 0x80,
0x12, 0x54,
0x14, 0x24,
0x15, 0x01,
0x28, 0x20,
0x75, 0x82,
0xFF, 0xFF, /* Terminator (reg 0xFF is unused) */
};
static int write_regs(struct i2c_client *client, u8 *regs)
{
int i;
for (i = 0; regs[i] != 0xFF; i += 2)
if (i2c_smbus_write_byte_data(client, regs[i], regs[i + 1]) < 0)
return -1;
return 0;
}
static struct i2c_driver wis_ov7640_driver;
static struct i2c_client wis_ov7640_client_templ = {
.name = "OV7640 (WIS)",
.driver = &wis_ov7640_driver,
};
static int wis_ov7640_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_ov7640_client_templ,
sizeof(wis_ov7640_client_templ));
client->adapter = adapter;
client->addr = addr;
client->flags = I2C_CLIENT_SCCB;
printk(KERN_DEBUG
"wis-ov7640: initializing OV7640 at address %d on %s\n",
addr, adapter->name);
if (write_regs(client, initial_registers) < 0) {
printk(KERN_ERR "wis-ov7640: error initializing OV7640\n");
kfree(client);
return 0;
}
i2c_attach_client(client);
return 0;
}
static int wis_ov7640_detach(struct i2c_client *client)
{
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
return 0;
}
static struct i2c_driver wis_ov7640_driver = {
.driver = {
.name = "WIS OV7640 I2C driver",
},
.id = I2C_DRIVERID_WIS_OV7640,
.detach_client = wis_ov7640_detach,
};
static int __init wis_ov7640_init(void)
{
int r;
r = i2c_add_driver(&wis_ov7640_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_ov7640_driver.id, wis_ov7640_detect);
}
static void __exit wis_ov7640_cleanup(void)
{
wis_i2c_del_driver(wis_ov7640_detect);
i2c_del_driver(&wis_ov7640_driver);
}
module_init(wis_ov7640_init);
module_exit(wis_ov7640_cleanup);
MODULE_LICENSE("GPL v2");

358
drivers/staging/go7007/wis-saa7113.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/ioctl.h>
#include "wis-i2c.h"
struct wis_saa7113 {
int norm;
int brightness;
int contrast;
int saturation;
int hue;
};
static u8 initial_registers[] =
{
0x01, 0x08,
0x02, 0xc0,
0x03, 0x33,
0x04, 0x00,
0x05, 0x00,
0x06, 0xe9,
0x07, 0x0d,
0x08, 0xd8,
0x09, 0x40,
0x0a, 0x80,
0x0b, 0x47,
0x0c, 0x40,
0x0d, 0x00,
0x0e, 0x01,
0x0f, 0x2a,
0x10, 0x40,
0x11, 0x0c,
0x12, 0xfe,
0x13, 0x00,
0x14, 0x00,
0x15, 0x04,
0x16, 0x00,
0x17, 0x00,
0x18, 0x00,
0x19, 0x00,
0x1a, 0x00,
0x1b, 0x00,
0x1c, 0x00,
0x1d, 0x00,
0x1e, 0x00,
0x1f, 0xc8,
0x40, 0x00,
0x41, 0xff,
0x42, 0xff,
0x43, 0xff,
0x44, 0xff,
0x45, 0xff,
0x46, 0xff,
0x47, 0xff,
0x48, 0xff,
0x49, 0xff,
0x4a, 0xff,
0x4b, 0xff,
0x4c, 0xff,
0x4d, 0xff,
0x4e, 0xff,
0x4f, 0xff,
0x50, 0xff,
0x51, 0xff,
0x52, 0xff,
0x53, 0xff,
0x54, 0xff,
0x55, 0xff,
0x56, 0xff,
0x57, 0xff,
0x58, 0x00,
0x59, 0x54,
0x5a, 0x07,
0x5b, 0x83,
0x5c, 0x00,
0x5d, 0x00,
0x5e, 0x00,
0x5f, 0x00,
0x60, 0x00,
0x61, 0x00,
0x00, 0x00, /* Terminator (reg 0x00 is read-only) */
};
static int write_reg(struct i2c_client *client, u8 reg, u8 value)
{
return i2c_smbus_write_byte_data(client, reg, value);
}
static int write_regs(struct i2c_client *client, u8 *regs)
{
int i;
for (i = 0; regs[i] != 0x00; i += 2)
if (i2c_smbus_write_byte_data(client, regs[i], regs[i + 1]) < 0)
return -1;
return 0;
}
static int wis_saa7113_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
struct wis_saa7113 *dec = i2c_get_clientdata(client);
switch (cmd) {
case VIDIOC_S_INPUT:
{
int *input = arg;
i2c_smbus_write_byte_data(client, 0x02, 0xC0 | *input);
i2c_smbus_write_byte_data(client, 0x09,
*input < 6 ? 0x40 : 0x80);
break;
}
case VIDIOC_S_STD:
{
v4l2_std_id *input = arg;
dec->norm = *input;
if (dec->norm & V4L2_STD_NTSC) {
write_reg(client, 0x0e, 0x01);
write_reg(client, 0x10, 0x40);
} else if (dec->norm & V4L2_STD_PAL) {
write_reg(client, 0x0e, 0x01);
write_reg(client, 0x10, 0x48);
} else if (dec->norm * V4L2_STD_SECAM) {
write_reg(client, 0x0e, 0x50);
write_reg(client, 0x10, 0x48);
}
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Brightness", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
case V4L2_CID_CONTRAST:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Contrast", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 71;
ctrl->flags = 0;
break;
case V4L2_CID_SATURATION:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Saturation", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 64;
ctrl->flags = 0;
break;
case V4L2_CID_HUE:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Hue", sizeof(ctrl->name));
ctrl->minimum = -128;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 0;
ctrl->flags = 0;
break;
}
break;
}
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
if (ctrl->value > 255)
dec->brightness = 255;
else if (ctrl->value < 0)
dec->brightness = 0;
else
dec->brightness = ctrl->value;
write_reg(client, 0x0a, dec->brightness);
break;
case V4L2_CID_CONTRAST:
if (ctrl->value > 127)
dec->contrast = 127;
else if (ctrl->value < 0)
dec->contrast = 0;
else
dec->contrast = ctrl->value;
write_reg(client, 0x0b, dec->contrast);
break;
case V4L2_CID_SATURATION:
if (ctrl->value > 127)
dec->saturation = 127;
else if (ctrl->value < 0)
dec->saturation = 0;
else
dec->saturation = ctrl->value;
write_reg(client, 0x0c, dec->saturation);
break;
case V4L2_CID_HUE:
if (ctrl->value > 127)
dec->hue = 127;
else if (ctrl->value < -128)
dec->hue = -128;
else
dec->hue = ctrl->value;
write_reg(client, 0x0d, dec->hue);
break;
}
break;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->value = dec->brightness;
break;
case V4L2_CID_CONTRAST:
ctrl->value = dec->contrast;
break;
case V4L2_CID_SATURATION:
ctrl->value = dec->saturation;
break;
case V4L2_CID_HUE:
ctrl->value = dec->hue;
break;
}
break;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_saa7113_driver;
static struct i2c_client wis_saa7113_client_templ = {
.name = "SAA7113 (WIS)",
.driver = &wis_saa7113_driver,
};
static int wis_saa7113_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
struct wis_saa7113 *dec;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_saa7113_client_templ,
sizeof(wis_saa7113_client_templ));
client->adapter = adapter;
client->addr = addr;
dec = kmalloc(sizeof(struct wis_saa7113), GFP_KERNEL);
if (dec == NULL) {
kfree(client);
return -ENOMEM;
}
dec->norm = V4L2_STD_NTSC;
dec->brightness = 128;
dec->contrast = 71;
dec->saturation = 64;
dec->hue = 0;
i2c_set_clientdata(client, dec);
printk(KERN_DEBUG
"wis-saa7113: initializing SAA7113 at address %d on %s\n",
addr, adapter->name);
if (write_regs(client, initial_registers) < 0) {
printk(KERN_ERR
"wis-saa7113: error initializing SAA7113\n");
kfree(client);
kfree(dec);
return 0;
}
i2c_attach_client(client);
return 0;
}
static int wis_saa7113_detach(struct i2c_client *client)
{
struct wis_saa7113 *dec = i2c_get_clientdata(client);
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
kfree(dec);
return 0;
}
static struct i2c_driver wis_saa7113_driver = {
.driver = {
.name = "WIS SAA7113 I2C driver",
},
.id = I2C_DRIVERID_WIS_SAA7113,
.detach_client = wis_saa7113_detach,
.command = wis_saa7113_command,
};
static int __init wis_saa7113_init(void)
{
int r;
r = i2c_add_driver(&wis_saa7113_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_saa7113_driver.id, wis_saa7113_detect);
}
static void __exit wis_saa7113_cleanup(void)
{
wis_i2c_del_driver(wis_saa7113_detect);
i2c_del_driver(&wis_saa7113_driver);
}
module_init(wis_saa7113_init);
module_exit(wis_saa7113_cleanup);
MODULE_LICENSE("GPL v2");

491
drivers/staging/go7007/wis-saa7115.c Normal file
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@ -0,0 +1,491 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/ioctl.h>
#include "wis-i2c.h"
struct wis_saa7115 {
int norm;
int brightness;
int contrast;
int saturation;
int hue;
};
static u8 initial_registers[] =
{
0x01, 0x08,
0x02, 0xc0,
0x03, 0x20,
0x04, 0x80,
0x05, 0x80,
0x06, 0xeb,
0x07, 0xe0,
0x08, 0xf0, /* always toggle FID */
0x09, 0x40,
0x0a, 0x80,
0x0b, 0x40,
0x0c, 0x40,
0x0d, 0x00,
0x0e, 0x03,
0x0f, 0x2a,
0x10, 0x0e,
0x11, 0x00,
0x12, 0x8d,
0x13, 0x00,
0x14, 0x00,
0x15, 0x11,
0x16, 0x01,
0x17, 0xda,
0x18, 0x40,
0x19, 0x80,
0x1a, 0x00,
0x1b, 0x42,
0x1c, 0xa9,
0x30, 0x66,
0x31, 0x90,
0x32, 0x01,
0x34, 0x00,
0x35, 0x00,
0x36, 0x20,
0x38, 0x03,
0x39, 0x20,
0x3a, 0x88,
0x40, 0x00,
0x41, 0xff,
0x42, 0xff,
0x43, 0xff,
0x44, 0xff,
0x45, 0xff,
0x46, 0xff,
0x47, 0xff,
0x48, 0xff,
0x49, 0xff,
0x4a, 0xff,
0x4b, 0xff,
0x4c, 0xff,
0x4d, 0xff,
0x4e, 0xff,
0x4f, 0xff,
0x50, 0xff,
0x51, 0xff,
0x52, 0xff,
0x53, 0xff,
0x54, 0xf4 /*0xff*/,
0x55, 0xff,
0x56, 0xff,
0x57, 0xff,
0x58, 0x40,
0x59, 0x47,
0x5a, 0x06 /*0x03*/,
0x5b, 0x83,
0x5d, 0x06,
0x5e, 0x00,
0x80, 0x30, /* window defined scaler operation, task A and B enabled */
0x81, 0x03, /* use scaler datapath generated V */
0x83, 0x00,
0x84, 0x00,
0x85, 0x00,
0x86, 0x45,
0x87, 0x31,
0x88, 0xc0,
0x90, 0x02, /* task A process top field */
0x91, 0x08,
0x92, 0x09,
0x93, 0x80,
0x94, 0x06,
0x95, 0x00,
0x96, 0xc0,
0x97, 0x02,
0x98, 0x12,
0x99, 0x00,
0x9a, 0xf2,
0x9b, 0x00,
0x9c, 0xd0,
0x9d, 0x02,
0x9e, 0xf2,
0x9f, 0x00,
0xa0, 0x01,
0xa1, 0x01,
0xa2, 0x01,
0xa4, 0x80,
0xa5, 0x40,
0xa6, 0x40,
0xa8, 0x00,
0xa9, 0x04,
0xaa, 0x00,
0xac, 0x00,
0xad, 0x02,
0xae, 0x00,
0xb0, 0x00,
0xb1, 0x04,
0xb2, 0x00,
0xb3, 0x04,
0xb4, 0x00,
0xb8, 0x00,
0xbc, 0x00,
0xc0, 0x03, /* task B process bottom field */
0xc1, 0x08,
0xc2, 0x09,
0xc3, 0x80,
0xc4, 0x06,
0xc5, 0x00,
0xc6, 0xc0,
0xc7, 0x02,
0xc8, 0x12,
0xc9, 0x00,
0xca, 0xf2,
0xcb, 0x00,
0xcc, 0xd0,
0xcd, 0x02,
0xce, 0xf2,
0xcf, 0x00,
0xd0, 0x01,
0xd1, 0x01,
0xd2, 0x01,
0xd4, 0x80,
0xd5, 0x40,
0xd6, 0x40,
0xd8, 0x00,
0xd9, 0x04,
0xda, 0x00,
0xdc, 0x00,
0xdd, 0x02,
0xde, 0x00,
0xe0, 0x00,
0xe1, 0x04,
0xe2, 0x00,
0xe3, 0x04,
0xe4, 0x00,
0xe8, 0x00,
0x88, 0xf0, /* End of original static list */
0x00, 0x00, /* Terminator (reg 0x00 is read-only) */
};
static int write_reg(struct i2c_client *client, u8 reg, u8 value)
{
return i2c_smbus_write_byte_data(client, reg, value);
}
static int write_regs(struct i2c_client *client, u8 *regs)
{
int i;
for (i = 0; regs[i] != 0x00; i += 2)
if (i2c_smbus_write_byte_data(client, regs[i], regs[i + 1]) < 0)
return -1;
return 0;
}
static int wis_saa7115_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
struct wis_saa7115 *dec = i2c_get_clientdata(client);
switch (cmd) {
case VIDIOC_S_INPUT:
{
int *input = arg;
i2c_smbus_write_byte_data(client, 0x02, 0xC0 | *input);
i2c_smbus_write_byte_data(client, 0x09,
*input < 6 ? 0x40 : 0xC0);
break;
}
case DECODER_SET_RESOLUTION:
{
struct video_decoder_resolution *res = arg;
/* Course-grained scaler */
int h_integer_scaler = res->width < 704 ? 704 / res->width : 1;
/* Fine-grained scaler to take care of remainder */
int h_scaling_increment = (704 / h_integer_scaler) *
1024 / res->width;
/* Fine-grained scaler only */
int v_scaling_increment = (dec->norm & V4L2_STD_NTSC ?
240 : 288) * 1024 / res->height;
u8 regs[] = {
0x88, 0xc0,
0x9c, res->width & 0xff,
0x9d, res->width >> 8,
0x9e, res->height & 0xff,
0x9f, res->height >> 8,
0xa0, h_integer_scaler,
0xa1, 1,
0xa2, 1,
0xa8, h_scaling_increment & 0xff,
0xa9, h_scaling_increment >> 8,
0xac, (h_scaling_increment / 2) & 0xff,
0xad, (h_scaling_increment / 2) >> 8,
0xb0, v_scaling_increment & 0xff,
0xb1, v_scaling_increment >> 8,
0xb2, v_scaling_increment & 0xff,
0xb3, v_scaling_increment >> 8,
0xcc, res->width & 0xff,
0xcd, res->width >> 8,
0xce, res->height & 0xff,
0xcf, res->height >> 8,
0xd0, h_integer_scaler,
0xd1, 1,
0xd2, 1,
0xd8, h_scaling_increment & 0xff,
0xd9, h_scaling_increment >> 8,
0xdc, (h_scaling_increment / 2) & 0xff,
0xdd, (h_scaling_increment / 2) >> 8,
0xe0, v_scaling_increment & 0xff,
0xe1, v_scaling_increment >> 8,
0xe2, v_scaling_increment & 0xff,
0xe3, v_scaling_increment >> 8,
0x88, 0xf0,
0, 0,
};
write_regs(client, regs);
break;
}
case VIDIOC_S_STD:
{
v4l2_std_id *input = arg;
u8 regs[] = {
0x88, 0xc0,
0x98, *input & V4L2_STD_NTSC ? 0x12 : 0x16,
0x9a, *input & V4L2_STD_NTSC ? 0xf2 : 0x20,
0x9b, *input & V4L2_STD_NTSC ? 0x00 : 0x01,
0xc8, *input & V4L2_STD_NTSC ? 0x12 : 0x16,
0xca, *input & V4L2_STD_NTSC ? 0xf2 : 0x20,
0xcb, *input & V4L2_STD_NTSC ? 0x00 : 0x01,
0x88, 0xf0,
0x30, *input & V4L2_STD_NTSC ? 0x66 : 0x00,
0x31, *input & V4L2_STD_NTSC ? 0x90 : 0xe0,
0, 0,
};
write_regs(client, regs);
dec->norm = *input;
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Brightness", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
case V4L2_CID_CONTRAST:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Contrast", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 64;
ctrl->flags = 0;
break;
case V4L2_CID_SATURATION:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Saturation", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 64;
ctrl->flags = 0;
break;
case V4L2_CID_HUE:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Hue", sizeof(ctrl->name));
ctrl->minimum = -128;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 0;
ctrl->flags = 0;
break;
}
break;
}
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
if (ctrl->value > 255)
dec->brightness = 255;
else if (ctrl->value < 0)
dec->brightness = 0;
else
dec->brightness = ctrl->value;
write_reg(client, 0x0a, dec->brightness);
break;
case V4L2_CID_CONTRAST:
if (ctrl->value > 127)
dec->contrast = 127;
else if (ctrl->value < 0)
dec->contrast = 0;
else
dec->contrast = ctrl->value;
write_reg(client, 0x0b, dec->contrast);
break;
case V4L2_CID_SATURATION:
if (ctrl->value > 127)
dec->saturation = 127;
else if (ctrl->value < 0)
dec->saturation = 0;
else
dec->saturation = ctrl->value;
write_reg(client, 0x0c, dec->saturation);
break;
case V4L2_CID_HUE:
if (ctrl->value > 127)
dec->hue = 127;
else if (ctrl->value < -128)
dec->hue = -128;
else
dec->hue = ctrl->value;
write_reg(client, 0x0d, dec->hue);
break;
}
break;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->value = dec->brightness;
break;
case V4L2_CID_CONTRAST:
ctrl->value = dec->contrast;
break;
case V4L2_CID_SATURATION:
ctrl->value = dec->saturation;
break;
case V4L2_CID_HUE:
ctrl->value = dec->hue;
break;
}
break;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_saa7115_driver;
static struct i2c_client wis_saa7115_client_templ = {
.name = "SAA7115 (WIS)",
.driver = &wis_saa7115_driver,
};
static int wis_saa7115_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
struct wis_saa7115 *dec;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_saa7115_client_templ,
sizeof(wis_saa7115_client_templ));
client->adapter = adapter;
client->addr = addr;
dec = kmalloc(sizeof(struct wis_saa7115), GFP_KERNEL);
if (dec == NULL) {
kfree(client);
return -ENOMEM;
}
dec->norm = V4L2_STD_NTSC;
dec->brightness = 128;
dec->contrast = 64;
dec->saturation = 64;
dec->hue = 0;
i2c_set_clientdata(client, dec);
printk(KERN_DEBUG
"wis-saa7115: initializing SAA7115 at address %d on %s\n",
addr, adapter->name);
if (write_regs(client, initial_registers) < 0) {
printk(KERN_ERR
"wis-saa7115: error initializing SAA7115\n");
kfree(client);
kfree(dec);
return 0;
}
i2c_attach_client(client);
return 0;
}
static int wis_saa7115_detach(struct i2c_client *client)
{
struct wis_saa7115 *dec = i2c_get_clientdata(client);
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
kfree(dec);
return 0;
}
static struct i2c_driver wis_saa7115_driver = {
.driver = {
.name = "WIS SAA7115 I2C driver",
},
.id = I2C_DRIVERID_WIS_SAA7115,
.detach_client = wis_saa7115_detach,
.command = wis_saa7115_command,
};
static int __init wis_saa7115_init(void)
{
int r;
r = i2c_add_driver(&wis_saa7115_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_saa7115_driver.id, wis_saa7115_detect);
}
static void __exit wis_saa7115_cleanup(void)
{
wis_i2c_del_driver(wis_saa7115_detect);
i2c_del_driver(&wis_saa7115_driver);
}
module_init(wis_saa7115_init);
module_exit(wis_saa7115_cleanup);
MODULE_LICENSE("GPL v2");

742
drivers/staging/go7007/wis-sony-tuner.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/tuner.h>
#include <media/v4l2-common.h>
#include <media/v4l2-ioctl.h>
#include "wis-i2c.h"
/* #define MPX_DEBUG */
/* AS(IF/MPX) pin: LOW HIGH/OPEN
* IF/MPX address: 0x42/0x40 0x43/0x44
*/
#define IF_I2C_ADDR 0x43
#define MPX_I2C_ADDR 0x44
static v4l2_std_id force_band;
static char force_band_str[] = "-";
module_param_string(force_band, force_band_str, sizeof(force_band_str), 0644);
static int force_mpx_mode = -1;
module_param(force_mpx_mode, int, 0644);
/* Store tuner info in the same format as tuner.c, so maybe we can put the
* Sony tuner support in there. */
struct sony_tunertype {
char *name;
unsigned char Vendor; /* unused here */
unsigned char Type; /* unused here */
unsigned short thresh1; /* band switch VHF_LO <=> VHF_HI */
unsigned short thresh2; /* band switch VHF_HI <=> UHF */
unsigned char VHF_L;
unsigned char VHF_H;
unsigned char UHF;
unsigned char config;
unsigned short IFPCoff;
};
/* This array is indexed by (tuner_type - 200) */
static struct sony_tunertype sony_tuners[] = {
{ "Sony PAL+SECAM (BTF-PG472Z)", 0, 0,
16*144.25, 16*427.25, 0x01, 0x02, 0x04, 0xc6, 623},
{ "Sony NTSC_JP (BTF-PK467Z)", 0, 0,
16*220.25, 16*467.25, 0x01, 0x02, 0x04, 0xc6, 940},
{ "Sony NTSC (BTF-PB463Z)", 0, 0,
16*130.25, 16*364.25, 0x01, 0x02, 0x04, 0xc6, 732},
};
struct wis_sony_tuner {
int type;
v4l2_std_id std;
unsigned int freq;
int mpxmode;
u32 audmode;
};
/* Basically the same as default_set_tv_freq() in tuner.c */
static int set_freq(struct i2c_client *client, int freq)
{
struct wis_sony_tuner *t = i2c_get_clientdata(client);
char *band_name;
int n;
int band_select;
struct sony_tunertype *tun;
u8 buffer[4];
tun = &sony_tuners[t->type - 200];
if (freq < tun->thresh1) {
band_name = "VHF_L";
band_select = tun->VHF_L;
} else if (freq < tun->thresh2) {
band_name = "VHF_H";
band_select = tun->VHF_H;
} else {
band_name = "UHF";
band_select = tun->UHF;
}
printk(KERN_DEBUG "wis-sony-tuner: tuning to frequency %d.%04d (%s)\n",
freq / 16, (freq % 16) * 625, band_name);
n = freq + tun->IFPCoff;
buffer[0] = n >> 8;
buffer[1] = n & 0xff;
buffer[2] = tun->config;
buffer[3] = band_select;
i2c_master_send(client, buffer, 4);
return 0;
}
static int mpx_write(struct i2c_client *client, int dev, int addr, int val)
{
u8 buffer[5];
struct i2c_msg msg;
buffer[0] = dev;
buffer[1] = addr >> 8;
buffer[2] = addr & 0xff;
buffer[3] = val >> 8;
buffer[4] = val & 0xff;
msg.addr = MPX_I2C_ADDR;
msg.flags = 0;
msg.len = 5;
msg.buf = buffer;
i2c_transfer(client->adapter, &msg, 1);
return 0;
}
/*
* MPX register values for the BTF-PG472Z:
*
* FM_ NICAM_ SCART_
* MODUS SOURCE ACB PRESCAL PRESCAL PRESCAL SYSTEM VOLUME
* 10/0030 12/0008 12/0013 12/000E 12/0010 12/0000 10/0020 12/0000
* ---------------------------------------------------------------
* Auto 1003 0020 0100 2603 5000 XXXX 0001 7500
*
* B/G
* Mono 1003 0020 0100 2603 5000 XXXX 0003 7500
* A2 1003 0020 0100 2601 5000 XXXX 0003 7500
* NICAM 1003 0120 0100 2603 5000 XXXX 0008 7500
*
* I
* Mono 1003 0020 0100 2603 7900 XXXX 000A 7500
* NICAM 1003 0120 0100 2603 7900 XXXX 000A 7500
*
* D/K
* Mono 1003 0020 0100 2603 5000 XXXX 0004 7500
* A2-1 1003 0020 0100 2601 5000 XXXX 0004 7500
* A2-2 1003 0020 0100 2601 5000 XXXX 0005 7500
* A2-3 1003 0020 0100 2601 5000 XXXX 0007 7500
* NICAM 1003 0120 0100 2603 5000 XXXX 000B 7500
*
* L/L'
* Mono 0003 0200 0100 7C03 5000 2200 0009 7500
* NICAM 0003 0120 0100 7C03 5000 XXXX 0009 7500
*
* M
* Mono 1003 0200 0100 2B03 5000 2B00 0002 7500
*
* For Asia, replace the 0x26XX in FM_PRESCALE with 0x14XX.
*
* Bilingual selection in A2/NICAM:
*
* High byte of SOURCE Left chan Right chan
* 0x01 MAIN SUB
* 0x03 MAIN MAIN
* 0x04 SUB SUB
*
* Force mono in NICAM by setting the high byte of SOURCE to 0x02 (L/L') or
* 0x00 (all other bands). Force mono in A2 with FMONO_A2:
*
* FMONO_A2
* 10/0022
* --------
* Forced mono ON 07F0
* Forced mono OFF 0190
*/
static struct {
enum { AUD_MONO, AUD_A2, AUD_NICAM, AUD_NICAM_L } audio_mode;
u16 modus;
u16 source;
u16 acb;
u16 fm_prescale;
u16 nicam_prescale;
u16 scart_prescale;
u16 system;
u16 volume;
} mpx_audio_modes[] = {
/* Auto */ { AUD_MONO, 0x1003, 0x0020, 0x0100, 0x2603,
0x5000, 0x0000, 0x0001, 0x7500 },
/* B/G Mono */ { AUD_MONO, 0x1003, 0x0020, 0x0100, 0x2603,
0x5000, 0x0000, 0x0003, 0x7500 },
/* B/G A2 */ { AUD_A2, 0x1003, 0x0020, 0x0100, 0x2601,
0x5000, 0x0000, 0x0003, 0x7500 },
/* B/G NICAM */ { AUD_NICAM, 0x1003, 0x0120, 0x0100, 0x2603,
0x5000, 0x0000, 0x0008, 0x7500 },
/* I Mono */ { AUD_MONO, 0x1003, 0x0020, 0x0100, 0x2603,
0x7900, 0x0000, 0x000A, 0x7500 },
/* I NICAM */ { AUD_NICAM, 0x1003, 0x0120, 0x0100, 0x2603,
0x7900, 0x0000, 0x000A, 0x7500 },
/* D/K Mono */ { AUD_MONO, 0x1003, 0x0020, 0x0100, 0x2603,
0x5000, 0x0000, 0x0004, 0x7500 },
/* D/K A2-1 */ { AUD_A2, 0x1003, 0x0020, 0x0100, 0x2601,
0x5000, 0x0000, 0x0004, 0x7500 },
/* D/K A2-2 */ { AUD_A2, 0x1003, 0x0020, 0x0100, 0x2601,
0x5000, 0x0000, 0x0005, 0x7500 },
/* D/K A2-3 */ { AUD_A2, 0x1003, 0x0020, 0x0100, 0x2601,
0x5000, 0x0000, 0x0007, 0x7500 },
/* D/K NICAM */ { AUD_NICAM, 0x1003, 0x0120, 0x0100, 0x2603,
0x5000, 0x0000, 0x000B, 0x7500 },
/* L/L' Mono */ { AUD_MONO, 0x0003, 0x0200, 0x0100, 0x7C03,
0x5000, 0x2200, 0x0009, 0x7500 },
/* L/L' NICAM */{ AUD_NICAM_L, 0x0003, 0x0120, 0x0100, 0x7C03,
0x5000, 0x0000, 0x0009, 0x7500 },
};
#define MPX_NUM_MODES ARRAY_SIZE(mpx_audio_modes)
static int mpx_setup(struct i2c_client *client)
{
struct wis_sony_tuner *t = i2c_get_clientdata(client);
u16 source = 0;
u8 buffer[3];
struct i2c_msg msg;
/* reset MPX */
buffer[0] = 0x00;
buffer[1] = 0x80;
buffer[2] = 0x00;
msg.addr = MPX_I2C_ADDR;
msg.flags = 0;
msg.len = 3;
msg.buf = buffer;
i2c_transfer(client->adapter, &msg, 1);
buffer[1] = 0x00;
i2c_transfer(client->adapter, &msg, 1);
if (mpx_audio_modes[t->mpxmode].audio_mode != AUD_MONO) {
switch (t->audmode) {
case V4L2_TUNER_MODE_MONO:
switch (mpx_audio_modes[t->mpxmode].audio_mode) {
case AUD_A2:
source = mpx_audio_modes[t->mpxmode].source;
break;
case AUD_NICAM:
source = 0x0000;
break;
case AUD_NICAM_L:
source = 0x0200;
break;
default:
break;
}
break;
case V4L2_TUNER_MODE_STEREO:
source = mpx_audio_modes[t->mpxmode].source;
break;
case V4L2_TUNER_MODE_LANG1:
source = 0x0300;
break;
case V4L2_TUNER_MODE_LANG2:
source = 0x0400;
break;
}
source |= mpx_audio_modes[t->mpxmode].source & 0x00ff;
} else
source = mpx_audio_modes[t->mpxmode].source;
mpx_write(client, 0x10, 0x0030, mpx_audio_modes[t->mpxmode].modus);
mpx_write(client, 0x12, 0x0008, source);
mpx_write(client, 0x12, 0x0013, mpx_audio_modes[t->mpxmode].acb);
mpx_write(client, 0x12, 0x000e,
mpx_audio_modes[t->mpxmode].fm_prescale);
mpx_write(client, 0x12, 0x0010,
mpx_audio_modes[t->mpxmode].nicam_prescale);
mpx_write(client, 0x12, 0x000d,
mpx_audio_modes[t->mpxmode].scart_prescale);
mpx_write(client, 0x10, 0x0020, mpx_audio_modes[t->mpxmode].system);
mpx_write(client, 0x12, 0x0000, mpx_audio_modes[t->mpxmode].volume);
if (mpx_audio_modes[t->mpxmode].audio_mode == AUD_A2)
mpx_write(client, 0x10, 0x0022,
t->audmode == V4L2_TUNER_MODE_MONO ? 0x07f0 : 0x0190);
#ifdef MPX_DEBUG
{
u8 buf1[3], buf2[2];
struct i2c_msg msgs[2];
printk(KERN_DEBUG "wis-sony-tuner: MPX registers: %04x %04x "
"%04x %04x %04x %04x %04x %04x\n",
mpx_audio_modes[t->mpxmode].modus,
source,
mpx_audio_modes[t->mpxmode].acb,
mpx_audio_modes[t->mpxmode].fm_prescale,
mpx_audio_modes[t->mpxmode].nicam_prescale,
mpx_audio_modes[t->mpxmode].scart_prescale,
mpx_audio_modes[t->mpxmode].system,
mpx_audio_modes[t->mpxmode].volume);
buf1[0] = 0x11;
buf1[1] = 0x00;
buf1[2] = 0x7e;
msgs[0].addr = MPX_I2C_ADDR;
msgs[0].flags = 0;
msgs[0].len = 3;
msgs[0].buf = buf1;
msgs[1].addr = MPX_I2C_ADDR;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 2;
msgs[1].buf = buf2;
i2c_transfer(client->adapter, msgs, 2);
printk(KERN_DEBUG "wis-sony-tuner: MPX system: %02x%02x\n",
buf2[0], buf2[1]);
buf1[0] = 0x11;
buf1[1] = 0x02;
buf1[2] = 0x00;
i2c_transfer(client->adapter, msgs, 2);
printk(KERN_DEBUG "wis-sony-tuner: MPX status: %02x%02x\n",
buf2[0], buf2[1]);
}
#endif
return 0;
}
/*
* IF configuration values for the BTF-PG472Z:
*
* B/G: 0x94 0x70 0x49
* I: 0x14 0x70 0x4a
* D/K: 0x14 0x70 0x4b
* L: 0x04 0x70 0x4b
* L': 0x44 0x70 0x53
* M: 0x50 0x30 0x4c
*/
static int set_if(struct i2c_client *client)
{
struct wis_sony_tuner *t = i2c_get_clientdata(client);
u8 buffer[4];
struct i2c_msg msg;
int default_mpx_mode = 0;
/* configure IF */
buffer[0] = 0;
if (t->std & V4L2_STD_PAL_BG) {
buffer[1] = 0x94;
buffer[2] = 0x70;
buffer[3] = 0x49;
default_mpx_mode = 1;
} else if (t->std & V4L2_STD_PAL_I) {
buffer[1] = 0x14;
buffer[2] = 0x70;
buffer[3] = 0x4a;
default_mpx_mode = 4;
} else if (t->std & V4L2_STD_PAL_DK) {
buffer[1] = 0x14;
buffer[2] = 0x70;
buffer[3] = 0x4b;
default_mpx_mode = 6;
} else if (t->std & V4L2_STD_SECAM_L) {
buffer[1] = 0x04;
buffer[2] = 0x70;
buffer[3] = 0x4b;
default_mpx_mode = 11;
}
msg.addr = IF_I2C_ADDR;
msg.flags = 0;
msg.len = 4;
msg.buf = buffer;
i2c_transfer(client->adapter, &msg, 1);
/* Select MPX mode if not forced by the user */
if (force_mpx_mode >= 0 || force_mpx_mode < MPX_NUM_MODES)
t->mpxmode = force_mpx_mode;
else
t->mpxmode = default_mpx_mode;
printk(KERN_DEBUG "wis-sony-tuner: setting MPX to mode %d\n",
t->mpxmode);
mpx_setup(client);
return 0;
}
static int tuner_command(struct i2c_client *client, unsigned int cmd, void *arg)
{
struct wis_sony_tuner *t = i2c_get_clientdata(client);
switch (cmd) {
#ifdef TUNER_SET_TYPE_ADDR
case TUNER_SET_TYPE_ADDR:
{
struct tuner_setup *tun_setup = arg;
int *type = &tun_setup->type;
#else
case TUNER_SET_TYPE:
{
int *type = arg;
#endif
if (t->type >= 0) {
if (t->type != *type)
printk(KERN_ERR "wis-sony-tuner: type already "
"set to %d, ignoring request for %d\n",
t->type, *type);
break;
}
t->type = *type;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
switch (force_band_str[0]) {
case 'b':
case 'B':
case 'g':
case 'G':
printk(KERN_INFO "wis-sony-tuner: forcing "
"tuner to PAL-B/G bands\n");
force_band = V4L2_STD_PAL_BG;
break;
case 'i':
case 'I':
printk(KERN_INFO "wis-sony-tuner: forcing "
"tuner to PAL-I band\n");
force_band = V4L2_STD_PAL_I;
break;
case 'd':
case 'D':
case 'k':
case 'K':
printk(KERN_INFO "wis-sony-tuner: forcing "
"tuner to PAL-D/K bands\n");
force_band = V4L2_STD_PAL_I;
break;
case 'l':
case 'L':
printk(KERN_INFO "wis-sony-tuner: forcing "
"tuner to SECAM-L band\n");
force_band = V4L2_STD_SECAM_L;
break;
default:
force_band = 0;
break;
}
if (force_band)
t->std = force_band;
else
t->std = V4L2_STD_PAL_BG;
set_if(client);
break;
case TUNER_SONY_BTF_PK467Z:
t->std = V4L2_STD_NTSC_M_JP;
break;
case TUNER_SONY_BTF_PB463Z:
t->std = V4L2_STD_NTSC_M;
break;
default:
printk(KERN_ERR "wis-sony-tuner: tuner type %d is not "
"supported by this module\n", *type);
break;
}
if (type >= 0)
printk(KERN_INFO
"wis-sony-tuner: type set to %d (%s)\n",
t->type, sony_tuners[t->type - 200].name);
break;
}
case VIDIOC_G_FREQUENCY:
{
struct v4l2_frequency *f = arg;
f->frequency = t->freq;
break;
}
case VIDIOC_S_FREQUENCY:
{
struct v4l2_frequency *f = arg;
t->freq = f->frequency;
set_freq(client, t->freq);
break;
}
case VIDIOC_ENUMSTD:
{
struct v4l2_standard *std = arg;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
switch (std->index) {
case 0:
v4l2_video_std_construct(std,
V4L2_STD_PAL_BG, "PAL-B/G");
break;
case 1:
v4l2_video_std_construct(std,
V4L2_STD_PAL_I, "PAL-I");
break;
case 2:
v4l2_video_std_construct(std,
V4L2_STD_PAL_DK, "PAL-D/K");
break;
case 3:
v4l2_video_std_construct(std,
V4L2_STD_SECAM_L, "SECAM-L");
break;
default:
std->id = 0; /* hack to indicate EINVAL */
break;
}
break;
case TUNER_SONY_BTF_PK467Z:
if (std->index != 0) {
std->id = 0; /* hack to indicate EINVAL */
break;
}
v4l2_video_std_construct(std,
V4L2_STD_NTSC_M_JP, "NTSC-J");
break;
case TUNER_SONY_BTF_PB463Z:
if (std->index != 0) {
std->id = 0; /* hack to indicate EINVAL */
break;
}
v4l2_video_std_construct(std, V4L2_STD_NTSC_M, "NTSC");
break;
}
break;
}
case VIDIOC_G_STD:
{
v4l2_std_id *std = arg;
*std = t->std;
break;
}
case VIDIOC_S_STD:
{
v4l2_std_id *std = arg;
v4l2_std_id old = t->std;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
if (force_band && (*std & force_band) != *std &&
*std != V4L2_STD_PAL &&
*std != V4L2_STD_SECAM) {
printk(KERN_DEBUG "wis-sony-tuner: ignoring "
"requested TV standard in "
"favor of force_band value\n");
t->std = force_band;
} else if (*std & V4L2_STD_PAL_BG) { /* default */
t->std = V4L2_STD_PAL_BG;
} else if (*std & V4L2_STD_PAL_I) {
t->std = V4L2_STD_PAL_I;
} else if (*std & V4L2_STD_PAL_DK) {
t->std = V4L2_STD_PAL_DK;
} else if (*std & V4L2_STD_SECAM_L) {
t->std = V4L2_STD_SECAM_L;
} else {
printk(KERN_ERR "wis-sony-tuner: TV standard "
"not supported\n");
*std = 0; /* hack to indicate EINVAL */
break;
}
if (old != t->std)
set_if(client);
break;
case TUNER_SONY_BTF_PK467Z:
if (!(*std & V4L2_STD_NTSC_M_JP)) {
printk(KERN_ERR "wis-sony-tuner: TV standard "
"not supported\n");
*std = 0; /* hack to indicate EINVAL */
}
break;
case TUNER_SONY_BTF_PB463Z:
if (!(*std & V4L2_STD_NTSC_M)) {
printk(KERN_ERR "wis-sony-tuner: TV standard "
"not supported\n");
*std = 0; /* hack to indicate EINVAL */
}
break;
}
break;
}
case VIDIOC_QUERYSTD:
{
v4l2_std_id *std = arg;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
if (force_band)
*std = force_band;
else
*std = V4L2_STD_PAL_BG | V4L2_STD_PAL_I |
V4L2_STD_PAL_DK | V4L2_STD_SECAM_L;
break;
case TUNER_SONY_BTF_PK467Z:
*std = V4L2_STD_NTSC_M_JP;
break;
case TUNER_SONY_BTF_PB463Z:
*std = V4L2_STD_NTSC_M;
break;
}
break;
}
case VIDIOC_G_TUNER:
{
struct v4l2_tuner *tun = arg;
memset(t, 0, sizeof(*tun));
strcpy(tun->name, "Television");
tun->type = V4L2_TUNER_ANALOG_TV;
tun->rangelow = 0UL; /* does anything use these? */
tun->rangehigh = 0xffffffffUL;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
tun->capability = V4L2_TUNER_CAP_NORM |
V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
V4L2_TUNER_CAP_LANG2;
tun->rxsubchans = V4L2_TUNER_SUB_MONO |
V4L2_TUNER_SUB_STEREO | V4L2_TUNER_SUB_LANG1 |
V4L2_TUNER_SUB_LANG2;
break;
case TUNER_SONY_BTF_PK467Z:
case TUNER_SONY_BTF_PB463Z:
tun->capability = V4L2_TUNER_CAP_STEREO;
tun->rxsubchans = V4L2_TUNER_SUB_MONO |
V4L2_TUNER_SUB_STEREO;
break;
}
tun->audmode = t->audmode;
return 0;
}
case VIDIOC_S_TUNER:
{
struct v4l2_tuner *tun = arg;
switch (t->type) {
case TUNER_SONY_BTF_PG472Z:
if (tun->audmode != t->audmode) {
t->audmode = tun->audmode;
mpx_setup(client);
}
break;
case TUNER_SONY_BTF_PK467Z:
case TUNER_SONY_BTF_PB463Z:
break;
}
return 0;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_sony_tuner_driver;
static struct i2c_client wis_sony_tuner_client_templ = {
.name = "Sony TV Tuner (WIS)",
.driver = &wis_sony_tuner_driver,
};
static int wis_sony_tuner_detect(struct i2c_adapter *adapter,
int addr, int kind)
{
struct i2c_client *client;
struct wis_sony_tuner *t;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_I2C_BLOCK))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_sony_tuner_client_templ,
sizeof(wis_sony_tuner_client_templ));
client->adapter = adapter;
client->addr = addr;
t = kmalloc(sizeof(struct wis_sony_tuner), GFP_KERNEL);
if (t == NULL) {
kfree(client);
return -ENOMEM;
}
t->type = -1;
t->freq = 0;
t->mpxmode = 0;
t->audmode = V4L2_TUNER_MODE_STEREO;
i2c_set_clientdata(client, t);
printk(KERN_DEBUG
"wis-sony-tuner: initializing tuner at address %d on %s\n",
addr, adapter->name);
i2c_attach_client(client);
return 0;
}
static int wis_sony_tuner_detach(struct i2c_client *client)
{
struct wis_sony_tuner *t = i2c_get_clientdata(client);
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(t);
kfree(client);
return 0;
}
static struct i2c_driver wis_sony_tuner_driver = {
.driver = {
.name = "WIS Sony TV Tuner I2C driver",
},
.id = I2C_DRIVERID_WIS_SONY_TUNER,
.detach_client = wis_sony_tuner_detach,
.command = tuner_command,
};
static int __init wis_sony_tuner_init(void)
{
int r;
r = i2c_add_driver(&wis_sony_tuner_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_sony_tuner_driver.id,
wis_sony_tuner_detect);
}
static void __exit wis_sony_tuner_cleanup(void)
{
wis_i2c_del_driver(wis_sony_tuner_detect);
i2c_del_driver(&wis_sony_tuner_driver);
}
module_init(wis_sony_tuner_init);
module_exit(wis_sony_tuner_cleanup);
MODULE_LICENSE("GPL v2");

380
drivers/staging/go7007/wis-tw2804.c Normal file
View file

@ -0,0 +1,380 @@
/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/ioctl.h>
#include "wis-i2c.h"
struct wis_tw2804 {
int channel;
int norm;
int brightness;
int contrast;
int saturation;
int hue;
};
static u8 global_registers[] =
{
0x39, 0x00,
0x3a, 0xff,
0x3b, 0x84,
0x3c, 0x80,
0x3d, 0x80,
0x3e, 0x82,
0x3f, 0x82,
0xff, 0xff, /* Terminator (reg 0xff does not exist) */
};
static u8 channel_registers[] =
{
0x01, 0xc4,
0x02, 0xa5,
0x03, 0x20,
0x04, 0xd0,
0x05, 0x20,
0x06, 0xd0,
0x07, 0x88,
0x08, 0x20,
0x09, 0x07,
0x0a, 0xf0,
0x0b, 0x07,
0x0c, 0xf0,
0x0d, 0x40,
0x0e, 0xd2,
0x0f, 0x80,
0x10, 0x80,
0x11, 0x80,
0x12, 0x80,
0x13, 0x1f,
0x14, 0x00,
0x15, 0x00,
0x16, 0x00,
0x17, 0x00,
0x18, 0xff,
0x19, 0xff,
0x1a, 0xff,
0x1b, 0xff,
0x1c, 0xff,
0x1d, 0xff,
0x1e, 0xff,
0x1f, 0xff,
0x20, 0x07,
0x21, 0x07,
0x22, 0x00,
0x23, 0x91,
0x24, 0x51,
0x25, 0x03,
0x26, 0x00,
0x27, 0x00,
0x28, 0x00,
0x29, 0x00,
0x2a, 0x00,
0x2b, 0x00,
0x2c, 0x00,
0x2d, 0x00,
0x2e, 0x00,
0x2f, 0x00,
0x30, 0x00,
0x31, 0x00,
0x32, 0x00,
0x33, 0x00,
0x34, 0x00,
0x35, 0x00,
0x36, 0x00,
0x37, 0x00,
0xff, 0xff, /* Terminator (reg 0xff does not exist) */
};
static int write_reg(struct i2c_client *client, u8 reg, u8 value, int channel)
{
return i2c_smbus_write_byte_data(client, reg | (channel << 6), value);
}
static int write_regs(struct i2c_client *client, u8 *regs, int channel)
{
int i;
for (i = 0; regs[i] != 0xff; i += 2)
if (i2c_smbus_write_byte_data(client,
regs[i] | (channel << 6), regs[i + 1]) < 0)
return -1;
return 0;
}
static int wis_tw2804_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
struct wis_tw2804 *dec = i2c_get_clientdata(client);
if (cmd == DECODER_SET_CHANNEL) {
int *input = arg;
if (*input < 0 || *input > 3) {
printk(KERN_ERR "wis-tw2804: channel %d is not "
"between 0 and 3!\n", *input);
return 0;
}
dec->channel = *input;
printk(KERN_DEBUG "wis-tw2804: initializing TW2804 "
"channel %d\n", dec->channel);
if (dec->channel == 0 &&
write_regs(client, global_registers, 0) < 0) {
printk(KERN_ERR "wis-tw2804: error initializing "
"TW2804 global registers\n");
return 0;
}
if (write_regs(client, channel_registers, dec->channel) < 0) {
printk(KERN_ERR "wis-tw2804: error initializing "
"TW2804 channel %d\n", dec->channel);
return 0;
}
return 0;
}
if (dec->channel < 0) {
printk(KERN_DEBUG "wis-tw2804: ignoring command %08x until "
"channel number is set\n", cmd);
return 0;
}
switch (cmd) {
case VIDIOC_S_STD:
{
v4l2_std_id *input = arg;
u8 regs[] = {
0x01, *input & V4L2_STD_NTSC ? 0xc4 : 0x84,
0x09, *input & V4L2_STD_NTSC ? 0x07 : 0x04,
0x0a, *input & V4L2_STD_NTSC ? 0xf0 : 0x20,
0x0b, *input & V4L2_STD_NTSC ? 0x07 : 0x04,
0x0c, *input & V4L2_STD_NTSC ? 0xf0 : 0x20,
0x0d, *input & V4L2_STD_NTSC ? 0x40 : 0x4a,
0x16, *input & V4L2_STD_NTSC ? 0x00 : 0x40,
0x17, *input & V4L2_STD_NTSC ? 0x00 : 0x40,
0x20, *input & V4L2_STD_NTSC ? 0x07 : 0x0f,
0x21, *input & V4L2_STD_NTSC ? 0x07 : 0x0f,
0xff, 0xff,
};
write_regs(client, regs, dec->channel);
dec->norm = *input;
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Brightness", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
case V4L2_CID_CONTRAST:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Contrast", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
case V4L2_CID_SATURATION:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Saturation", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
case V4L2_CID_HUE:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Hue", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 128;
ctrl->flags = 0;
break;
}
break;
}
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
if (ctrl->value > 255)
dec->brightness = 255;
else if (ctrl->value < 0)
dec->brightness = 0;
else
dec->brightness = ctrl->value;
write_reg(client, 0x12, dec->brightness, dec->channel);
break;
case V4L2_CID_CONTRAST:
if (ctrl->value > 255)
dec->contrast = 255;
else if (ctrl->value < 0)
dec->contrast = 0;
else
dec->contrast = ctrl->value;
write_reg(client, 0x11, dec->contrast, dec->channel);
break;
case V4L2_CID_SATURATION:
if (ctrl->value > 255)
dec->saturation = 255;
else if (ctrl->value < 0)
dec->saturation = 0;
else
dec->saturation = ctrl->value;
write_reg(client, 0x10, dec->saturation, dec->channel);
break;
case V4L2_CID_HUE:
if (ctrl->value > 255)
dec->hue = 255;
else if (ctrl->value < 0)
dec->hue = 0;
else
dec->hue = ctrl->value;
write_reg(client, 0x0f, dec->hue, dec->channel);
break;
}
break;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->value = dec->brightness;
break;
case V4L2_CID_CONTRAST:
ctrl->value = dec->contrast;
break;
case V4L2_CID_SATURATION:
ctrl->value = dec->saturation;
break;
case V4L2_CID_HUE:
ctrl->value = dec->hue;
break;
}
break;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_tw2804_driver;
static struct i2c_client wis_tw2804_client_templ = {
.name = "TW2804 (WIS)",
.driver = &wis_tw2804_driver,
};
static int wis_tw2804_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
struct wis_tw2804 *dec;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_tw2804_client_templ,
sizeof(wis_tw2804_client_templ));
client->adapter = adapter;
client->addr = addr;
dec = kmalloc(sizeof(struct wis_tw2804), GFP_KERNEL);
if (dec == NULL) {
kfree(client);
return -ENOMEM;
}
dec->channel = -1;
dec->norm = V4L2_STD_NTSC;
dec->brightness = 128;
dec->contrast = 128;
dec->saturation = 128;
dec->hue = 128;
i2c_set_clientdata(client, dec);
printk(KERN_DEBUG "wis-tw2804: creating TW2804 at address %d on %s\n",
addr, adapter->name);
i2c_attach_client(client);
return 0;
}
static int wis_tw2804_detach(struct i2c_client *client)
{
struct wis_tw2804 *dec = i2c_get_clientdata(client);
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
kfree(dec);
return 0;
}
static struct i2c_driver wis_tw2804_driver = {
.driver = {
.name = "WIS TW2804 I2C driver",
},
.id = I2C_DRIVERID_WIS_TW2804,
.detach_client = wis_tw2804_detach,
.command = wis_tw2804_command,
};
static int __init wis_tw2804_init(void)
{
int r;
r = i2c_add_driver(&wis_tw2804_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_tw2804_driver.id, wis_tw2804_detect);
}
static void __exit wis_tw2804_cleanup(void)
{
wis_i2c_del_driver(wis_tw2804_detect);
i2c_del_driver(&wis_tw2804_driver);
}
module_init(wis_tw2804_init);
module_exit(wis_tw2804_cleanup);
MODULE_LICENSE("GPL v2");

362
drivers/staging/go7007/wis-tw9903.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <linux/ioctl.h>
#include "wis-i2c.h"
struct wis_tw9903 {
int norm;
int brightness;
int contrast;
int hue;
};
static u8 initial_registers[] =
{
0x02, 0x44, /* input 1, composite */
0x03, 0x92, /* correct digital format */
0x04, 0x00,
0x05, 0x80, /* or 0x00 for PAL */
0x06, 0x40, /* second internal current reference */
0x07, 0x02, /* window */
0x08, 0x14, /* window */
0x09, 0xf0, /* window */
0x0a, 0x81, /* window */
0x0b, 0xd0, /* window */
0x0c, 0x8c,
0x0d, 0x00, /* scaling */
0x0e, 0x11, /* scaling */
0x0f, 0x00, /* scaling */
0x10, 0x00, /* brightness */
0x11, 0x60, /* contrast */
0x12, 0x01, /* sharpness */
0x13, 0x7f, /* U gain */
0x14, 0x5a, /* V gain */
0x15, 0x00, /* hue */
0x16, 0xc3, /* sharpness */
0x18, 0x00,
0x19, 0x58, /* vbi */
0x1a, 0x80,
0x1c, 0x0f, /* video norm */
0x1d, 0x7f, /* video norm */
0x20, 0xa0, /* clamping gain (working 0x50) */
0x21, 0x22,
0x22, 0xf0,
0x23, 0xfe,
0x24, 0x3c,
0x25, 0x38,
0x26, 0x44,
0x27, 0x20,
0x28, 0x00,
0x29, 0x15,
0x2a, 0xa0,
0x2b, 0x44,
0x2c, 0x37,
0x2d, 0x00,
0x2e, 0xa5, /* burst PLL control (working: a9) */
0x2f, 0xe0, /* 0xea is blue test frame -- 0xe0 for normal */
0x31, 0x00,
0x33, 0x22,
0x34, 0x11,
0x35, 0x35,
0x3b, 0x05,
0x06, 0xc0, /* reset device */
0x00, 0x00, /* Terminator (reg 0x00 is read-only) */
};
static int write_reg(struct i2c_client *client, u8 reg, u8 value)
{
return i2c_smbus_write_byte_data(client, reg, value);
}
static int write_regs(struct i2c_client *client, u8 *regs)
{
int i;
for (i = 0; regs[i] != 0x00; i += 2)
if (i2c_smbus_write_byte_data(client, regs[i], regs[i + 1]) < 0)
return -1;
return 0;
}
static int wis_tw9903_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
struct wis_tw9903 *dec = i2c_get_clientdata(client);
switch (cmd) {
case VIDIOC_S_INPUT:
{
int *input = arg;
i2c_smbus_write_byte_data(client, 0x02, 0x40 | (*input << 1));
break;
}
#if 0 /* The scaler on this thing seems to be horribly broken */
case DECODER_SET_RESOLUTION:
{
struct video_decoder_resolution *res = arg;
/*int hscale = 256 * 720 / res->width;*/
int hscale = 256 * 720 / (res->width - (res->width > 704 ? 0 : 8));
int vscale = 256 * (dec->norm & V4L2_STD_NTSC ? 240 : 288)
/ res->height;
u8 regs[] = {
0x0d, vscale & 0xff,
0x0f, hscale & 0xff,
0x0e, ((vscale & 0xf00) >> 4) | ((hscale & 0xf00) >> 8),
0x06, 0xc0, /* reset device */
0, 0,
};
printk(KERN_DEBUG "vscale is %04x, hscale is %04x\n",
vscale, hscale);
/*write_regs(client, regs);*/
break;
}
#endif
case VIDIOC_S_STD:
{
v4l2_std_id *input = arg;
u8 regs[] = {
0x05, *input & V4L2_STD_NTSC ? 0x80 : 0x00,
0x07, *input & V4L2_STD_NTSC ? 0x02 : 0x12,
0x08, *input & V4L2_STD_NTSC ? 0x14 : 0x18,
0x09, *input & V4L2_STD_NTSC ? 0xf0 : 0x20,
0, 0,
};
write_regs(client, regs);
dec->norm = *input;
break;
}
case VIDIOC_QUERYCTRL:
{
struct v4l2_queryctrl *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Brightness", sizeof(ctrl->name));
ctrl->minimum = -128;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 0x00;
ctrl->flags = 0;
break;
case V4L2_CID_CONTRAST:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Contrast", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 255;
ctrl->step = 1;
ctrl->default_value = 0x60;
ctrl->flags = 0;
break;
#if 0
/* I don't understand how the Chroma Gain registers work... */
case V4L2_CID_SATURATION:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Saturation", sizeof(ctrl->name));
ctrl->minimum = 0;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 64;
ctrl->flags = 0;
break;
#endif
case V4L2_CID_HUE:
ctrl->type = V4L2_CTRL_TYPE_INTEGER;
strncpy(ctrl->name, "Hue", sizeof(ctrl->name));
ctrl->minimum = -128;
ctrl->maximum = 127;
ctrl->step = 1;
ctrl->default_value = 0;
ctrl->flags = 0;
break;
}
break;
}
case VIDIOC_S_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
if (ctrl->value > 127)
dec->brightness = 127;
else if (ctrl->value < -128)
dec->brightness = -128;
else
dec->brightness = ctrl->value;
write_reg(client, 0x10, dec->brightness);
break;
case V4L2_CID_CONTRAST:
if (ctrl->value > 255)
dec->contrast = 255;
else if (ctrl->value < 0)
dec->contrast = 0;
else
dec->contrast = ctrl->value;
write_reg(client, 0x11, dec->contrast);
break;
#if 0
case V4L2_CID_SATURATION:
if (ctrl->value > 127)
dec->saturation = 127;
else if (ctrl->value < 0)
dec->saturation = 0;
else
dec->saturation = ctrl->value;
/*write_reg(client, 0x0c, dec->saturation);*/
break;
#endif
case V4L2_CID_HUE:
if (ctrl->value > 127)
dec->hue = 127;
else if (ctrl->value < -128)
dec->hue = -128;
else
dec->hue = ctrl->value;
write_reg(client, 0x15, dec->hue);
break;
}
break;
}
case VIDIOC_G_CTRL:
{
struct v4l2_control *ctrl = arg;
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
ctrl->value = dec->brightness;
break;
case V4L2_CID_CONTRAST:
ctrl->value = dec->contrast;
break;
#if 0
case V4L2_CID_SATURATION:
ctrl->value = dec->saturation;
break;
#endif
case V4L2_CID_HUE:
ctrl->value = dec->hue;
break;
}
break;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_tw9903_driver;
static struct i2c_client wis_tw9903_client_templ = {
.name = "TW9903 (WIS)",
.driver = &wis_tw9903_driver,
};
static int wis_tw9903_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
struct wis_tw9903 *dec;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_tw9903_client_templ,
sizeof(wis_tw9903_client_templ));
client->adapter = adapter;
client->addr = addr;
dec = kmalloc(sizeof(struct wis_tw9903), GFP_KERNEL);
if (dec == NULL) {
kfree(client);
return -ENOMEM;
}
dec->norm = V4L2_STD_NTSC;
dec->brightness = 0;
dec->contrast = 0x60;
dec->hue = 0;
i2c_set_clientdata(client, dec);
printk(KERN_DEBUG
"wis-tw9903: initializing TW9903 at address %d on %s\n",
addr, adapter->name);
if (write_regs(client, initial_registers) < 0) {
printk(KERN_ERR "wis-tw9903: error initializing TW9903\n");
kfree(client);
kfree(dec);
return 0;
}
i2c_attach_client(client);
return 0;
}
static int wis_tw9903_detach(struct i2c_client *client)
{
struct wis_tw9903 *dec = i2c_get_clientdata(client);
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
kfree(dec);
return 0;
}
static struct i2c_driver wis_tw9903_driver = {
.driver = {
.name = "WIS TW9903 I2C driver",
},
.id = I2C_DRIVERID_WIS_TW9903,
.detach_client = wis_tw9903_detach,
.command = wis_tw9903_command,
};
static int __init wis_tw9903_init(void)
{
int r;
r = i2c_add_driver(&wis_tw9903_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_tw9903_driver.id, wis_tw9903_detect);
}
static void __exit wis_tw9903_cleanup(void)
{
wis_i2c_del_driver(wis_tw9903_detect);
i2c_del_driver(&wis_tw9903_driver);
}
module_init(wis_tw9903_init);
module_exit(wis_tw9903_cleanup);
MODULE_LICENSE("GPL v2");

136
drivers/staging/go7007/wis-uda1342.c Normal file
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/*
* Copyright (C) 2005-2006 Micronas USA Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software Foundation,
* Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
#include <media/tvaudio.h>
#include <media/v4l2-common.h>
#include "wis-i2c.h"
static int write_reg(struct i2c_client *client, int reg, int value)
{
/* UDA1342 wants MSB first, but SMBus sends LSB first */
i2c_smbus_write_word_data(client, reg, swab16(value));
return 0;
}
static int wis_uda1342_command(struct i2c_client *client,
unsigned int cmd, void *arg)
{
switch (cmd) {
case VIDIOC_S_AUDIO:
{
int *inp = arg;
switch (*inp) {
case TVAUDIO_INPUT_TUNER:
write_reg(client, 0x00, 0x1441); /* select input 2 */
break;
case TVAUDIO_INPUT_EXTERN:
write_reg(client, 0x00, 0x1241); /* select input 1 */
break;
default:
printk(KERN_ERR "wis-uda1342: input %d not supported\n",
*inp);
break;
}
break;
}
default:
break;
}
return 0;
}
static struct i2c_driver wis_uda1342_driver;
static struct i2c_client wis_uda1342_client_templ = {
.name = "UDA1342 (WIS)",
.driver = &wis_uda1342_driver,
};
static int wis_uda1342_detect(struct i2c_adapter *adapter, int addr, int kind)
{
struct i2c_client *client;
if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA))
return 0;
client = kmalloc(sizeof(struct i2c_client), GFP_KERNEL);
if (client == NULL)
return -ENOMEM;
memcpy(client, &wis_uda1342_client_templ,
sizeof(wis_uda1342_client_templ));
client->adapter = adapter;
client->addr = addr;
printk(KERN_DEBUG
"wis-uda1342: initializing UDA1342 at address %d on %s\n",
addr, adapter->name);
write_reg(client, 0x00, 0x8000); /* reset registers */
write_reg(client, 0x00, 0x1241); /* select input 1 */
i2c_attach_client(client);
return 0;
}
static int wis_uda1342_detach(struct i2c_client *client)
{
int r;
r = i2c_detach_client(client);
if (r < 0)
return r;
kfree(client);
return 0;
}
static struct i2c_driver wis_uda1342_driver = {
.driver = {
.name = "WIS UDA1342 I2C driver",
},
.id = I2C_DRIVERID_WIS_UDA1342,
.detach_client = wis_uda1342_detach,
.command = wis_uda1342_command,
};
static int __init wis_uda1342_init(void)
{
int r;
r = i2c_add_driver(&wis_uda1342_driver);
if (r < 0)
return r;
return wis_i2c_add_driver(wis_uda1342_driver.id, wis_uda1342_detect);
}
static void __exit wis_uda1342_cleanup(void)
{
wis_i2c_del_driver(wis_uda1342_detect);
i2c_del_driver(&wis_uda1342_driver);
}
module_init(wis_uda1342_init);
module_exit(wis_uda1342_cleanup);
MODULE_LICENSE("GPL v2");

10
drivers/staging/me4000/Kconfig Normal file
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config ME4000
tristate "Meilhaus ME-4000 support"
default n
depends on PCI
help
This driver supports the Meilhaus ME-4000 family of boards
that do data collection and multipurpose I/O.
To compile this driver as a module, choose M here: the module
will be called me4000.

1
drivers/staging/me4000/Makefile Normal file
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obj-$(CONFIG_ME4000) += me4000.o

13
drivers/staging/me4000/README Normal file
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TODO:
- checkpatch.pl cleanups
- sparse cleanups
- possible /proc interaction cleanups
- more info needed for Kconfig entry
- real device id?
- module parameter cleanup
Please send patches to Greg Kroah-Hartman <gregkh@suse.de>
and Cc: Wolfgang Beiter <w.beiter@aon.at> and
Guenter Gebhardt <g.gebhardt@meilhaus.de>

6133
drivers/staging/me4000/me4000.c Normal file
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954
drivers/staging/me4000/me4000.h Normal file
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/*
* Copyright (C) 2003 Meilhaus Electronic GmbH (support@meilhaus.de)
*
* Source File : me4000.h
* Author : GG (Guenter Gebhardt) <g.gebhardt@meilhaus.de>
*/
#ifndef _ME4000_H_
#define _ME4000_H_
#ifdef __KERNEL__
/*=============================================================================
The version of the driver release
===========================================================================*/
#define ME4000_DRIVER_VERSION 0x10009 // Version 1.00.09
/*=============================================================================
Debug section
===========================================================================*/
#undef ME4000_CALL_DEBUG // Debug function entry and exit
#undef ME4000_ISR_DEBUG // Debug the interrupt service routine
#undef ME4000_PORT_DEBUG // Debug port access
#undef ME4000_DEBUG // General purpose debug masseges
#ifdef ME4000_CALL_DEBUG
#undef CALL_PDEBUG
#define CALL_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
#else
# define CALL_PDEBUG(fmt, args...) // no debugging, do nothing
#endif
#ifdef ME4000_ISR_DEBUG
#undef ISR_PDEBUG
#define ISR_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
#else
#define ISR_PDEBUG(fmt, args...) // no debugging, do nothing
#endif
#ifdef ME4000_PORT_DEBUG
#undef PORT_PDEBUG
#define PORT_PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
#else
#define PORT_PDEBUG(fmt, args...) // no debugging, do nothing
#endif
#ifdef ME4000_DEBUG
#undef PDEBUG
#define PDEBUG(fmt, args...) printk(KERN_DEBUG"ME4000:" fmt, ##args)
#else
#define PDEBUG(fmt, args...) // no debugging, do nothing
#endif
/*=============================================================================
PCI vendor and device IDs
===========================================================================*/
#define PCI_VENDOR_ID_MEILHAUS 0x1402
#define PCI_DEVICE_ID_MEILHAUS_ME4650 0x4650 // Low Cost version
#define PCI_DEVICE_ID_MEILHAUS_ME4660 0x4660 // Standard version
#define PCI_DEVICE_ID_MEILHAUS_ME4660I 0x4661 // Isolated version
#define PCI_DEVICE_ID_MEILHAUS_ME4660S 0x4662 // Standard version with Sample and Hold
#define PCI_DEVICE_ID_MEILHAUS_ME4660IS 0x4663 // Isolated version with Sample and Hold
#define PCI_DEVICE_ID_MEILHAUS_ME4670 0x4670 // Standard version
#define PCI_DEVICE_ID_MEILHAUS_ME4670I 0x4671 // Isolated version
#define PCI_DEVICE_ID_MEILHAUS_ME4670S 0x4672 // Standard version with Sample and Hold
#define PCI_DEVICE_ID_MEILHAUS_ME4670IS 0x4673 // Isolated version with Sample and Hold
#define PCI_DEVICE_ID_MEILHAUS_ME4680 0x4680 // Standard version
#define PCI_DEVICE_ID_MEILHAUS_ME4680I 0x4681 // Isolated version
#define PCI_DEVICE_ID_MEILHAUS_ME4680S 0x4682 // Standard version with Sample and Hold
#define PCI_DEVICE_ID_MEILHAUS_ME4680IS 0x4683 // Isolated version with Sample and Hold
/*=============================================================================
Device names, for entries in /proc/..
===========================================================================*/
#define ME4000_NAME "me4000"
#define ME4000_AO_NAME "me4000_ao"
#define ME4000_AI_NAME "me4000_ai"
#define ME4000_DIO_NAME "me4000_dio"
#define ME4000_CNT_NAME "me4000_cnt"
#define ME4000_EXT_INT_NAME "me4000_ext_int"
/*=============================================================================
ME-4000 base register offsets
===========================================================================*/
#define ME4000_AO_00_CTRL_REG 0x00 // R/W
#define ME4000_AO_00_STATUS_REG 0x04 // R/_
#define ME4000_AO_00_FIFO_REG 0x08 // _/W
#define ME4000_AO_00_SINGLE_REG 0x0C // R/W
#define ME4000_AO_00_TIMER_REG 0x10 // _/W
#define ME4000_AO_01_CTRL_REG 0x18 // R/W
#define ME4000_AO_01_STATUS_REG 0x1C // R/_
#define ME4000_AO_01_FIFO_REG 0x20 // _/W
#define ME4000_AO_01_SINGLE_REG 0x24 // R/W
#define ME4000_AO_01_TIMER_REG 0x28 // _/W
#define ME4000_AO_02_CTRL_REG 0x30 // R/W
#define ME4000_AO_02_STATUS_REG 0x34 // R/_
#define ME4000_AO_02_FIFO_REG 0x38 // _/W
#define ME4000_AO_02_SINGLE_REG 0x3C // R/W
#define ME4000_AO_02_TIMER_REG 0x40 // _/W
#define ME4000_AO_03_CTRL_REG 0x48 // R/W
#define ME4000_AO_03_STATUS_REG 0x4C // R/_
#define ME4000_AO_03_FIFO_REG 0x50 // _/W
#define ME4000_AO_03_SINGLE_REG 0x54 // R/W
#define ME4000_AO_03_TIMER_REG 0x58 // _/W
#define ME4000_AI_CTRL_REG 0x74 // _/W
#define ME4000_AI_STATUS_REG 0x74 // R/_
#define ME4000_AI_CHANNEL_LIST_REG 0x78 // _/W
#define ME4000_AI_DATA_REG 0x7C // R/_
#define ME4000_AI_CHAN_TIMER_REG 0x80 // _/W
#define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 // _/W
#define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 // _/W
#define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8C // _/W
#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 // _/W
#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 // _/W
#define ME4000_AI_START_REG 0x98 // R/_
#define ME4000_IRQ_STATUS_REG 0x9C // R/_
#define ME4000_DIO_PORT_0_REG 0xA0 // R/W
#define ME4000_DIO_PORT_1_REG 0xA4 // R/W
#define ME4000_DIO_PORT_2_REG 0xA8 // R/W
#define ME4000_DIO_PORT_3_REG 0xAC // R/W
#define ME4000_DIO_DIR_REG 0xB0 // R/W
#define ME4000_AO_LOADSETREG_XX 0xB4 // R/W
#define ME4000_DIO_CTRL_REG 0xB8 // R/W
#define ME4000_AO_DEMUX_ADJUST_REG 0xBC // -/W
#define ME4000_AI_SAMPLE_COUNTER_REG 0xC0 // _/W
/*=============================================================================
Value to adjust Demux
===========================================================================*/
#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4C
/*=============================================================================
Counter base register offsets
===========================================================================*/
#define ME4000_CNT_COUNTER_0_REG 0x00
#define ME4000_CNT_COUNTER_1_REG 0x01
#define ME4000_CNT_COUNTER_2_REG 0x02
#define ME4000_CNT_CTRL_REG 0x03
/*=============================================================================
PLX base register offsets
===========================================================================*/
#define PLX_INTCSR 0x4C // Interrupt control and status register
#define PLX_ICR 0x50 // Initialization control register
/*=============================================================================
Bits for the PLX_ICSR register
===========================================================================*/
#define PLX_INTCSR_LOCAL_INT1_EN 0x01 // If set, local interrupt 1 is enabled (r/w)
#define PLX_INTCSR_LOCAL_INT1_POL 0x02 // If set, local interrupt 1 polarity is active high (r/w)
#define PLX_INTCSR_LOCAL_INT1_STATE 0x04 // If set, local interrupt 1 is active (r/_)
#define PLX_INTCSR_LOCAL_INT2_EN 0x08 // If set, local interrupt 2 is enabled (r/w)
#define PLX_INTCSR_LOCAL_INT2_POL 0x10 // If set, local interrupt 2 polarity is active high (r/w)
#define PLX_INTCSR_LOCAL_INT2_STATE 0x20 // If set, local interrupt 2 is active (r/_)
#define PLX_INTCSR_PCI_INT_EN 0x40 // If set, PCI interrupt is enabled (r/w)
#define PLX_INTCSR_SOFT_INT 0x80 // If set, a software interrupt is generated (r/w)
/*=============================================================================
Bits for the PLX_ICR register
===========================================================================*/
#define PLX_ICR_BIT_EEPROM_CLOCK_SET 0x01000000
#define PLX_ICR_BIT_EEPROM_CHIP_SELECT 0x02000000
#define PLX_ICR_BIT_EEPROM_WRITE 0x04000000
#define PLX_ICR_BIT_EEPROM_READ 0x08000000
#define PLX_ICR_BIT_EEPROM_VALID 0x10000000
#define PLX_ICR_MASK_EEPROM 0x1F000000
#define EEPROM_DELAY 1
/*=============================================================================
Bits for the ME4000_AO_CTRL_REG register
===========================================================================*/
#define ME4000_AO_CTRL_BIT_MODE_0 0x001
#define ME4000_AO_CTRL_BIT_MODE_1 0x002
#define ME4000_AO_CTRL_MASK_MODE 0x003
#define ME4000_AO_CTRL_BIT_STOP 0x004
#define ME4000_AO_CTRL_BIT_ENABLE_FIFO 0x008
#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG 0x010
#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE 0x020
#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP 0x080
#define ME4000_AO_CTRL_BIT_ENABLE_DO 0x100
#define ME4000_AO_CTRL_BIT_ENABLE_IRQ 0x200
#define ME4000_AO_CTRL_BIT_RESET_IRQ 0x400
#define ME4000_AO_CTRL_BIT_EX_TRIG_BOTH 0x800
/*=============================================================================
Bits for the ME4000_AO_STATUS_REG register
===========================================================================*/
#define ME4000_AO_STATUS_BIT_FSM 0x01
#define ME4000_AO_STATUS_BIT_FF 0x02
#define ME4000_AO_STATUS_BIT_HF 0x04
#define ME4000_AO_STATUS_BIT_EF 0x08
/*=============================================================================
Bits for the ME4000_AI_CTRL_REG register
===========================================================================*/
#define ME4000_AI_CTRL_BIT_MODE_0 0x00000001
#define ME4000_AI_CTRL_BIT_MODE_1 0x00000002
#define ME4000_AI_CTRL_BIT_MODE_2 0x00000004
#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD 0x00000008
#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP 0x00000010
#define ME4000_AI_CTRL_BIT_STOP 0x00000020
#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO 0x00000040
#define ME4000_AI_CTRL_BIT_DATA_FIFO 0x00000080
#define ME4000_AI_CTRL_BIT_FULLSCALE 0x00000100
#define ME4000_AI_CTRL_BIT_OFFSET 0x00000200
#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG 0x00000400
#define ME4000_AI_CTRL_BIT_EX_TRIG 0x00000800
#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING 0x00001000
#define ME4000_AI_CTRL_BIT_EX_IRQ 0x00002000
#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET 0x00004000
#define ME4000_AI_CTRL_BIT_LE_IRQ 0x00008000
#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET 0x00010000
#define ME4000_AI_CTRL_BIT_HF_IRQ 0x00020000
#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET 0x00040000
#define ME4000_AI_CTRL_BIT_SC_IRQ 0x00080000
#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET 0x00100000
#define ME4000_AI_CTRL_BIT_SC_RELOAD 0x00200000
#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH 0x80000000
/*=============================================================================
Bits for the ME4000_AI_STATUS_REG register
===========================================================================*/
#define ME4000_AI_STATUS_BIT_EF_CHANNEL 0x00400000
#define ME4000_AI_STATUS_BIT_HF_CHANNEL 0x00800000
#define ME4000_AI_STATUS_BIT_FF_CHANNEL 0x01000000
#define ME4000_AI_STATUS_BIT_EF_DATA 0x02000000
#define ME4000_AI_STATUS_BIT_HF_DATA 0x04000000
#define ME4000_AI_STATUS_BIT_FF_DATA 0x08000000
#define ME4000_AI_STATUS_BIT_LE 0x10000000
#define ME4000_AI_STATUS_BIT_FSM 0x20000000
/*=============================================================================
Bits for the ME4000_IRQ_STATUS_REG register
===========================================================================*/
#define ME4000_IRQ_STATUS_BIT_EX 0x01
#define ME4000_IRQ_STATUS_BIT_LE 0x02
#define ME4000_IRQ_STATUS_BIT_AI_HF 0x04
#define ME4000_IRQ_STATUS_BIT_AO_0_HF 0x08
#define ME4000_IRQ_STATUS_BIT_AO_1_HF 0x10
#define ME4000_IRQ_STATUS_BIT_AO_2_HF 0x20
#define ME4000_IRQ_STATUS_BIT_AO_3_HF 0x40
#define ME4000_IRQ_STATUS_BIT_SC 0x80
/*=============================================================================
Bits for the ME4000_DIO_CTRL_REG register
===========================================================================*/
#define ME4000_DIO_CTRL_BIT_MODE_0 0X0001
#define ME4000_DIO_CTRL_BIT_MODE_1 0X0002
#define ME4000_DIO_CTRL_BIT_MODE_2 0X0004
#define ME4000_DIO_CTRL_BIT_MODE_3 0X0008
#define ME4000_DIO_CTRL_BIT_MODE_4 0X0010
#define ME4000_DIO_CTRL_BIT_MODE_5 0X0020
#define ME4000_DIO_CTRL_BIT_MODE_6 0X0040
#define ME4000_DIO_CTRL_BIT_MODE_7 0X0080
#define ME4000_DIO_CTRL_BIT_FUNCTION_0 0X0100
#define ME4000_DIO_CTRL_BIT_FUNCTION_1 0X0200
#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 0X0400
#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 0X0800
#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 0X1000
#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 0X2000
/*=============================================================================
Bits for the ME4000_CNT_CTRL_REG register
===========================================================================*/
#define ME4000_CNT_CTRL_BIT_COUNTER_0 0x00
#define ME4000_CNT_CTRL_BIT_COUNTER_1 0x40
#define ME4000_CNT_CTRL_BIT_COUNTER_2 0x80
#define ME4000_CNT_CTRL_BIT_MODE_0 0x00 // Change state if zero crossing
#define ME4000_CNT_CTRL_BIT_MODE_1 0x02 // Retriggerable One-Shot
#define ME4000_CNT_CTRL_BIT_MODE_2 0x04 // Asymmetrical divider
#define ME4000_CNT_CTRL_BIT_MODE_3 0x06 // Symmetrical divider
#define ME4000_CNT_CTRL_BIT_MODE_4 0x08 // Counter start by software trigger
#define ME4000_CNT_CTRL_BIT_MODE_5 0x0A // Counter start by hardware trigger
/*=============================================================================
Extract information from minor device number
===========================================================================*/
#define AO_BOARD(dev) ((MINOR(dev) >> 6) & 0x3)
#define AO_PORT(dev) ((MINOR(dev) >> 2) & 0xF)
#define AO_MODE(dev) (MINOR(dev) & 0x3)
#define AI_BOARD(dev) ((MINOR(dev) >> 3) & 0x1F)
#define AI_MODE(dev) (MINOR(dev) & 0x7)
#define DIO_BOARD(dev) (MINOR(dev))
#define CNT_BOARD(dev) (MINOR(dev))
#define EXT_INT_BOARD(dev) (MINOR(dev))
/*=============================================================================
Circular buffer used for analog input/output reads/writes.
===========================================================================*/
typedef struct me4000_circ_buf {
s16 *buf;
int volatile head;
int volatile tail;
} me4000_circ_buf_t;
/*=============================================================================
Information about the hardware capabilities
===========================================================================*/
typedef struct me4000_ao_info {
int count;
int fifo_count;
} me4000_ao_info_t;
typedef struct me4000_ai_info {
int count;
int sh_count;
int diff_count;
int ex_trig_analog;
} me4000_ai_info_t;
typedef struct me4000_dio_info {
int count;
} me4000_dio_info_t;
typedef struct me4000_cnt_info {
int count;
} me4000_cnt_info_t;
typedef struct me4000_board {
u16 vendor_id;
u16 device_id;
me4000_ao_info_t ao;
me4000_ai_info_t ai;
me4000_dio_info_t dio;
me4000_cnt_info_t cnt;
} me4000_board_t;
static me4000_board_t me4000_boards[] = {
{PCI_VENDOR_ID_MEILHAUS, 0x4610, {0, 0}, {16, 0, 0, 0}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4650, {0, 0}, {16, 0, 0, 0}, {4}, {0}},
{PCI_VENDOR_ID_MEILHAUS, 0x4660, {2, 0}, {16, 0, 0, 0}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4661, {2, 0}, {16, 0, 0, 0}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4662, {2, 0}, {16, 8, 0, 0}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4663, {2, 0}, {16, 8, 0, 0}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4670, {4, 0}, {32, 0, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4671, {4, 0}, {32, 0, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4672, {4, 0}, {32, 8, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4673, {4, 0}, {32, 8, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4680, {4, 4}, {32, 0, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4681, {4, 4}, {32, 0, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4682, {4, 4}, {32, 8, 16, 1}, {4}, {3}},
{PCI_VENDOR_ID_MEILHAUS, 0x4683, {4, 4}, {32, 8, 16, 1}, {4}, {3}},
{0},
};
#define ME4000_BOARD_VERSIONS (sizeof(me4000_boards) / sizeof(me4000_board_t) - 1)
/*=============================================================================
PCI device table.
This is used by modprobe to translate PCI IDs to drivers.
===========================================================================*/
static struct pci_device_id me4000_pci_table[] __devinitdata = {
{PCI_VENDOR_ID_MEILHAUS, 0x4610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4661, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4662, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4670, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4671, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4672, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4673, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4682, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{PCI_VENDOR_ID_MEILHAUS, 0x4683, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
{0}
};
MODULE_DEVICE_TABLE(pci, me4000_pci_table);
/*=============================================================================
Global board and subdevice information structures
===========================================================================*/
typedef struct me4000_info {
struct list_head list; // List of all detected boards
int board_count; // Index of the board after detection
unsigned long plx_regbase; // PLX configuration space base address
unsigned long me4000_regbase; // Base address of the ME4000
unsigned long timer_regbase; // Base address of the timer circuit
unsigned long program_regbase; // Base address to set the program pin for the xilinx
unsigned long plx_regbase_size; // PLX register set space
unsigned long me4000_regbase_size; // ME4000 register set space
unsigned long timer_regbase_size; // Timer circuit register set space
unsigned long program_regbase_size; // Size of program base address of the ME4000
unsigned int serial_no; // Serial number of the board
unsigned char hw_revision; // Hardware revision of the board
unsigned short vendor_id; // Meilhaus vendor id (0x1402)
unsigned short device_id; // Device ID
int pci_bus_no; // PCI bus number
int pci_dev_no; // PCI device number
int pci_func_no; // PCI function number
struct pci_dev *pci_dev_p; // General PCI information
me4000_board_t *board_p; // Holds the board capabilities
unsigned int irq; // IRQ assigned from the PCI BIOS
unsigned int irq_count; // Count of external interrupts
spinlock_t preload_lock; // Guards the analog output preload register
spinlock_t ai_ctrl_lock; // Guards the analog input control register
struct list_head ao_context_list; // List with analog output specific context
struct me4000_ai_context *ai_context; // Analog input specific context
struct me4000_dio_context *dio_context; // Digital I/O specific context
struct me4000_cnt_context *cnt_context; // Counter specific context
struct me4000_ext_int_context *ext_int_context; // External interrupt specific context
} me4000_info_t;
typedef struct me4000_ao_context {
struct list_head list; // linked list of me4000_ao_context_t
int index; // Index in the list
int mode; // Indicates mode (0 = single, 1 = wraparound, 2 = continous)
int dac_in_use; // Indicates if already opend
spinlock_t use_lock; // Guards in_use
spinlock_t int_lock; // Used when locking out interrupts
me4000_circ_buf_t circ_buf; // Circular buffer
wait_queue_head_t wait_queue; // Wait queue to sleep while blocking write
me4000_info_t *board_info;
unsigned int irq; // The irq associated with this ADC
int volatile pipe_flag; // Indicates broken pipe set from me4000_ao_isr()
unsigned long ctrl_reg;
unsigned long status_reg;
unsigned long fifo_reg;
unsigned long single_reg;
unsigned long timer_reg;
unsigned long irq_status_reg;
unsigned long preload_reg;
struct fasync_struct *fasync_p; // Queue for asynchronous notification
} me4000_ao_context_t;
typedef struct me4000_ai_context {
struct list_head list; // linked list of me4000_ai_info_t
int mode; // Indicates mode
int in_use; // Indicates if already opend
spinlock_t use_lock; // Guards in_use
spinlock_t int_lock; // Used when locking out interrupts
int number; // Number of the DAC
unsigned int irq; // The irq associated with this ADC
me4000_circ_buf_t circ_buf; // Circular buffer
wait_queue_head_t wait_queue; // Wait queue to sleep while blocking read
me4000_info_t *board_info;
struct fasync_struct *fasync_p; // Queue for asynchronous notification
unsigned long ctrl_reg;
unsigned long status_reg;
unsigned long channel_list_reg;
unsigned long data_reg;
unsigned long chan_timer_reg;
unsigned long chan_pre_timer_reg;
unsigned long scan_timer_low_reg;
unsigned long scan_timer_high_reg;
unsigned long scan_pre_timer_low_reg;
unsigned long scan_pre_timer_high_reg;
unsigned long start_reg;
unsigned long irq_status_reg;
unsigned long sample_counter_reg;
unsigned long chan_timer;
unsigned long chan_pre_timer;
unsigned long scan_timer_low;
unsigned long scan_timer_high;
unsigned long channel_list_count;
unsigned long sample_counter;
int sample_counter_reload;
} me4000_ai_context_t;
typedef struct me4000_dio_context {
struct list_head list; // linked list of me4000_dio_context_t
int in_use; // Indicates if already opend
spinlock_t use_lock; // Guards in_use
int number;
int dio_count;
me4000_info_t *board_info;
unsigned long dir_reg;
unsigned long ctrl_reg;
unsigned long port_0_reg;
unsigned long port_1_reg;
unsigned long port_2_reg;
unsigned long port_3_reg;
} me4000_dio_context_t;
typedef struct me4000_cnt_context {
struct list_head list; // linked list of me4000_dio_context_t
int in_use; // Indicates if already opend
spinlock_t use_lock; // Guards in_use
int number;
int cnt_count;
me4000_info_t *board_info;
unsigned long ctrl_reg;
unsigned long counter_0_reg;
unsigned long counter_1_reg;
unsigned long counter_2_reg;
} me4000_cnt_context_t;
typedef struct me4000_ext_int_context {
struct list_head list; // linked list of me4000_dio_context_t
int in_use; // Indicates if already opend
spinlock_t use_lock; // Guards in_use
int number;
me4000_info_t *board_info;
unsigned int irq;
unsigned long int_count;
struct fasync_struct *fasync_ptr;
unsigned long ctrl_reg;
unsigned long irq_status_reg;
} me4000_ext_int_context_t;
#endif
/*=============================================================================
Application include section starts here
===========================================================================*/
/*-----------------------------------------------------------------------------
Defines for analog input
----------------------------------------------------------------------------*/
/* General stuff */
#define ME4000_AI_FIFO_COUNT 2048
#define ME4000_AI_MIN_TICKS 66
#define ME4000_AI_MAX_SCAN_TICKS 0xFFFFFFFFFFLL
#define ME4000_AI_BUFFER_SIZE (32 * 1024) // Size in bytes
#define ME4000_AI_BUFFER_COUNT ((ME4000_AI_BUFFER_SIZE) / 2) // Size in values
/* Channel list defines and masks */
#define ME4000_AI_CHANNEL_LIST_COUNT 1024
#define ME4000_AI_LIST_INPUT_SINGLE_ENDED 0x000
#define ME4000_AI_LIST_INPUT_DIFFERENTIAL 0x020
#define ME4000_AI_LIST_RANGE_BIPOLAR_10 0x000
#define ME4000_AI_LIST_RANGE_BIPOLAR_2_5 0x040
#define ME4000_AI_LIST_RANGE_UNIPOLAR_10 0x080
#define ME4000_AI_LIST_RANGE_UNIPOLAR_2_5 0x0C0
#define ME4000_AI_LIST_LAST_ENTRY 0x100
/* External trigger defines */
#define ME4000_AI_TRIGGER_SOFTWARE 0x0 // Use only with API
#define ME4000_AI_TRIGGER_EXT_DIGITAL 0x1
#define ME4000_AI_TRIGGER_EXT_ANALOG 0x2
#define ME4000_AI_TRIGGER_EXT_EDGE_RISING 0x0
#define ME4000_AI_TRIGGER_EXT_EDGE_FALLING 0x1
#define ME4000_AI_TRIGGER_EXT_EDGE_BOTH 0x2
/* Sample and Hold */
#define ME4000_AI_SIMULTANEOUS_DISABLE 0x0
#define ME4000_AI_SIMULTANEOUS_ENABLE 0x1
/* Defines for the Sample Counter */
#define ME4000_AI_SC_RELOAD 0x0
#define ME4000_AI_SC_ONCE 0x1
/* Modes for analog input */
#define ME4000_AI_ACQ_MODE_SINGLE 0x00 // Catch one single value
#define ME4000_AI_ACQ_MODE_SOFTWARE 0x01 // Continous sampling with software start
#define ME4000_AI_ACQ_MODE_EXT 0x02 // Continous sampling with external trigger start
#define ME4000_AI_ACQ_MODE_EXT_SINGLE_VALUE 0x03 // Sample one value by external trigger
#define ME4000_AI_ACQ_MODE_EXT_SINGLE_CHANLIST 0x04 // Sample one channel list by external trigger
/* Staus of AI FSM */
#define ME4000_AI_STATUS_IDLE 0x0
#define ME4000_AI_STATUS_BUSY 0x1
/* Voltages for calibration */
#define ME4000_AI_GAIN_1_UNI_OFFSET 10.0E-3
#define ME4000_AI_GAIN_1_UNI_FULLSCALE 9950.0E-3
#define ME4000_AI_GAIN_1_BI_OFFSET 0.0
#define ME4000_AI_GAIN_1_BI_FULLSCALE 9950.0E-3
#define ME4000_AI_GAIN_4_UNI_OFFSET 10.0E-3
#define ME4000_AI_GAIN_4_UNI_FULLSCALE 2450.0E-3
#define ME4000_AI_GAIN_4_BI_OFFSET 0.0
#define ME4000_AI_GAIN_4_BI_FULLSCALE 2450.0E-3
/* Ideal digits for calibration */
#define ME4000_AI_GAIN_1_UNI_OFFSET_DIGITS (-32702)
#define ME4000_AI_GAIN_1_UNI_FULLSCALE_DIGITS 32440
#define ME4000_AI_GAIN_1_BI_OFFSET_DIGITS 0
#define ME4000_AI_GAIN_1_BI_FULLSCALE_DIGITS 32604
#define ME4000_AI_GAIN_4_UNI_OFFSET_DIGITS (-32505)
#define ME4000_AI_GAIN_4_UNI_FULLSCALE_DIGITS 31457
#define ME4000_AI_GAIN_4_BI_OFFSET_DIGITS 0
#define ME4000_AI_GAIN_4_BI_FULLSCALE_DIGITS 32113
/*-----------------------------------------------------------------------------
Defines for analog output
----------------------------------------------------------------------------*/
/* General stuff */
#define ME4000_AO_FIFO_COUNT (4 * 1024)
#define ME4000_AO_MIN_TICKS 66
#define ME4000_AO_BUFFER_SIZE (32 * 1024) // Size in bytes
#define ME4000_AO_BUFFER_COUNT ((ME4000_AO_BUFFER_SIZE) / 2) // Size in values
/* Conversion modes for analog output */
#define ME4000_AO_CONV_MODE_SINGLE 0x0
#define ME4000_AO_CONV_MODE_WRAPAROUND 0x1
#define ME4000_AO_CONV_MODE_CONTINUOUS 0x2
/* Trigger setup */
#define ME4000_AO_TRIGGER_EXT_EDGE_RISING 0x0
#define ME4000_AO_TRIGGER_EXT_EDGE_FALLING 0x1
#define ME4000_AO_TRIGGER_EXT_EDGE_BOTH 0x2
/* Status of AO FSM */
#define ME4000_AO_STATUS_IDLE 0x0
#define ME4000_AO_STATUS_BUSY 0x1
/*-----------------------------------------------------------------------------
Defines for eeprom
----------------------------------------------------------------------------*/
#define ME4000_EEPROM_CMD_READ 0x180
#define ME4000_EEPROM_CMD_WRITE_ENABLE 0x130
#define ME4000_EEPROM_CMD_WRITE_DISABLE 0x100
#define ME4000_EEPROM_CMD_WRITE 0x1400000
#define ME4000_EEPROM_CMD_LENGTH_READ 9
#define ME4000_EEPROM_CMD_LENGTH_WRITE_ENABLE 9
#define ME4000_EEPROM_CMD_LENGTH_WRITE_DISABLE 9
#define ME4000_EEPROM_CMD_LENGTH_WRITE 25
#define ME4000_EEPROM_ADR_DATE_HIGH 0x32
#define ME4000_EEPROM_ADR_DATE_LOW 0x33
#define ME4000_EEPROM_ADR_GAIN_1_UNI_OFFSET 0x34
#define ME4000_EEPROM_ADR_GAIN_1_UNI_FULLSCALE 0x35
#define ME4000_EEPROM_ADR_GAIN_1_BI_OFFSET 0x36
#define ME4000_EEPROM_ADR_GAIN_1_BI_FULLSCALE 0x37
#define ME4000_EEPROM_ADR_GAIN_1_DIFF_OFFSET 0x38
#define ME4000_EEPROM_ADR_GAIN_1_DIFF_FULLSCALE 0x39
#define ME4000_EEPROM_ADR_GAIN_4_UNI_OFFSET 0x3A
#define ME4000_EEPROM_ADR_GAIN_4_UNI_FULLSCALE 0x3B
#define ME4000_EEPROM_ADR_GAIN_4_BI_OFFSET 0x3C
#define ME4000_EEPROM_ADR_GAIN_4_BI_FULLSCALE 0x3D
#define ME4000_EEPROM_ADR_GAIN_4_DIFF_OFFSET 0x3E
#define ME4000_EEPROM_ADR_GAIN_4_DIFF_FULLSCALE 0x3F
#define ME4000_EEPROM_ADR_LENGTH 6
#define ME4000_EEPROM_DATA_LENGTH 16
/*-----------------------------------------------------------------------------
Defines for digital I/O
----------------------------------------------------------------------------*/
#define ME4000_DIO_PORT_A 0x0
#define ME4000_DIO_PORT_B 0x1
#define ME4000_DIO_PORT_C 0x2
#define ME4000_DIO_PORT_D 0x3
#define ME4000_DIO_PORT_INPUT 0x0
#define ME4000_DIO_PORT_OUTPUT 0x1
#define ME4000_DIO_FIFO_LOW 0x2
#define ME4000_DIO_FIFO_HIGH 0x3
#define ME4000_DIO_FUNCTION_PATTERN 0x0
#define ME4000_DIO_FUNCTION_DEMUX 0x1
#define ME4000_DIO_FUNCTION_MUX 0x2
/*-----------------------------------------------------------------------------
Defines for counters
----------------------------------------------------------------------------*/
#define ME4000_CNT_COUNTER_0 0
#define ME4000_CNT_COUNTER_1 1
#define ME4000_CNT_COUNTER_2 2
#define ME4000_CNT_MODE_0 0 // Change state if zero crossing
#define ME4000_CNT_MODE_1 1 // Retriggerable One-Shot
#define ME4000_CNT_MODE_2 2 // Asymmetrical divider
#define ME4000_CNT_MODE_3 3 // Symmetrical divider
#define ME4000_CNT_MODE_4 4 // Counter start by software trigger
#define ME4000_CNT_MODE_5 5 // Counter start by hardware trigger
/*-----------------------------------------------------------------------------
General type definitions
----------------------------------------------------------------------------*/
typedef struct me4000_user_info {
int board_count; // Index of the board after detection
unsigned long plx_regbase; // PLX configuration space base address
unsigned long me4000_regbase; // Base address of the ME4000
unsigned long plx_regbase_size; // PLX register set space
unsigned long me4000_regbase_size; // ME4000 register set space
unsigned long serial_no; // Serial number of the board
unsigned char hw_revision; // Hardware revision of the board
unsigned short vendor_id; // Meilhaus vendor id (0x1402)
unsigned short device_id; // Device ID
int pci_bus_no; // PCI bus number
int pci_dev_no; // PCI device number
int pci_func_no; // PCI function number
char irq; // IRQ assigned from the PCI BIOS
int irq_count; // Count of external interrupts
int driver_version; // Version of the driver release
int ao_count; // Count of analog output channels
int ao_fifo_count; // Count fo analog output fifos
int ai_count; // Count of analog input channels
int ai_sh_count; // Count of sample and hold devices
int ai_ex_trig_analog; // Flag to indicate if analogous external trigger is available
int dio_count; // Count of digital I/O ports
int cnt_count; // Count of counters
} me4000_user_info_t;
/*-----------------------------------------------------------------------------
Type definitions for analog output
----------------------------------------------------------------------------*/
typedef struct me4000_ao_channel_list {
unsigned long count;
unsigned long *list;
} me4000_ao_channel_list_t;
/*-----------------------------------------------------------------------------
Type definitions for analog input
----------------------------------------------------------------------------*/
typedef struct me4000_ai_channel_list {
unsigned long count;
unsigned long *list;
} me4000_ai_channel_list_t;
typedef struct me4000_ai_timer {
unsigned long pre_chan;
unsigned long chan;
unsigned long scan_low;
unsigned long scan_high;
} me4000_ai_timer_t;
typedef struct me4000_ai_config {
me4000_ai_timer_t timer;
me4000_ai_channel_list_t channel_list;
int sh;
} me4000_ai_config_t;
typedef struct me4000_ai_single {
int channel;
int range;
int mode;
short value;
unsigned long timeout;
} me4000_ai_single_t;
typedef struct me4000_ai_trigger {
int mode;
int edge;
} me4000_ai_trigger_t;
typedef struct me4000_ai_sc {
unsigned long value;
int reload;
} me4000_ai_sc_t;
/*-----------------------------------------------------------------------------
Type definitions for eeprom
----------------------------------------------------------------------------*/
typedef struct me4000_eeprom {
unsigned long date;
short uni_10_offset;
short uni_10_fullscale;
short uni_2_5_offset;
short uni_2_5_fullscale;
short bi_10_offset;
short bi_10_fullscale;
short bi_2_5_offset;
short bi_2_5_fullscale;
short diff_10_offset;
short diff_10_fullscale;
short diff_2_5_offset;
short diff_2_5_fullscale;
} me4000_eeprom_t;
/*-----------------------------------------------------------------------------
Type definitions for digital I/O
----------------------------------------------------------------------------*/
typedef struct me4000_dio_config {
int port;
int mode;
int function;
} me4000_dio_config_t;
typedef struct me4000_dio_byte {
int port;
unsigned char byte;
} me4000_dio_byte_t;
/*-----------------------------------------------------------------------------
Type definitions for counters
----------------------------------------------------------------------------*/
typedef struct me4000_cnt {
int counter;
unsigned short value;
} me4000_cnt_t;
typedef struct me4000_cnt_config {
int counter;
int mode;
} me4000_cnt_config_t;
/*-----------------------------------------------------------------------------
Type definitions for external interrupt
----------------------------------------------------------------------------*/
typedef struct {
int int1_count;
int int2_count;
} me4000_int_type;
/*-----------------------------------------------------------------------------
The ioctls of the board
----------------------------------------------------------------------------*/
#define ME4000_IOCTL_MAXNR 50
#define ME4000_MAGIC 'y'
#define ME4000_GET_USER_INFO _IOR (ME4000_MAGIC, 0, me4000_user_info_t)
#define ME4000_AO_START _IOW (ME4000_MAGIC, 1, unsigned long)
#define ME4000_AO_STOP _IO (ME4000_MAGIC, 2)
#define ME4000_AO_IMMEDIATE_STOP _IO (ME4000_MAGIC, 3)
#define ME4000_AO_RESET _IO (ME4000_MAGIC, 4)
#define ME4000_AO_PRELOAD _IO (ME4000_MAGIC, 5)
#define ME4000_AO_PRELOAD_UPDATE _IO (ME4000_MAGIC, 6)
#define ME4000_AO_EX_TRIG_ENABLE _IO (ME4000_MAGIC, 7)
#define ME4000_AO_EX_TRIG_DISABLE _IO (ME4000_MAGIC, 8)
#define ME4000_AO_EX_TRIG_SETUP _IOW (ME4000_MAGIC, 9, int)
#define ME4000_AO_TIMER_SET_DIVISOR _IOW (ME4000_MAGIC, 10, unsigned long)
#define ME4000_AO_ENABLE_DO _IO (ME4000_MAGIC, 11)
#define ME4000_AO_DISABLE_DO _IO (ME4000_MAGIC, 12)
#define ME4000_AO_FSM_STATE _IOR (ME4000_MAGIC, 13, int)
#define ME4000_AI_SINGLE _IOR (ME4000_MAGIC, 14, me4000_ai_single_t)
#define ME4000_AI_START _IOW (ME4000_MAGIC, 15, unsigned long)
#define ME4000_AI_STOP _IO (ME4000_MAGIC, 16)
#define ME4000_AI_IMMEDIATE_STOP _IO (ME4000_MAGIC, 17)
#define ME4000_AI_EX_TRIG_ENABLE _IO (ME4000_MAGIC, 18)
#define ME4000_AI_EX_TRIG_DISABLE _IO (ME4000_MAGIC, 19)
#define ME4000_AI_EX_TRIG_SETUP _IOW (ME4000_MAGIC, 20, me4000_ai_trigger_t)
#define ME4000_AI_CONFIG _IOW (ME4000_MAGIC, 21, me4000_ai_config_t)
#define ME4000_AI_SC_SETUP _IOW (ME4000_MAGIC, 22, me4000_ai_sc_t)
#define ME4000_AI_FSM_STATE _IOR (ME4000_MAGIC, 23, int)
#define ME4000_DIO_CONFIG _IOW (ME4000_MAGIC, 24, me4000_dio_config_t)
#define ME4000_DIO_GET_BYTE _IOR (ME4000_MAGIC, 25, me4000_dio_byte_t)
#define ME4000_DIO_SET_BYTE _IOW (ME4000_MAGIC, 26, me4000_dio_byte_t)
#define ME4000_DIO_RESET _IO (ME4000_MAGIC, 27)
#define ME4000_CNT_READ _IOR (ME4000_MAGIC, 28, me4000_cnt_t)
#define ME4000_CNT_WRITE _IOW (ME4000_MAGIC, 29, me4000_cnt_t)
#define ME4000_CNT_CONFIG _IOW (ME4000_MAGIC, 30, me4000_cnt_config_t)
#define ME4000_CNT_RESET _IO (ME4000_MAGIC, 31)
#define ME4000_EXT_INT_DISABLE _IO (ME4000_MAGIC, 32)
#define ME4000_EXT_INT_ENABLE _IO (ME4000_MAGIC, 33)
#define ME4000_EXT_INT_COUNT _IOR (ME4000_MAGIC, 34, int)
#define ME4000_AI_OFFSET_ENABLE _IO (ME4000_MAGIC, 35)
#define ME4000_AI_OFFSET_DISABLE _IO (ME4000_MAGIC, 36)
#define ME4000_AI_FULLSCALE_ENABLE _IO (ME4000_MAGIC, 37)
#define ME4000_AI_FULLSCALE_DISABLE _IO (ME4000_MAGIC, 38)
#define ME4000_AI_EEPROM_READ _IOR (ME4000_MAGIC, 39, me4000_eeprom_t)
#define ME4000_AI_EEPROM_WRITE _IOW (ME4000_MAGIC, 40, me4000_eeprom_t)
#define ME4000_AO_SIMULTANEOUS_EX_TRIG _IO (ME4000_MAGIC, 41)
#define ME4000_AO_SIMULTANEOUS_SW _IO (ME4000_MAGIC, 42)
#define ME4000_AO_SIMULTANEOUS_DISABLE _IO (ME4000_MAGIC, 43)
#define ME4000_AO_SIMULTANEOUS_UPDATE _IOW (ME4000_MAGIC, 44, me4000_ao_channel_list_t)
#define ME4000_AO_SYNCHRONOUS_EX_TRIG _IO (ME4000_MAGIC, 45)
#define ME4000_AO_SYNCHRONOUS_SW _IO (ME4000_MAGIC, 46)
#define ME4000_AO_SYNCHRONOUS_DISABLE _IO (ME4000_MAGIC, 47)
#define ME4000_AO_EX_TRIG_TIMEOUT _IOW (ME4000_MAGIC, 48, unsigned long)
#define ME4000_AO_GET_FREE_BUFFER _IOR (ME4000_MAGIC, 49, unsigned long)
#define ME4000_AI_GET_COUNT_BUFFER _IOR (ME4000_MAGIC, 50, unsigned long)
#endif

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drivers/staging/me4000/me4000_firmware.h Normal file
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drivers/staging/me4000/me4610_firmware.h Normal file
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config SLICOSS
tristate "Alacritech Gigabit IS-NIC support"
depends on PCI && X86 && NETDEV_1000
default n
help
This driver supports Alacritech's IS-NIC gigabit ethernet cards.
This includes the following devices:
Mojave cards (single port PCI Gigabit) both copper and fiber
Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
To compile this driver as a module, choose M here: the module
will be called slicoss.

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drivers/staging/slicoss/Makefile Normal file
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obj-$(CONFIG_SLICOSS) += slicoss.o

19
drivers/staging/slicoss/README Normal file
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This driver is supposed to support:
Mojave cards (single port PCI Gigabit) both copper and fiber
Oasis cards (single and dual port PCI-x Gigabit) copper and fiber
Kalahari cards (dual and quad port PCI-e Gigabit) copper and fiber
The driver was actually tested on Oasis and Kalahari cards.
TODO:
- move firmware loading to request_firmware()
- remove direct memory access of structures
- any remaining sparse and checkpatch.pl warnings
- any netdev recommended changes
Please send patches to:
Greg Kroah-Hartman <gregkh@suse.de>
and Cc: Lior Dotan <liodot@gmail.com> and Christopher Harrer
<charrer@alacritech.com> as well as they are also able to test out any
changes.

8215
drivers/staging/slicoss/gbdownload.h Normal file
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drivers/staging/slicoss/gbrcvucode.h Normal file
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/*
* Copyright (c) 1997-2002 Alacritech, Inc. All rights reserved
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
#define GB_RCVUCODE_VERS_STRING "1.2"
#define GB_RCVUCODE_VERS_DATE "2006/03/27 15:12:15"
static u32 GBRcvUCodeLen = 512;
static u8 GBRcvUCode[2560] =
{
0x47, 0x75, 0x01, 0x00, 0x04, 0xa0, 0x13, 0x01, 0x00, 0x1c, 0xb7, 0x5b, 0x09,
0x30, 0x00, 0xb6, 0x5f, 0x01, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x18, 0x3b,
0x78, 0x3a, 0x00, 0x1c, 0xa2, 0x77, 0x01, 0x00, 0x1c, 0x07, 0x1d, 0x01, 0x70,
0x18, 0xb3, 0x7b, 0xa9, 0xaa, 0x1e, 0xb4, 0x7b, 0x01, 0x0c, 0x1c, 0xb5, 0x7b,
0x1d, 0x06, 0x1c, 0x00, 0x00, 0x40, 0x64, 0x08, 0x0c, 0x31, 0x56, 0x70, 0x04,
0x0c, 0x31, 0x56, 0x80, 0x04, 0x0c, 0x31, 0x4a, 0x90, 0x04, 0x0c, 0x31, 0x46,
0xa0, 0x00, 0x09, 0x25, 0x51, 0xc0, 0x04, 0x0c, 0x31, 0x4e, 0xb0, 0x00, 0xe9,
0x24, 0x51, 0xc0, 0x04, 0xcc, 0xb3, 0x00, 0x1c, 0x1c, 0xeb, 0x2d, 0x01, 0x00,
0x1c, 0x06, 0x56, 0x42, 0xd4, 0x08, 0x07, 0x9d, 0x00, 0x00, 0x1c, 0x7b, 0xb7,
0x02, 0x00, 0x10, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0x06, 0x56, 0x5a, 0xc0, 0x04,
0xa0, 0x30, 0x6c, 0x03, 0x00, 0xac, 0x30, 0x6d, 0x03, 0x00, 0xcd, 0x03, 0x3a,
0x00, 0x1c, 0x7b, 0xb7, 0x02, 0x00, 0x1c, 0x60, 0x8e, 0x41, 0x54, 0x09, 0x29,
0x25, 0x6d, 0x03, 0x00, 0x80, 0x8e, 0x41, 0x54, 0x09, 0x8c, 0x30, 0x8d, 0x00,
0x04, 0x47, 0x1c, 0x01, 0x00, 0x1c, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0x00, 0x00,
0x60, 0x00, 0x04, 0x47, 0x1c, 0x61, 0xc0, 0x04, 0x47, 0x1c, 0x6d, 0x03, 0x00,
0x6c, 0x30, 0x01, 0x00, 0x1c, 0x4d, 0x34, 0x02, 0x00, 0x1c, 0x7b, 0xb7, 0x02,
0x00, 0x1c, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xc8, 0x83, 0x37, 0x00, 0x1c, 0x80,
0x01, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x60, 0x00, 0x04, 0xa0, 0x0f, 0x40, 0x54,
0x09, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x7b, 0xfb, 0xf2, 0x00, 0x1c, 0xcc, 0x33,
0x0d, 0x00, 0x1c, 0xb4, 0x7b, 0xfd, 0x03, 0x1c, 0x80, 0x0e, 0x40, 0x54, 0x09,
0xe0, 0xfb, 0x05, 0x00, 0x1c, 0x00, 0x00, 0xa0, 0x03, 0x00, 0xb3, 0x0f, 0x41,
0x54, 0x09, 0x00, 0x00, 0xe8, 0x70, 0x04, 0x00, 0x00, 0xe8, 0x80, 0x04, 0x00,
0x00, 0xa0, 0x93, 0x00, 0x61, 0x76, 0xa1, 0xc3, 0x04, 0xc0, 0x8d, 0x41, 0x54,
0x09, 0xe0, 0x7b, 0x00, 0xc0, 0x1f, 0xa0, 0xfd, 0xc1, 0x01, 0x00, 0xcc, 0x33,
0x05, 0x00, 0x1c, 0xd4, 0x03, 0x00, 0x3c, 0x1c, 0xd4, 0xd3, 0x1b, 0x00, 0x1c,
0xc0, 0xd3, 0x52, 0x00, 0x1c, 0x00, 0x00, 0x74, 0x13, 0x04, 0x8e, 0x8e, 0x42,
0x54, 0x09, 0x5b, 0x80, 0x76, 0x13, 0x04, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00,
0x00, 0x90, 0x01, 0x00, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xa0, 0x0f, 0x41, 0x54,
0x09, 0xc0, 0x03, 0xfc, 0x7f, 0x1c, 0xa0, 0x01, 0x9c, 0x01, 0x00, 0x00, 0x00,
0xa0, 0x01, 0x00, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xc0, 0x03, 0xfc, 0x03, 0x1c,
0xf5, 0x77, 0x01, 0x00, 0x1c, 0x26, 0x7a, 0xf6, 0x05, 0x1c, 0xa0, 0x0f, 0x41,
0x54, 0x09, 0xb3, 0x0f, 0x41, 0x54, 0x09, 0xb5, 0x02, 0x02, 0x00, 0x1c, 0xa0,
0x0f, 0x41, 0x54, 0x09, 0x7a, 0x06, 0x02, 0x00, 0x1c, 0xb5, 0x02, 0x02, 0x00,
0x1c, 0x53, 0x0f, 0x42, 0x54, 0x09, 0xaf, 0x03, 0x01, 0x00, 0x1c, 0x7a, 0x0e,
0x42, 0x54, 0x09, 0xb5, 0x02, 0x02, 0x00, 0x1c, 0x00, 0x00, 0x02, 0x00, 0x1c,
0xa0, 0x3d, 0xa6, 0x11, 0x04, 0x00, 0x00, 0xa8, 0x11, 0x04, 0xd4, 0xd3, 0x52,
0x00, 0x1c, 0xb5, 0x3e, 0xae, 0x01, 0x00, 0x20, 0xfb, 0xfd, 0xff, 0x1f, 0x80,
0x2c, 0x84, 0x03, 0x00, 0xb9, 0x3a, 0x9a, 0x01, 0x00, 0x75, 0x3b, 0x02, 0x00,
0x1c, 0xa7, 0x1c, 0x01, 0x00, 0x10, 0xdb, 0x83, 0x16, 0x00, 0x1c, 0xc7, 0x1d,
0x1d, 0xc1, 0x04, 0xb9, 0x3b, 0x89, 0xc1, 0x04, 0x8b, 0x2c, 0x01, 0x00, 0x1c,
0x6b, 0x2c, 0x31, 0xc1, 0x04, 0x00, 0x00, 0x74, 0x11, 0x00, 0xcb, 0x2c, 0x75,
0xc1, 0x04, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0x54,
0xd0, 0x02, 0x00, 0x1c, 0x49, 0x25, 0xad, 0x01, 0x00, 0xab, 0x2c, 0x7d, 0xc1,
0x04, 0xa7, 0x1d, 0x6d, 0x03, 0x00, 0xcc, 0x33, 0x09, 0x00, 0x1c, 0xeb, 0x2d,
0x01, 0x00, 0x1c, 0xea, 0x29, 0x01, 0x00, 0x1c, 0xa0, 0x0f, 0x41, 0x54, 0x09,
0xae, 0x0f, 0x41, 0x54, 0x09, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xd4, 0x07, 0xfc,
0x03, 0x1c, 0x99, 0x3a, 0x02, 0x00, 0x1c, 0xbb, 0x38, 0x02, 0x00, 0x1c, 0x00,
0x38, 0x00, 0x00, 0x1c, 0x00, 0x00, 0xf8, 0x01, 0x04, 0xdb, 0x3b, 0x7e, 0x00,
0x1c, 0xc7, 0x1d, 0x01, 0x00, 0x1c, 0x26, 0x7a, 0x0a, 0x06, 0x1c, 0x27, 0x1d,
0x01, 0x00, 0x1c, 0xb3, 0x0f, 0x41, 0x54, 0x09, 0x7a, 0x0e, 0x42, 0x54, 0x09,
0x53, 0x0f, 0x42, 0x54, 0x09, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0x53, 0x0f, 0x42,
0x54, 0x09, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0x53, 0x0f, 0x42, 0x54, 0x09, 0xa0,
0x0f, 0x41, 0x54, 0x09, 0x7a, 0x06, 0x02, 0x00, 0x1c, 0x53, 0x0f, 0x42, 0x54,
0x09, 0xaf, 0x03, 0x01, 0x00, 0x1c, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0x53, 0x0f,
0x42, 0x54, 0x09, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0x53, 0x0f, 0x42, 0x54, 0x09,
0x7a, 0x0e, 0x42, 0x54, 0x09, 0x53, 0x0f, 0x42, 0x54, 0x09, 0x7a, 0x0e, 0x42,
0x54, 0x09, 0x00, 0x3d, 0x02, 0x00, 0x1c, 0x00, 0x00, 0x54, 0x12, 0x00, 0xcb,
0x2c, 0x01, 0x00, 0x1c, 0x75, 0x3b, 0x02, 0x00, 0x1c, 0xa7, 0x1c, 0x01, 0x00,
0x10, 0xa6, 0x7b, 0xf1, 0x05, 0x1c, 0x00, 0x00, 0x88, 0xc2, 0x04, 0xa6, 0x7b,
0xf1, 0x05, 0x1c, 0x00, 0x00, 0xa0, 0xc2, 0x04, 0xcb, 0x2f, 0x05, 0x00, 0x1c,
0x60, 0x2c, 0x00, 0x00, 0x1c, 0xc7, 0x1c, 0xe1, 0x02, 0x00, 0x53, 0x0f, 0x42,
0x54, 0x09, 0xc0, 0x83, 0xf1, 0x32, 0x1c, 0x00, 0x00, 0x5c, 0x02, 0x04, 0x46,
0x7a, 0xda, 0x05, 0x1c, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0xc0, 0x83, 0xf1, 0x32,
0x1c, 0x00, 0x00, 0x64, 0x02, 0x04, 0x40, 0xfa, 0x15, 0x00, 0x1c, 0x00, 0x00,
0xa0, 0x02, 0x04, 0x46, 0x7a, 0xda, 0x05, 0x1c, 0xa0, 0x0f, 0x41, 0x54, 0x09,
0xa0, 0x0f, 0x41, 0x54, 0x09, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xa0, 0x0f, 0x41,
0x54, 0x09, 0xb3, 0x7b, 0x01, 0xc0, 0x1f, 0x74, 0x0e, 0x40, 0x54, 0x09, 0xc0,
0x03, 0x9c, 0x00, 0x1c, 0x80, 0x00, 0xf0, 0x02, 0x00, 0x00, 0x00, 0xf0, 0x02,
0x04, 0x00, 0x00, 0xc4, 0x12, 0x05, 0x07, 0x1d, 0x01, 0x00, 0x1c, 0xd4, 0xd3,
0x2b, 0x00, 0x1c, 0xd4, 0xd3, 0x52, 0x00, 0x1c, 0x80, 0x76, 0x95, 0x13, 0x04,
0x00, 0x00, 0xf8, 0x02, 0x00, 0xa6, 0x7b, 0xa9, 0x03, 0x10, 0xc7, 0x9c, 0x00,
0x00, 0x1c, 0x80, 0x2c, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x78, 0x02, 0x04, 0x00,
0x00, 0x6c, 0xc3, 0x04, 0xab, 0x2d, 0xf1, 0x12, 0x05, 0x07, 0x1d, 0xcd, 0xc2,
0x04, 0x8b, 0x2d, 0x01, 0x00, 0x1c, 0x69, 0x25, 0x01, 0x00, 0x1c, 0xa6, 0x7b,
0xa9, 0x03, 0x10, 0xcb, 0x2f, 0x09, 0x00, 0x1c, 0x60, 0x2c, 0x00, 0x00, 0x1c,
0x00, 0x00, 0x60, 0x03, 0x00, 0x53, 0x0f, 0x42, 0x54, 0x09, 0x46, 0x7a, 0xda,
0x05, 0x1c, 0x7a, 0x0e, 0x42, 0x54, 0x09, 0x40, 0xfa, 0x15, 0x00, 0x1c, 0x00,
0x00, 0x28, 0x03, 0x04, 0x46, 0x7a, 0xda, 0x05, 0x1c, 0xb5, 0x0f, 0x41, 0x54,
0x09, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0x73, 0xec, 0x42, 0x03, 0x04, 0x60, 0x2c,
0x00, 0x00, 0x1c, 0x00, 0x00, 0x40, 0x03, 0x00, 0xc7, 0x1c, 0x01, 0x00, 0x1c,
0x00, 0x00, 0x40, 0x13, 0x05, 0x07, 0x1d, 0x01, 0x00, 0x1c, 0xc0, 0xd7, 0x22,
0x00, 0x1c, 0x75, 0x56, 0x96, 0x13, 0x04, 0x60, 0x2c, 0x00, 0x00, 0x1c, 0xe7,
0x1c, 0x5d, 0x03, 0x04, 0xe7, 0x9c, 0x00, 0x00, 0x1c, 0xa6, 0x7b, 0xa9, 0x03,
0x10, 0x80, 0x2c, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x10, 0x03, 0x04, 0x00, 0x00,
0x6c, 0xc3, 0x04, 0xb9, 0x7b, 0x01, 0x00, 0x1c, 0x00, 0x00, 0xa0, 0xc3, 0x04,
0xcb, 0xaf, 0xfc, 0x07, 0x1c, 0xcb, 0x2f, 0x01, 0x04, 0x1c, 0xc7, 0x9f, 0x80,
0x03, 0x1c, 0x00, 0x00, 0xa0, 0xc3, 0x04, 0xcb, 0xaf, 0xfc, 0x07, 0x1c, 0xcb,
0x2f, 0x0d, 0x04, 0x1c, 0xc7, 0x9f, 0x80, 0x03, 0x1c, 0x00, 0x00, 0xa0, 0xc3,
0x04, 0xcb, 0xaf, 0x00, 0xf8, 0x1d, 0xcb, 0x2f, 0x01, 0x00, 0x1d, 0x00, 0x00,
0xa0, 0xc3, 0x04, 0x00, 0x00, 0xa0, 0x13, 0x05, 0x07, 0x1d, 0x01, 0x00, 0x1c,
0xc0, 0x1d, 0xf0, 0xd3, 0x08, 0x27, 0x9d, 0xf8, 0x03, 0x00, 0xa0, 0xee, 0x56,
0xd4, 0x00, 0xfb, 0x75, 0x19, 0x14, 0x04, 0x20, 0x7b, 0x06, 0x00, 0x1c, 0xc0,
0x1c, 0x2c, 0x04, 0x00, 0x00, 0x00, 0xc4, 0xd3, 0x08, 0x00, 0x00, 0x10, 0xf4,
0x00, 0xc0, 0xef, 0xf2, 0x00, 0x1c, 0x20, 0x25, 0x6c, 0x14, 0x04, 0x60, 0xb7,
0xe6, 0x03, 0x00, 0x00, 0x00, 0x1c, 0x15, 0x00, 0xcc, 0xb3, 0xfc, 0x03, 0x1c,
0xcc, 0x33, 0x05, 0x02, 0x1c, 0x00, 0x00, 0x1c, 0xc5, 0x04, 0x60, 0xb7, 0x1e,
0x05, 0x04, 0x00, 0x00, 0x1c, 0x15, 0x04, 0x00, 0x00, 0x6c, 0xc4, 0x04, 0xc0,
0x1d, 0xac, 0xf3, 0x04, 0x00, 0x00, 0x78, 0xc4, 0x04, 0x07, 0x9d, 0x00, 0x00,
0x1c, 0x1b, 0x74, 0x0d, 0xf4, 0x04, 0xa0, 0x0f, 0x41, 0x54, 0x09, 0xe0, 0x7b,
0x00, 0xfc, 0x1f, 0x39, 0x7f, 0x02, 0x00, 0x1c, 0x07, 0x1d, 0xb1, 0xc3, 0x04,
0xa6, 0x7b, 0xc1, 0x03, 0x1c, 0x00, 0x00, 0x78, 0xc4, 0x04, 0xe0, 0x1c, 0x00,
0x00, 0x1c, 0x00, 0x00, 0xb8, 0x03, 0x04, 0xcb, 0xaf, 0x00, 0xf8, 0x1d, 0xcb,
0x2f, 0x01, 0x10, 0x1d, 0x00, 0x00, 0xc0, 0xc3, 0x04, 0x00, 0x00, 0xc0, 0x03,
0x04, 0xcb, 0xaf, 0x00, 0xf8, 0x1d, 0xcb, 0x2f, 0x01, 0x18, 0x1d, 0xc7, 0x9f,
0x00, 0x0b, 0x1c, 0x00, 0x00, 0xc0, 0xc3, 0x04, 0xfb, 0x75, 0x01, 0x00, 0x1c,
0x07, 0x1d, 0x01, 0x00, 0x1c, 0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x01,
0x02, 0x1c, 0x00, 0x00, 0xc0, 0xc3, 0x04, 0xa0, 0x1c, 0x00, 0x00, 0x1c, 0xa0,
0xee, 0xb6, 0x03, 0x04, 0xcb, 0xaf, 0xfc, 0x07, 0x1c, 0xcb, 0x2f, 0x09, 0x04,
0x1c, 0xfb, 0x75, 0x01, 0x00, 0x1c, 0x00, 0x00, 0xc0, 0xc3, 0x04, 0xcc, 0xb3,
0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x01, 0x02, 0x1c, 0x00, 0x00, 0x1c, 0xc5, 0x04,
0x00, 0x00, 0x88, 0x34, 0x05, 0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x15,
0x02, 0x1c, 0x47, 0x9d, 0x64, 0xc4, 0x04, 0x00, 0x00, 0x88, 0x44, 0x00, 0x80,
0x1d, 0x8c, 0x54, 0x04, 0x87, 0x1d, 0x9d, 0x04, 0x00, 0xce, 0x76, 0x01, 0x00,
0x1c, 0xef, 0x76, 0xad, 0xc4, 0x04, 0xa4, 0x77, 0x9d, 0x24, 0x09, 0xe4, 0x76,
0x01, 0x00, 0x1c, 0xc4, 0x76, 0x01, 0x00, 0x1c, 0x00, 0x00, 0xa8, 0x54, 0x04,
0xd7, 0x76, 0x01, 0x50, 0x18, 0xf6, 0x76, 0x01, 0x00, 0x1c, 0x00, 0x00, 0x00,
0x30, 0x18, 0x00, 0x00, 0x00, 0x00, 0x10, 0xcc, 0x30, 0x51, 0xc5, 0x04, 0xeb,
0x2d, 0x01, 0x00, 0x1c, 0xea, 0x29, 0x01, 0x00, 0x1c, 0xc0, 0x59, 0x01, 0x00,
0x1c, 0xf5, 0x77, 0x39, 0xc5, 0x04, 0xe0, 0x30, 0xec, 0x04, 0x00, 0x00, 0x4c,
0xc0, 0x04, 0x00, 0x20, 0x4c, 0x04, 0x05, 0x00, 0x00, 0x00, 0xf8, 0x04, 0x00,
0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x09, 0x02, 0x1c, 0xeb, 0x2d, 0xc5,
0xc4, 0x04, 0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x19, 0x02, 0x1c, 0xeb,
0x2d, 0xc5, 0xc4, 0x04, 0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33, 0x0d, 0x02,
0x1c, 0xeb, 0x2d, 0xc5, 0xc4, 0x04, 0xcc, 0xb3, 0xfc, 0x03, 0x1c, 0xcc, 0x33,
0x11, 0x02, 0x1c, 0xeb, 0x2d, 0xc5, 0xc4, 0x04, 0x00, 0x7b, 0x00, 0x80, 0x1c,
0xae, 0x77, 0x51, 0x05, 0x00, 0x00, 0x00, 0x04, 0xc0, 0x04, 0xd3, 0x8b, 0x00,
0xfc, 0x1f, 0x60, 0x7a, 0x3c, 0x00, 0x1c, 0x60, 0x4c, 0xd0, 0x04, 0x00, 0xc0,
0x2f, 0x20, 0x05, 0x1f, 0xe0, 0x30, 0xc0, 0x04, 0x00, 0x80, 0x25, 0xc0, 0x04,
0x00, 0xb5, 0x5b, 0xc1, 0x04, 0x04, 0x69, 0x26, 0x01, 0x00, 0x1c, 0x6a, 0x2b,
0x01, 0x00, 0x1c, 0x80, 0x1d, 0x00, 0x00, 0x1c, 0xa9, 0x25, 0x51, 0x05, 0x00,
0xee, 0x30, 0x00, 0x00, 0x1c, 0xaf, 0x77, 0x11, 0x05, 0x00, 0xb4, 0x5f, 0x01,
0x40, 0x18, 0x07, 0x9d, 0x54, 0x55, 0x04, 0xb7, 0x76, 0x01, 0x00, 0x1c, 0x96,
0x76, 0x01, 0x00, 0x1c, 0x47, 0x1d, 0x01, 0x00, 0x1c, 0xa4, 0x33, 0x01, 0x60,
0x18, 0xa4, 0x2f, 0x01, 0x60, 0x18, 0x64, 0x77, 0x01, 0x60, 0x18, 0x24, 0x77,
0x01, 0x60, 0x18, 0x44, 0x77, 0x01, 0x00, 0x1c, 0x64, 0x88, 0x03, 0x00, 0x1c,
0xa4, 0x3f, 0x01, 0x00, 0x1c, 0xa4, 0x3b, 0x01, 0x00, 0x1c, 0x53, 0x77, 0x01,
0x00, 0x1c, 0xd3, 0xcf, 0x3b, 0x00, 0x1c, 0x53, 0x4f, 0x02, 0x00, 0x1c, 0xd3,
0xcf, 0x00, 0x00, 0x1f, 0xda, 0xcf, 0x0b, 0x00, 0x1c, 0xd5, 0x57, 0x0f, 0x00,
0x1c, 0xd3, 0xd3, 0x37, 0x00, 0x1c, 0xd4, 0x53, 0x0f, 0x00, 0x1c, 0xe0, 0x29,
0x00, 0x00, 0x1c, 0xf5, 0xd5, 0xc0, 0x05, 0x00, 0x00, 0x00, 0xac, 0x55, 0x04,
0x77, 0x56, 0x01, 0x00, 0x1c, 0x56, 0x53, 0x01, 0x00, 0x1c, 0x00, 0x00, 0x00,
0x10, 0x18, 0x00, 0x00, 0x04, 0xc0, 0x04, 0xf5, 0x55, 0x01, 0x00, 0x1c, 0x00,
0x00, 0xc4, 0x55, 0x04, 0x77, 0x56, 0x01, 0x00, 0x1c, 0x56, 0x53, 0x01, 0x00,
0x1c, 0x00, 0x00, 0x00, 0x10, 0x18, 0x00, 0x00, 0x04, 0xc0, 0x04, 0xcb, 0x2f,
0x01, 0x18, 0x10, 0xcb, 0x2f, 0x01, 0x10, 0x10, 0xcb, 0x2f, 0x01, 0x08, 0x10,
0xcb, 0x2f, 0x01, 0x08, 0x10, 0xcb, 0x2f, 0x01, 0x20, 0x10, 0xcb, 0x2f, 0x01,
0x00, 0x10, 0xcb, 0x2f, 0x01, 0x28, 0x10, 0x89, 0x25, 0x6d, 0xc2, 0x04, 0x00,
0x00, 0x04, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc3,
0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc2, 0x04, 0x00, 0x00,
0x04, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04,
0x00, 0x00, 0x6c, 0xc3, 0x04, 0x40, 0x1c, 0x68, 0xc0, 0x04, 0x40, 0x1c, 0x98,
0xc0, 0x04, 0xa7, 0x77, 0x6d, 0xc3, 0x04, 0x00, 0x00, 0xc0, 0xc0, 0x04, 0x27,
0x1d, 0xed, 0xc0, 0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x00, 0x00, 0x6c, 0xc3,
0x04, 0x00, 0x00, 0x6c, 0xc3, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00,
0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6,
0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00,
0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c,
0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04, 0x00, 0x00, 0x3c, 0xc6, 0x04,
};

6850
drivers/staging/slicoss/oasisdbgdownload.h Normal file
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File diff suppressed because it is too large Load diff

6848
drivers/staging/slicoss/oasisdownload.h Normal file
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File diff suppressed because it is too large Load diff

205
drivers/staging/slicoss/oasisrcvucode.h Normal file
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@ -0,0 +1,205 @@
#define OASIS_RCVUCODE_VERS_STRING "1.2"
#define OASIS_RCVUCODE_VERS_DATE "2006/03/27 15:10:28"
static u32 OasisRcvUCodeLen = 512;
static u8 OasisRcvUCode[2560] =
{
0x47, 0x75, 0x01, 0x00, 0x04, 0xa0, 0x13, 0x01, 0x00, 0x1c, 0xb7, 0x5b, 0x09,
0x30, 0x00, 0xb6, 0x5f, 0x01, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x20, 0x18, 0x3b,
0x78, 0x3a, 0x00, 0x1c, 0xa2, 0x77, 0x01, 0x00, 0x1c, 0x07, 0x1d, 0x01, 0x70,
0x18, 0xad, 0x7b, 0xf1, 0xff, 0x1c, 0xb3, 0x7b, 0xa9, 0xaa, 0x1e, 0xb4, 0x7b,
0x01, 0x0c, 0x1c, 0xb5, 0x7b, 0x0d, 0x06, 0x1c, 0x00, 0x00, 0x30, 0x64, 0x08,
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};

598
drivers/staging/slicoss/slic.h Normal file
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@ -0,0 +1,598 @@
/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slic.h
*
* This is the base set of header definitions for the SLICOSS driver.
*/
#ifndef __SLIC_DRIVER_H__
#define __SLIC_DRIVER_H__
struct slic_spinlock {
spinlock_t lock;
unsigned long flags;
};
#define SLIC_RSPQ_PAGES_GB 10
#define SLIC_RSPQ_BUFSINPAGE (PAGE_SIZE / SLIC_RSPBUF_SIZE)
struct slic_rspqueue {
u32 offset;
u32 pageindex;
u32 num_pages;
struct slic_rspbuf *rspbuf;
u32 *vaddr[SLIC_RSPQ_PAGES_GB];
dma_addr_t paddr[SLIC_RSPQ_PAGES_GB];
};
#define SLIC_RCVQ_EXPANSION 1
#define SLIC_RCVQ_ENTRIES (256 * SLIC_RCVQ_EXPANSION)
#define SLIC_RCVQ_MINENTRIES (SLIC_RCVQ_ENTRIES / 2)
#define SLIC_RCVQ_MAX_PROCESS_ISR ((SLIC_RCVQ_ENTRIES * 4))
#define SLIC_RCVQ_RCVBUFSIZE 2048
#define SLIC_RCVQ_FILLENTRIES (16 * SLIC_RCVQ_EXPANSION)
#define SLIC_RCVQ_FILLTHRESH (SLIC_RCVQ_ENTRIES - SLIC_RCVQ_FILLENTRIES)
struct slic_rcvqueue {
struct sk_buff *head;
struct sk_buff *tail;
u32 count;
u32 size;
u32 errors;
};
struct slic_rcvbuf_info {
u32 id;
u32 starttime;
u32 stoptime;
u32 slicworld;
u32 lasttime;
u32 lastid;
};
/*
SLIC Handle structure. Used to restrict handle values to
32 bits by using an index rather than an address.
Simplifies ucode in 64-bit systems
*/
struct slic_handle_word {
union {
struct {
ushort index;
ushort bottombits; /* to denote num bufs to card */
} parts;
u32 whole;
} handle;
};
struct slic_handle {
struct slic_handle_word token; /* token passed between host and card*/
ushort type;
void *address; /* actual address of the object*/
ushort offset;
struct slic_handle *other_handle;
struct slic_handle *next;
};
#define SLIC_HANDLE_FREE 0x0000
#define SLIC_HANDLE_DATA 0x0001
#define SLIC_HANDLE_CMD 0x0002
#define SLIC_HANDLE_CONTEXT 0x0003
#define SLIC_HANDLE_TEAM 0x0004
#define handle_index handle.parts.index
#define handle_bottom handle.parts.bottombits
#define handle_token handle.whole
#define SLIC_HOSTCMD_SIZE 512
struct slic_hostcmd {
struct slic_host64_cmd cmd64;
u32 type;
struct sk_buff *skb;
u32 paddrl;
u32 paddrh;
u32 busy;
u32 cmdsize;
ushort numbufs;
struct slic_handle *pslic_handle;/* handle associated with command */
struct slic_hostcmd *next;
struct slic_hostcmd *next_all;
};
#define SLIC_CMDQ_CMDSINPAGE (PAGE_SIZE / SLIC_HOSTCMD_SIZE)
#define SLIC_CMD_DUMB 3
#define SLIC_CMDQ_INITCMDS 256
#define SLIC_CMDQ_MAXCMDS 256
#define SLIC_CMDQ_MAXOUTSTAND SLIC_CMDQ_MAXCMDS
#define SLIC_CMDQ_MAXPAGES (SLIC_CMDQ_MAXCMDS / SLIC_CMDQ_CMDSINPAGE)
#define SLIC_CMDQ_INITPAGES (SLIC_CMDQ_INITCMDS / SLIC_CMDQ_CMDSINPAGE)
struct slic_cmdqmem {
int pagecnt;
u32 *pages[SLIC_CMDQ_MAXPAGES];
dma_addr_t dma_pages[SLIC_CMDQ_MAXPAGES];
};
struct slic_cmdqueue {
struct slic_hostcmd *head;
struct slic_hostcmd *tail;
int count;
struct slic_spinlock lock;
};
#ifdef STATUS_SUCCESS
#undef STATUS_SUCCESS
#endif
#define STATUS_SUCCESS 0
#define STATUS_PENDING 0
#define STATUS_FAILURE -1
#define STATUS_ERROR -2
#define STATUS_NOT_SUPPORTED -3
#define STATUS_BUFFER_TOO_SHORT -4
#define SLIC_MAX_CARDS 32
#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
#if SLIC_DUMP_ENABLED
/*
Dump buffer size
This cannot be bigger than the max DMA size the card supports,
given the current code structure in the host and ucode.
Mojave supports 16K, Oasis supports 16K-1, so
just set this at 15K, shouldnt make that much of a diff.
*/
#define DUMP_BUF_SIZE 0x3C00
#endif
struct mcast_address {
unsigned char address[6];
struct mcast_address *next;
};
#define CARD_DOWN 0x00000000
#define CARD_UP 0x00000001
#define CARD_FAIL 0x00000002
#define CARD_DIAG 0x00000003
#define CARD_SLEEP 0x00000004
#define ADAPT_DOWN 0x00
#define ADAPT_UP 0x01
#define ADAPT_FAIL 0x02
#define ADAPT_RESET 0x03
#define ADAPT_SLEEP 0x04
#define ADAPT_FLAGS_BOOTTIME 0x0001
#define ADAPT_FLAGS_IS64BIT 0x0002
#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
#define ADAPT_FLAGS_FIBERMEDIA 0x0008
#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
#define ADAPT_FLAGS_INT_REGISTERED 0x0020
#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
#define LINK_DOWN 0x00
#define LINK_CONFIG 0x01
#define LINK_UP 0x02
#define LINK_10MB 0x00
#define LINK_100MB 0x01
#define LINK_AUTOSPEED 0x02
#define LINK_1000MB 0x03
#define LINK_10000MB 0x04
#define LINK_HALFD 0x00
#define LINK_FULLD 0x01
#define LINK_AUTOD 0x02
#define MAC_DIRECTED 0x00000001
#define MAC_BCAST 0x00000002
#define MAC_MCAST 0x00000004
#define MAC_PROMISC 0x00000008
#define MAC_LOOPBACK 0x00000010
#define MAC_ALLMCAST 0x00000020
#define SLIC_DUPLEX(x) ((x == LINK_FULLD) ? "FDX" : "HDX")
#define SLIC_SPEED(x) ((x == LINK_100MB) ? "100Mb" : ((x == LINK_1000MB) ?\
"1000Mb" : " 10Mb"))
#define SLIC_LINKSTATE(x) ((x == LINK_DOWN) ? "Down" : "Up ")
#define SLIC_ADAPTER_STATE(x) ((x == ADAPT_UP) ? "UP" : "Down")
#define SLIC_CARD_STATE(x) ((x == CARD_UP) ? "UP" : "Down")
struct slic_iface_stats {
/*
* Stats
*/
u64 xmt_bytes;
u64 xmt_ucast;
u64 xmt_mcast;
u64 xmt_bcast;
u64 xmt_errors;
u64 xmt_discards;
u64 xmit_collisions;
u64 xmit_excess_xmit_collisions;
u64 rcv_bytes;
u64 rcv_ucast;
u64 rcv_mcast;
u64 rcv_bcast;
u64 rcv_errors;
u64 rcv_discards;
};
struct sliccp_stats {
u64 xmit_tcp_segs;
u64 xmit_tcp_bytes;
u64 rcv_tcp_segs;
u64 rcv_tcp_bytes;
};
struct slicnet_stats {
struct sliccp_stats tcp;
struct slic_iface_stats iface;
};
#define SLIC_LOADTIMER_PERIOD 1
#define SLIC_INTAGG_DEFAULT 200
#define SLIC_LOAD_0 0
#define SLIC_INTAGG_0 0
#define SLIC_LOAD_1 8000
#define SLIC_LOAD_2 10000
#define SLIC_LOAD_3 12000
#define SLIC_LOAD_4 14000
#define SLIC_LOAD_5 16000
#define SLIC_INTAGG_1 50
#define SLIC_INTAGG_2 100
#define SLIC_INTAGG_3 150
#define SLIC_INTAGG_4 200
#define SLIC_INTAGG_5 250
#define SLIC_LOAD_1GB 3000
#define SLIC_LOAD_2GB 6000
#define SLIC_LOAD_3GB 12000
#define SLIC_LOAD_4GB 24000
#define SLIC_LOAD_5GB 48000
#define SLIC_INTAGG_1GB 50
#define SLIC_INTAGG_2GB 75
#define SLIC_INTAGG_3GB 100
#define SLIC_INTAGG_4GB 100
#define SLIC_INTAGG_5GB 100
struct ether_header {
unsigned char ether_dhost[6];
unsigned char ether_shost[6];
ushort ether_type;
};
struct sliccard {
uint busnumber;
uint slotnumber;
uint state;
uint cardnum;
uint card_size;
uint adapters_activated;
uint adapters_allocated;
uint adapters_sleeping;
uint gennumber;
u32 events;
u32 loadlevel_current;
u32 load;
uint reset_in_progress;
u32 pingstatus;
u32 bad_pingstatus;
struct timer_list loadtimer;
u32 loadtimerset;
uint config_set;
struct slic_config config;
struct dentry *debugfs_dir;
struct dentry *debugfs_cardinfo;
struct adapter *master;
struct adapter *adapter[SLIC_MAX_PORTS];
struct sliccard *next;
u32 error_interrupts;
u32 error_rmiss_interrupts;
u32 rcv_interrupts;
u32 xmit_interrupts;
u32 num_isrs;
u32 false_interrupts;
u32 max_isr_rcvs;
u32 max_isr_xmits;
u32 rcv_interrupt_yields;
u32 tx_packets;
#if SLIC_DUMP_ENABLED
u32 dumpstatus; /* Result of dump UPR */
void *cmdbuffer;
ulong cmdbuffer_phys;
u32 cmdbuffer_physl;
u32 cmdbuffer_physh;
u32 dump_count;
struct task_struct *dump_task_id;
u32 dump_wait_count;
uint dumpthread_running; /* has a dump thread been init'd */
uint dump_requested; /* 0 no, 1 = reqstd 2=curr 3=done */
u32 dumptime_start;
u32 dumptime_complete;
u32 dumptime_delta;
void *dumpbuffer;
ulong dumpbuffer_phys;
u32 dumpbuffer_physl;
u32 dumpbuffer_physh;
wait_queue_head_t dump_wq;
struct file *dumphandle;
mm_segment_t dumpfile_fs;
#endif
u32 debug_ix;
ushort reg_type[32];
ushort reg_offset[32];
u32 reg_value[32];
u32 reg_valueh[32];
};
#define NUM_CFG_SPACES 2
#define NUM_CFG_REGS 64
#define NUM_CFG_REG_ULONGS (NUM_CFG_REGS / sizeof(u32))
struct physcard {
struct adapter *adapter[SLIC_MAX_PORTS];
struct physcard *next;
uint adapters_allocd;
/* the following is not currently needed
u32 bridge_busnum;
u32 bridge_cfg[NUM_CFG_SPACES][NUM_CFG_REG_ULONGS];
*/
};
struct base_driver {
struct slic_spinlock driver_lock;
u32 num_slic_cards;
u32 num_slic_ports;
u32 num_slic_ports_active;
u32 dynamic_intagg;
struct sliccard *slic_card;
struct physcard *phys_card;
uint cardnuminuse[SLIC_MAX_CARDS];
};
struct slic_shmem {
volatile u32 isr;
volatile u32 linkstatus;
volatile struct slic_stats inicstats;
};
struct slic_reg_params {
u32 linkspeed;
u32 linkduplex;
u32 fail_on_bad_eeprom;
};
struct slic_upr {
uint adapter;
u32 upr_request;
u32 upr_data;
u32 upr_data_h;
u32 upr_buffer;
u32 upr_buffer_h;
struct slic_upr *next;
};
struct slic_ifevents {
uint oflow802;
uint uflow802;
uint Tprtoflow;
uint rcvearly;
uint Bufov;
uint Carre;
uint Longe;
uint Invp;
uint Crc;
uint Drbl;
uint Code;
uint IpHlen;
uint IpLen;
uint IpCsum;
uint TpCsum;
uint TpHlen;
};
struct adapter {
void *ifp;
struct sliccard *card;
uint port;
struct physcard *physcard;
uint physport;
uint cardindex;
uint card_size;
uint chipid;
struct net_device *netdev;
struct net_device *next_netdevice;
struct slic_spinlock adapter_lock;
struct slic_spinlock reset_lock;
struct pci_dev *pcidev;
uint busnumber;
uint slotnumber;
uint functionnumber;
ushort vendid;
ushort devid;
ushort subsysid;
u32 irq;
void __iomem *memorybase;
u32 memorylength;
u32 drambase;
u32 dramlength;
uint queues_initialized;
uint allocated;
uint activated;
u32 intrregistered;
uint isp_initialized;
uint gennumber;
u32 curaddrupper;
struct slic_shmem *pshmem;
dma_addr_t phys_shmem;
u32 isrcopy;
__iomem struct slic_regs *slic_regs;
unsigned char state;
unsigned char linkstate;
unsigned char linkspeed;
unsigned char linkduplex;
uint flags;
unsigned char macaddr[6];
unsigned char currmacaddr[6];
u32 macopts;
ushort devflags_prev;
u64 mcastmask;
struct mcast_address *mcastaddrs;
struct slic_upr *upr_list;
uint upr_busy;
struct timer_list pingtimer;
u32 pingtimerset;
struct timer_list statstimer;
u32 statstimerset;
struct timer_list loadtimer;
u32 loadtimerset;
struct dentry *debugfs_entry;
struct slic_spinlock upr_lock;
struct slic_spinlock bit64reglock;
struct slic_rspqueue rspqueue;
struct slic_rcvqueue rcvqueue;
struct slic_cmdqueue cmdq_free;
struct slic_cmdqueue cmdq_done;
struct slic_cmdqueue cmdq_all;
struct slic_cmdqmem cmdqmem;
/*
* SLIC Handles
*/
struct slic_handle slic_handles[SLIC_CMDQ_MAXCMDS+1]; /* Object handles*/
struct slic_handle *pfree_slic_handles; /* Free object handles*/
struct slic_spinlock handle_lock; /* Object handle list lock*/
ushort slic_handle_ix;
u32 xmitq_full;
u32 all_reg_writes;
u32 icr_reg_writes;
u32 isr_reg_writes;
u32 error_interrupts;
u32 error_rmiss_interrupts;
u32 rx_errors;
u32 rcv_drops;
u32 rcv_interrupts;
u32 xmit_interrupts;
u32 linkevent_interrupts;
u32 upr_interrupts;
u32 num_isrs;
u32 false_interrupts;
u32 tx_packets;
u32 xmit_completes;
u32 tx_drops;
u32 rcv_broadcasts;
u32 rcv_multicasts;
u32 rcv_unicasts;
u32 max_isr_rcvs;
u32 max_isr_xmits;
u32 rcv_interrupt_yields;
u32 intagg_period;
struct inicpm_state *inicpm_info;
void *pinicpm_info;
struct slic_reg_params reg_params;
struct slic_ifevents if_events;
struct slic_stats inicstats_prev;
struct slicnet_stats slic_stats;
struct net_device_stats stats;
};
#if SLIC_DUMP_ENABLED
#define SLIC_DUMP_REQUESTED 1
#define SLIC_DUMP_IN_PROGRESS 2
#define SLIC_DUMP_DONE 3
/****************************************************************************
*
* Microcode crash information structure. This
* structure is written out to the card's SRAM when the microcode panic's.
*
****************************************************************************/
struct slic_crash_info {
ushort cpu_id;
ushort crash_pc;
};
#define CRASH_INFO_OFFSET 0x155C
#endif
#define UPDATE_STATS(largestat, newstat, oldstat) \
{ \
if ((newstat) < (oldstat)) \
(largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
else \
(largestat) += ((newstat) - (oldstat)); \
}
#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
{ \
(largestat) += ((newstat) - (oldstat)); \
}
#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
{ \
_Result = TRUE; \
if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
_Result = FALSE; \
if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
_Result = FALSE; \
}
#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
#define SLIC_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & \
0x00000000FFFFFFFF)
#define SLIC_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & \
0x00000000FFFFFFFF)
#else
#define SLIC_GET_ADDR_LOW(_addr) (u32)_addr
#define SLIC_GET_ADDR_HIGH(_addr) (u32)0
#endif
#define FLUSH TRUE
#define DONT_FLUSH FALSE
#define SIOCSLICDUMPCARD (SIOCDEVPRIVATE+9)
#define SIOCSLICSETINTAGG (SIOCDEVPRIVATE+10)
#define SIOCSLICTRACEDUMP (SIOCDEVPRIVATE+11)
#endif /* __SLIC_DRIVER_H__ */

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/**************************************************************************
*
* Copyright (c)2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slic_os.h
*
* These are the Linux-specific definitions required for the SLICOSS
* driver, which should allow for greater portability to other OSes.
*/
#ifndef _SLIC_OS_SPECIFIC_H_
#define _SLIC_OS_SPECIFIC_H_
#define FALSE (0)
#define TRUE (1)
#define SLIC_SECS_TO_JIFFS(x) ((x) * HZ)
#define SLIC_MS_TO_JIFFIES(x) (SLIC_SECS_TO_JIFFS((x)) / 1000)
#ifdef DEBUG_REGISTER_TRACE
#define WRITE_REG(reg, value, flush) \
{ \
adapter->card->reg_type[adapter->card->debug_ix] = 0; \
adapter->card->reg_offset[adapter->card->debug_ix] = \
((unsigned char *)(&reg)) - \
((unsigned char *)adapter->slic_regs); \
adapter->card->reg_value[adapter->card->debug_ix++] = value; \
if (adapter->card->debug_ix == 32) \
adapter->card->debug_ix = 0; \
slic_reg32_write((&reg), (value), (flush)); \
}
#define WRITE_REG64(a, reg, value, regh, valh, flush) \
{ \
adapter->card->reg_type[adapter->card->debug_ix] = 1; \
adapter->card->reg_offset[adapter->card->debug_ix] = \
((unsigned char *)(&reg)) - \
((unsigned char *)adapter->slic_regs); \
adapter->card->reg_value[adapter->card->debug_ix] = value; \
adapter->card->reg_valueh[adapter->card->debug_ix++] = valh; \
if (adapter->card->debug_ix == 32) \
adapter->card->debug_ix = 0; \
slic_reg64_write((a), (&reg), (value), (&regh), (valh), \
(flush));\
}
#else
#define WRITE_REG(reg, value, flush) \
slic_reg32_write((&reg), (value), (flush))
#define WRITE_REG64(a, reg, value, regh, valh, flush) \
slic_reg64_write((a), (&reg), (value), (&regh), (valh), (flush))
#endif
#endif /* _SLIC_OS_SPECIFIC_H_ */

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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slicbuild.h
*
* The following contains the compiler directive switches used for
* different SLIC build options. They can all be set in the Makefile
* but the defaults are defined here.
*/
#ifndef _SLIC_BUILD_H_
#define _SLIC_BUILD_H_
#ifndef SLIC_PRODUCTION_BUILD
#define SLIC_PRODUCTION_BUILD 1
#endif
#ifndef SLIC_FAILURE_RESET
#define SLIC_FAILURE_RESET 1
#endif
#define DBG 1
#ifndef SLIC_ASSERT_ENABLED
#define SLIC_ASSERT_ENABLED 1
#endif
#ifndef SLIC_MCAST_ENABLED
#define SLIC_MCAST_ENABLED 1
#endif
#ifndef SLIC_GET_STATS_ENABLED
#define SLIC_GET_STATS_ENABLED 1
#endif
#ifndef SLIC_GET_STATS_TIMER_ENABLED
#define SLIC_GET_STATS_TIMER_ENABLED 0
#endif
#ifndef SLIC_PING_TIMER_ENABLED
#define SLIC_PING_TIMER_ENABLED 1
#endif
#ifndef SLIC_IOCTL_SUPPORT_ENABLED
#define SLIC_IOCTL_SUPPORT_ENABLED 1
#endif
#ifndef ATK_DEBUG
#define ATK_DEBUG 1
#endif
#ifndef SLIC_POWER_MANAGEMENT_ENABLED
#define SLIC_POWER_MANAGEMENT_ENABLED 0
#endif
#ifndef SLIC_INTERRUPT_PROCESS_LIMIT
#define SLIC_INTERRUPT_PROCESS_LIMIT 1
#endif
#ifndef LINUX_FREES_ADAPTER_RESOURCES
#define LINUX_FREES_ADAPTER_RESOURCES 1
#endif
#ifndef SLIC_OFFLOAD_IP_CHECKSUM
#define SLIC_OFFLOAD_IP_CHECKSUM 1
#endif
#ifndef SLIC_POWER_MANAGEMENT_ENABLED
#define SLIC_POWER_MANAGEMENT_ENABLED 0
#endif
#ifndef STATS_TIMER_INTERVAL
#define STATS_TIMER_INTERVAL 2
#endif
#ifndef PING_TIMER_INTERVAL
#define PING_TIMER_INTERVAL 1
#endif
#endif /* _SLIC_BUILD_H_ */

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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slicdbg.h
*
* All debug and assertion-based definitions and macros are included
* in this file for the SLICOSS driver.
*/
#ifndef _SLIC_DEBUG_H_
#define _SLIC_DEBUG_H_
#ifdef SLIC_DEFAULT_LOG_LEVEL
#else
#define SLICLEVEL KERN_DEBUG
#endif
#define SLIC_DISPLAY printk
#define DBG_ERROR(n, args...) SLIC_DISPLAY(KERN_EMERG n, ##args)
#define SLIC_DEBUG_MESSAGE 1
#if SLIC_DEBUG_MESSAGE
/*#define DBG_MSG(n, args...) SLIC_DISPLAY(SLICLEVEL n, ##args)*/
#define DBG_MSG(n, args...)
#else
#define DBG_MSG(n, args...)
#endif
#ifdef ASSERT
#undef ASSERT
#endif
#if SLIC_ASSERT_ENABLED
#ifdef CONFIG_X86_64
#define VALID_ADDRESS(p) (1)
#else
#define VALID_ADDRESS(p) (((u32)(p) & 0x80000000) || ((u32)(p) == 0))
#endif
#ifndef ASSERT
#define ASSERT(a) \
{ \
if (!(a)) { \
DBG_ERROR("ASSERT() Failure: file %s, function %s line %d\n",\
__FILE__, __func__, __LINE__); \
slic_assert_fail(); \
} \
}
#endif
#ifndef ASSERTMSG
#define ASSERTMSG(a,msg) \
{ \
if (!(a)) { \
DBG_ERROR("ASSERT() Failure: file %s, function %s"\
"line %d: %s\n",\
__FILE__, __func__, __LINE__, (msg)); \
slic_assert_fail(); \
} \
}
#endif
#else
#ifndef ASSERT
#define ASSERT(a)
#endif
#ifndef ASSERTMSG
#define ASSERTMSG(a, msg)
#endif
#endif /* SLIC_ASSERT_ENABLED */
#endif /* _SLIC_DEBUG_H_ */

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/*
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* NO LICENSE TO ANY ALACRITECH PATENT CLAIM IS GRANTED BY ANY COPYRIGHT
* LICENSE TO THIS OR OTHER SOFTWARE. THIS SOFTWARE MAY BE COVERED BY
* ALACRITECH PATENTS INCLUDING BUT NOT LIMITED TO U.S. PATENT NOS. 6,226,680,
* 6,247,060, 6,334,153, 6,389,479, 6,393,487, 6,427,171, 6,427,173
* and 6,434,620.
* THIS SOFTWARE IS NOT SUBJECT TO THE GNU GENERAL PUBLIC LICENSE (GPL).
*
* The views and conclusions contained in the software and
* documentation are those of the authors and should not be
* interpreted as representing official policies, either
* expressed or implied, of Alacritech, Inc.
*/
#ifndef _SLIC_DUMP_H_
#define _SLIC_DUMP_H_
#define DEBUG_SUCCESS 0
/***********************************************************************
*
* Utility processor register locations
*
**********************************************************************/
#define UTILITY_RESET 0x0
#define UTILITY_ISP_ADDR 0x4 /* Interrupt status Pointer */
#define UTILITY_ISR_ADDR 0x8 /* Interrupt status Register */
#define UTILITY_ICR_ADDR 0xc /* Interrupt Control Register */
#define UTILITY_CPR_ADDR 0x10 /* Command Pointer Register */
#define UTILITY_DPR_ADDR 0x14 /* Data Pointer Register */
#define UTILITY_DMP_TRQ 0x18 /* Dump queue onto ALU for analyser */
#define UTILITY_UPP_ADDR 0x1c /* Bits 63-32 of cmd/data pointer */
/***********************************************************************
*
* INIC status register bits
*
***********************************************************************/
#define SLIC_ISR_CC 0x10000000 /* Command complete - synchronous */
#define SLIC_ISR_ERR 0x01000000 /* Command Error - synchronous */
#define SLIC_ISR_CMD_MASK 0x11000000 /* Command status mask */
#define SLIC_ISR_TPH 0x00080000 /* Transmit processor halted - async */
#define SLIC_ISR_RPH 0x00040000 /* Receive processor halted - async */
/***********************************************************************
*
* INIC Control register values
*
***********************************************************************/
#define SLIC_ICR_OFF 0 /* Interrupts disabled */
#define SLIC_ICR_ON 1 /* Interrupts enabled */
#define SLIC_ICR_MASK 2 /* Interrupts masked */
#define WRITE_DREG(reg, value, flush) \
{ \
writel((value), (reg)); \
if ((flush)) { \
mb(); \
} \
}
/************************************************************************
*
* Command Format
*
* Each command contains a command byte which is defined as follows:
*
* bits: 7-3 2 1-0
* ----------------------------------------------
* command Alt. Proc Processor
*
************************************************************************/
/*
* Macro to create the command byte given the command, Alt. Proc, and
* Processor values. Note that the macro assumes that the values are
* preshifted. That is, the values for alt. proc are 0 for transmit and
* 4 for receive.
*/
#define COMMAND_BYTE(command, alt_proc, proc) ((command) | (alt_proc) | (proc))
/*
* Command values
*/
#define CMD_HALT 0x0 /* Send a halt to the INIC */
#define CMD_RUN 0x8 /* Start the halted INIC */
#define CMD_STEP 0x10 /* Single step the inic */
#define CMD_BREAK 0x18 /* Set a breakpoint - 8 byte command */
#define CMD_RESET_BREAK 0x20 /* Reset a breakpoint - 8 byte cmd */
#define CMD_DUMP 0x28 /* Dump INIC memory - 8 byte command */
#define CMD_LOAD 0x30 /* Load INIC memory - 8 byte command */
#define CMD_MAP 0x38 /* Map out a ROM instruction - 8 BC */
#define CMD_CAM_OPS 0x38 /* perform ops on specific CAM */
#define CMD_XMT 0x40 /* Transmit frame */
#define CMD_RCV 0x48 /* Receive frame */
/*
* Alt. Proc values
*
* When the proc value is set to the utility processor, the Alt. Proc
* specifies which processor handles the debugging.
*/
#define ALT_PROC_TRANSMIT 0x0
#define ALT_PROC_RECEIVE 0x4
/*
* Proc values
*/
#define PROC_INVALID 0x0
#define PROC_NONE 0x0 /* Gigabit use */
#define PROC_TRANSMIT 0x1
#define PROC_RECEIVE 0x2
#define PROC_UTILITY 0x3
/******************************************************************
*
* 8 byte command structure definitions
*
******************************************************************/
/*
* Break and Reset Break command structure
*/
struct BREAK {
unsigned char command; /* Command word defined above */
unsigned char resvd;
ushort count; /* Number of executions before break */
u32 addr; /* Address of break point */
};
/*
* Dump and Load command structure
*/
struct dump_cmd {
unsigned char cmd; /* Command word defined above */
unsigned char desc; /* Descriptor values - defined below */
ushort count; /* number of 4 byte words to be transferred */
u32 addr; /* start address of dump or load */
};
/*
* Receive or Transmit a frame.
*/
struct RCV_OR_XMT_FRAME {
unsigned char command; /* Command word defined above */
unsigned char MacId; /* Mac ID of interface - transmit only */
ushort count; /* Length of frame in bytes */
u32 pad; /* not used */
};
/*
* Values of desc field in DUMP_OR_LOAD structure
*/
#define DESC_RFILE 0x0 /* Register file */
#define DESC_SRAM 0x1 /* SRAM */
#define DESC_DRAM 0x2 /* DRAM */
#define DESC_QUEUE 0x3 /* queues */
#define DESC_REG 0x4 /* General registers (pc, status, etc) */
#define DESC_SENSE 0x5 /* Sense register */
/* Descriptor field definitions for CMD_DUMP_CAM */
#define DUMP_CAM_A 0
#define DUMP_CAM_B 1 /* unused at present */
#define DUMP_CAM_C 2
#define DUMP_CAM_D 3
#define SEARCH_CAM_A 4
#define SEARCH_CAM_C 5
/*
* Map command to replace a command in ROM with a command in WCS
*/
struct MAP {
unsigned char command; /* Command word defined above */
unsigned char not_used[3];
ushort map_to; /* Instruction address in WCS */
ushort map_out; /* Instruction address in ROM */
};
/*
* Misc definitions
*/
#define SLIC_MAX_QUEUE 32 /* Total # of queues on the INIC (0-31)*/
#define SLIC_4MAX_REG 512 /* Total # of 4-port file-registers */
#define SLIC_1MAX_REG 384 /* Total # of file-registers */
#define SLIC_GBMAX_REG 1024 /* Total # of Gbit file-registers */
#define SLIC_NUM_REG 32 /* non-file-registers = NUM_REG in tm-simba.h */
#define SLIC_GB_CAMA_SZE 32
#define SLIC_GB_CAMB_SZE 16
#define SLIC_GB_CAMAB_SZE 32
#define SLIC_GB_CAMC_SZE 16
#define SLIC_GB_CAMD_SZE 16
#define SLIC_GB_CAMCD_SZE 32
/*
* Coredump header structure
*/
struct CORE_Q {
u32 queueOff; /* Offset of queue */
u32 queuesize; /* size of queue */
};
#define DRIVER_NAME_SIZE 32
struct sliccore_hdr {
unsigned char driver_version[DRIVER_NAME_SIZE]; /* Driver version string */
u32 RcvRegOff; /* Offset of receive registers */
u32 RcvRegsize; /* size of receive registers */
u32 XmtRegOff; /* Offset of transmit registers */
u32 XmtRegsize; /* size of transmit registers */
u32 FileRegOff; /* Offset of register file */
u32 FileRegsize; /* size of register file */
u32 SramOff; /* Offset of Sram */
u32 Sramsize; /* size of Sram */
u32 DramOff; /* Offset of Dram */
u32 Dramsize; /* size of Dram */
CORE_Q queues[SLIC_MAX_QUEUE]; /* size and offsets of queues */
u32 CamAMOff; /* Offset of CAM A contents */
u32 CamASize; /* Size of Cam A */
u32 CamBMOff; /* Offset of CAM B contents */
u32 CamBSize; /* Size of Cam B */
u32 CamCMOff; /* Offset of CAM C contents */
u32 CamCSize; /* Size of Cam C */
u32 CamDMOff; /* Offset of CAM D contents */
u32 CamDSize; /* Size of Cam D */
};
/*
* definitions needed for our kernel-mode gdb stub.
*/
/***********************************************************************
*
* Definitions & Typedefs
*
**********************************************************************/
#define BUFMAX 0x20000 /* 128k - size of input/output buffer */
#define BUFMAXP2 5 /* 2**5 (32) 4K pages */
#define IOCTL_SIMBA_BREAK _IOW('s', 0, unsigned long)
/* #define IOCTL_SIMBA_INIT _IOW('s', 1, unsigned long) */
#define IOCTL_SIMBA_KILL_TGT_PROC _IOW('s', 2, unsigned long)
/***********************************************************************
*
* Global variables
*
***********************************************************************/
#define THREADRECEIVE 1 /* bit 0 of StoppedThreads */
#define THREADTRANSMIT 2 /* bit 1 of StoppedThreads */
#define THREADBOTH 3 /* bit 0 and 1.. */
#endif /* _SLIC_DUMP_H */

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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slichw.h
*
* This header file contains definitions that are common to our hardware.
*/
#ifndef __SLICHW_H__
#define __SLICHW_H__
#define PCI_VENDOR_ID_ALACRITECH 0x139A
#define SLIC_1GB_DEVICE_ID 0x0005
#define SLIC_2GB_DEVICE_ID 0x0007 /*Oasis Device ID */
#define SLIC_1GB_CICADA_SUBSYS_ID 0x0008
#define SLIC_NBR_MACS 4
#define SLIC_RCVBUF_SIZE 2048
#define SLIC_RCVBUF_HEADSIZE 34
#define SLIC_RCVBUF_TAILSIZE 0
#define SLIC_RCVBUF_DATASIZE (SLIC_RCVBUF_SIZE - (SLIC_RCVBUF_HEADSIZE +\
SLIC_RCVBUF_TAILSIZE))
#define VGBSTAT_XPERR 0x40000000
#define VGBSTAT_XERRSHFT 25
#define VGBSTAT_XCSERR 0x23
#define VGBSTAT_XUFLOW 0x22
#define VGBSTAT_XHLEN 0x20
#define VGBSTAT_NETERR 0x01000000
#define VGBSTAT_NERRSHFT 16
#define VGBSTAT_NERRMSK 0x1ff
#define VGBSTAT_NCSERR 0x103
#define VGBSTAT_NUFLOW 0x102
#define VGBSTAT_NHLEN 0x100
#define VGBSTAT_LNKERR 0x00000080
#define VGBSTAT_LERRMSK 0xff
#define VGBSTAT_LDEARLY 0x86
#define VGBSTAT_LBOFLO 0x85
#define VGBSTAT_LCODERR 0x84
#define VGBSTAT_LDBLNBL 0x83
#define VGBSTAT_LCRCERR 0x82
#define VGBSTAT_LOFLO 0x81
#define VGBSTAT_LUFLO 0x80
#define IRHDDR_FLEN_MSK 0x0000ffff
#define IRHDDR_SVALID 0x80000000
#define IRHDDR_ERR 0x10000000
#define VRHSTAT_802OE 0x80000000
#define VRHSTAT_TPOFLO 0x10000000
#define VRHSTATB_802UE 0x80000000
#define VRHSTATB_RCVE 0x40000000
#define VRHSTATB_BUFF 0x20000000
#define VRHSTATB_CARRE 0x08000000
#define VRHSTATB_LONGE 0x02000000
#define VRHSTATB_PREA 0x01000000
#define VRHSTATB_CRC 0x00800000
#define VRHSTATB_DRBL 0x00400000
#define VRHSTATB_CODE 0x00200000
#define VRHSTATB_TPCSUM 0x00100000
#define VRHSTATB_TPHLEN 0x00080000
#define VRHSTATB_IPCSUM 0x00040000
#define VRHSTATB_IPLERR 0x00020000
#define VRHSTATB_IPHERR 0x00010000
#define SLIC_MAX64_BCNT 23
#define SLIC_MAX32_BCNT 26
#define IHCMD_XMT_REQ 0x01
#define IHFLG_IFSHFT 2
#define SLIC_RSPBUF_SIZE 32
#define SLIC_RESET_MAGIC 0xDEAD
#define ICR_INT_OFF 0
#define ICR_INT_ON 1
#define ICR_INT_MASK 2
#define ISR_ERR 0x80000000
#define ISR_RCV 0x40000000
#define ISR_CMD 0x20000000
#define ISR_IO 0x60000000
#define ISR_UPC 0x10000000
#define ISR_LEVENT 0x08000000
#define ISR_RMISS 0x02000000
#define ISR_UPCERR 0x01000000
#define ISR_XDROP 0x00800000
#define ISR_UPCBSY 0x00020000
#define ISR_EVMSK 0xffff0000
#define ISR_PINGMASK 0x00700000
#define ISR_PINGDSMASK 0x00710000
#define ISR_UPCMASK 0x11000000
#define SLIC_WCS_START 0x80000000
#define SLIC_WCS_COMPARE 0x40000000
#define SLIC_RCVWCS_BEGIN 0x40000000
#define SLIC_RCVWCS_FINISH 0x80000000
#define SLIC_PM_MAXPATTERNS 6
#define SLIC_PM_PATTERNSIZE 128
#define SLIC_PMCAPS_WAKEONLAN 0x00000001
#define MIICR_REG_PCR 0x00000000
#define MIICR_REG_4 0x00040000
#define MIICR_REG_9 0x00090000
#define MIICR_REG_16 0x00100000
#define PCR_RESET 0x8000
#define PCR_POWERDOWN 0x0800
#define PCR_SPEED_100 0x2000
#define PCR_SPEED_1000 0x0040
#define PCR_AUTONEG 0x1000
#define PCR_AUTONEG_RST 0x0200
#define PCR_DUPLEX_FULL 0x0100
#define PSR_LINKUP 0x0004
#define PAR_ADV100FD 0x0100
#define PAR_ADV100HD 0x0080
#define PAR_ADV10FD 0x0040
#define PAR_ADV10HD 0x0020
#define PAR_ASYMPAUSE 0x0C00
#define PAR_802_3 0x0001
#define PAR_ADV1000XFD 0x0020
#define PAR_ADV1000XHD 0x0040
#define PAR_ASYMPAUSE_FIBER 0x0180
#define PGC_ADV1000FD 0x0200
#define PGC_ADV1000HD 0x0100
#define SEEQ_LINKFAIL 0x4000
#define SEEQ_SPEED 0x0080
#define SEEQ_DUPLEX 0x0040
#define TDK_DUPLEX 0x0800
#define TDK_SPEED 0x0400
#define MRV_REG16_XOVERON 0x0068
#define MRV_REG16_XOVEROFF 0x0008
#define MRV_SPEED_1000 0x8000
#define MRV_SPEED_100 0x4000
#define MRV_SPEED_10 0x0000
#define MRV_FULLDUPLEX 0x2000
#define MRV_LINKUP 0x0400
#define GIG_LINKUP 0x0001
#define GIG_FULLDUPLEX 0x0002
#define GIG_SPEED_MASK 0x000C
#define GIG_SPEED_1000 0x0008
#define GIG_SPEED_100 0x0004
#define GIG_SPEED_10 0x0000
#define MCR_RESET 0x80000000
#define MCR_CRCEN 0x40000000
#define MCR_FULLD 0x10000000
#define MCR_PAD 0x02000000
#define MCR_RETRYLATE 0x01000000
#define MCR_BOL_SHIFT 21
#define MCR_IPG1_SHIFT 14
#define MCR_IPG2_SHIFT 7
#define MCR_IPG3_SHIFT 0
#define GMCR_RESET 0x80000000
#define GMCR_GBIT 0x20000000
#define GMCR_FULLD 0x10000000
#define GMCR_GAPBB_SHIFT 14
#define GMCR_GAPR1_SHIFT 7
#define GMCR_GAPR2_SHIFT 0
#define GMCR_GAPBB_1000 0x60
#define GMCR_GAPR1_1000 0x2C
#define GMCR_GAPR2_1000 0x40
#define GMCR_GAPBB_100 0x70
#define GMCR_GAPR1_100 0x2C
#define GMCR_GAPR2_100 0x40
#define XCR_RESET 0x80000000
#define XCR_XMTEN 0x40000000
#define XCR_PAUSEEN 0x20000000
#define XCR_LOADRNG 0x10000000
#define RCR_RESET 0x80000000
#define RCR_RCVEN 0x40000000
#define RCR_RCVALL 0x20000000
#define RCR_RCVBAD 0x10000000
#define RCR_CTLEN 0x08000000
#define RCR_ADDRAEN 0x02000000
#define GXCR_RESET 0x80000000
#define GXCR_XMTEN 0x40000000
#define GXCR_PAUSEEN 0x20000000
#define GRCR_RESET 0x80000000
#define GRCR_RCVEN 0x40000000
#define GRCR_RCVALL 0x20000000
#define GRCR_RCVBAD 0x10000000
#define GRCR_CTLEN 0x08000000
#define GRCR_ADDRAEN 0x02000000
#define GRCR_HASHSIZE_SHIFT 17
#define GRCR_HASHSIZE 14
#define SLIC_EEPROM_ID 0xA5A5
#define SLIC_SRAM_SIZE2GB (64 * 1024)
#define SLIC_SRAM_SIZE1GB (32 * 1024)
#define SLIC_HOSTID_DEFAULT 0xFFFF /* uninitialized hostid */
#define SLIC_NBR_MACS 4
#ifndef FALSE
#define FALSE 0
#else
#undef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1
#else
#undef TRUE
#define TRUE 1
#endif
struct slic_rcvbuf {
unsigned char pad1[6];
ushort pad2;
u32 pad3;
u32 pad4;
u32 buffer;
u32 length;
u32 status;
u32 pad5;
ushort pad6;
unsigned char data[SLIC_RCVBUF_DATASIZE];
};
struct slic_hddr_wds {
union {
struct {
u32 frame_status;
u32 frame_status_b;
u32 time_stamp;
u32 checksum;
} hdrs_14port;
struct {
u32 frame_status;
ushort ByteCnt;
ushort TpChksum;
ushort CtxHash;
ushort MacHash;
u32 BufLnk;
} hdrs_gbit;
} u0;
};
#define frame_status14 u0.hdrs_14port.frame_status
#define frame_status_b14 u0.hdrs_14port.frame_status_b
#define frame_statusGB u0.hdrs_gbit.frame_status
struct slic_host64sg {
u32 paddrl;
u32 paddrh;
u32 length;
};
struct slic_host64_cmd {
u32 hosthandle;
u32 RSVD;
unsigned char command;
unsigned char flags;
union {
ushort rsv1;
ushort rsv2;
} u0;
union {
struct {
u32 totlen;
struct slic_host64sg bufs[SLIC_MAX64_BCNT];
} slic_buffers;
} u;
};
struct slic_rspbuf {
u32 hosthandle;
u32 pad0;
u32 pad1;
u32 status;
u32 pad2[4];
};
struct slic_regs {
u32 slic_reset; /* Reset Register */
u32 pad0;
u32 slic_icr; /* Interrupt Control Register */
u32 pad2;
#define SLIC_ICR 0x0008
u32 slic_isp; /* Interrupt status pointer */
u32 pad1;
#define SLIC_ISP 0x0010
u32 slic_isr; /* Interrupt status */
u32 pad3;
#define SLIC_ISR 0x0018
u32 slic_hbar; /* Header buffer address reg */
u32 pad4;
/* 31-8 - phy addr of set of contiguous hdr buffers
7-0 - number of buffers passed
Buffers are 256 bytes long on 256-byte boundaries. */
#define SLIC_HBAR 0x0020
#define SLIC_HBAR_CNT_MSK 0x000000FF
u32 slic_dbar; /* Data buffer handle & address reg */
u32 pad5;
/* 4 sets of registers; Buffers are 2K bytes long 2 per 4K page. */
#define SLIC_DBAR 0x0028
#define SLIC_DBAR_SIZE 2048
u32 slic_cbar; /* Xmt Cmd buf addr regs.*/
/* 1 per XMT interface
31-5 - phy addr of host command buffer
4-0 - length of cmd in multiples of 32 bytes
Buffers are 32 bytes up to 512 bytes long */
#define SLIC_CBAR 0x0030
#define SLIC_CBAR_LEN_MSK 0x0000001F
#define SLIC_CBAR_ALIGN 0x00000020
u32 slic_wcs; /* write control store*/
#define SLIC_WCS 0x0034
#define SLIC_WCS_START 0x80000000 /*Start the SLIC (Jump to WCS)*/
#define SLIC_WCS_COMPARE 0x40000000 /* Compare with value in WCS*/
u32 slic_rbar; /* Response buffer address reg.*/
u32 pad7;
/*31-8 - phy addr of set of contiguous response buffers
7-0 - number of buffers passed
Buffers are 32 bytes long on 32-byte boundaries.*/
#define SLIC_RBAR 0x0038
#define SLIC_RBAR_CNT_MSK 0x000000FF
#define SLIC_RBAR_SIZE 32
u32 slic_stats; /* read statistics (UPR) */
u32 pad8;
#define SLIC_RSTAT 0x0040
u32 slic_rlsr; /* read link status */
u32 pad9;
#define SLIC_LSTAT 0x0048
u32 slic_wmcfg; /* Write Mac Config */
u32 pad10;
#define SLIC_WMCFG 0x0050
u32 slic_wphy; /* Write phy register */
u32 pad11;
#define SLIC_WPHY 0x0058
u32 slic_rcbar; /*Rcv Cmd buf addr reg*/
u32 pad12;
#define SLIC_RCBAR 0x0060
u32 slic_rconfig; /* Read SLIC Config*/
u32 pad13;
#define SLIC_RCONFIG 0x0068
u32 slic_intagg; /* Interrupt aggregation time*/
u32 pad14;
#define SLIC_INTAGG 0x0070
u32 slic_wxcfg; /* Write XMIT config reg*/
u32 pad16;
#define SLIC_WXCFG 0x0078
u32 slic_wrcfg; /* Write RCV config reg*/
u32 pad17;
#define SLIC_WRCFG 0x0080
u32 slic_wraddral; /* Write rcv addr a low*/
u32 pad18;
#define SLIC_WRADDRAL 0x0088
u32 slic_wraddrah; /* Write rcv addr a high*/
u32 pad19;
#define SLIC_WRADDRAH 0x0090
u32 slic_wraddrbl; /* Write rcv addr b low*/
u32 pad20;
#define SLIC_WRADDRBL 0x0098
u32 slic_wraddrbh; /* Write rcv addr b high*/
u32 pad21;
#define SLIC_WRADDRBH 0x00a0
u32 slic_mcastlow; /* Low bits of mcast mask*/
u32 pad22;
#define SLIC_MCASTLOW 0x00a8
u32 slic_mcasthigh; /* High bits of mcast mask*/
u32 pad23;
#define SLIC_MCASTHIGH 0x00b0
u32 slic_ping; /* Ping the card*/
u32 pad24;
#define SLIC_PING 0x00b8
u32 slic_dump_cmd; /* Dump command */
u32 pad25;
#define SLIC_DUMP_CMD 0x00c0
u32 slic_dump_data; /* Dump data pointer */
u32 pad26;
#define SLIC_DUMP_DATA 0x00c8
u32 slic_pcistatus; /* Read card's pci_status register */
u32 pad27;
#define SLIC_PCISTATUS 0x00d0
u32 slic_wrhostid; /* Write hostid field */
u32 pad28;
#define SLIC_WRHOSTID 0x00d8
#define SLIC_RDHOSTID_1GB 0x1554
#define SLIC_RDHOSTID_2GB 0x1554
u32 slic_low_power; /* Put card in a low power state */
u32 pad29;
#define SLIC_LOW_POWER 0x00e0
u32 slic_quiesce; /* force slic into quiescent state
before soft reset */
u32 pad30;
#define SLIC_QUIESCE 0x00e8
u32 slic_reset_iface; /* reset interface queues */
u32 pad31;
#define SLIC_RESET_IFACE 0x00f0
u32 slic_addr_upper; /* Bits 63-32 for host i/f addrs */
u32 pad32;
#define SLIC_ADDR_UPPER 0x00f8 /*Register is only written when it has changed*/
u32 slic_hbar64; /* 64 bit Header buffer address reg */
u32 pad33;
#define SLIC_HBAR64 0x0100
u32 slic_dbar64; /* 64 bit Data buffer handle & address reg */
u32 pad34;
#define SLIC_DBAR64 0x0108
u32 slic_cbar64; /* 64 bit Xmt Cmd buf addr regs. */
u32 pad35;
#define SLIC_CBAR64 0x0110
u32 slic_rbar64; /* 64 bit Response buffer address reg.*/
u32 pad36;
#define SLIC_RBAR64 0x0118
u32 slic_rcbar64; /* 64 bit Rcv Cmd buf addr reg*/
u32 pad37;
#define SLIC_RCBAR64 0x0120
u32 slic_stats64; /*read statistics (64 bit UPR)*/
u32 pad38;
#define SLIC_RSTAT64 0x0128
u32 slic_rcv_wcs; /*Download Gigabit RCV sequencer ucode*/
u32 pad39;
#define SLIC_RCV_WCS 0x0130
#define SLIC_RCVWCS_BEGIN 0x40000000
#define SLIC_RCVWCS_FINISH 0x80000000
u32 slic_wrvlanid; /* Write VlanId field */
u32 pad40;
#define SLIC_WRVLANID 0x0138
u32 slic_read_xf_info; /* Read Transformer info */
u32 pad41;
#define SLIC_READ_XF_INFO 0x0140
u32 slic_write_xf_info; /* Write Transformer info */
u32 pad42;
#define SLIC_WRITE_XF_INFO 0x0148
u32 RSVD1; /* TOE Only */
u32 pad43;
u32 RSVD2; /* TOE Only */
u32 pad44;
u32 RSVD3; /* TOE Only */
u32 pad45;
u32 RSVD4; /* TOE Only */
u32 pad46;
u32 slic_ticks_per_sec; /* Write card ticks per second */
u32 pad47;
#define SLIC_TICKS_PER_SEC 0x0170
};
enum UPR_REQUEST {
SLIC_UPR_STATS,
SLIC_UPR_RLSR,
SLIC_UPR_WCFG,
SLIC_UPR_RCONFIG,
SLIC_UPR_RPHY,
SLIC_UPR_ENLB,
SLIC_UPR_ENCT,
SLIC_UPR_PDWN,
SLIC_UPR_PING,
SLIC_UPR_DUMP,
};
struct inicpm_wakepattern {
u32 patternlength;
unsigned char pattern[SLIC_PM_PATTERNSIZE];
unsigned char mask[SLIC_PM_PATTERNSIZE];
};
struct inicpm_state {
u32 powercaps;
u32 powerstate;
u32 wake_linkstatus;
u32 wake_magicpacket;
u32 wake_framepattern;
struct inicpm_wakepattern wakepattern[SLIC_PM_MAXPATTERNS];
};
struct slicpm_packet_pattern {
u32 priority;
u32 reserved;
u32 masksize;
u32 patternoffset;
u32 patternsize;
u32 patternflags;
};
enum slicpm_power_state {
slicpm_state_unspecified = 0,
slicpm_state_d0,
slicpm_state_d1,
slicpm_state_d2,
slicpm_state_d3,
slicpm_state_maximum
};
struct slicpm_wakeup_capabilities {
enum slicpm_power_state min_magic_packet_wakeup;
enum slicpm_power_state min_pattern_wakeup;
enum slicpm_power_state min_link_change_wakeup;
};
struct slic_pnp_capabilities {
u32 flags;
struct slicpm_wakeup_capabilities wakeup_capabilities;
};
struct xmt_stats {
u32 xmit_tcp_bytes;
u32 xmit_tcp_segs;
u32 xmit_bytes;
u32 xmit_collisions;
u32 xmit_unicasts;
u32 xmit_other_error;
u32 xmit_excess_collisions;
};
struct rcv_stats {
u32 rcv_tcp_bytes;
u32 rcv_tcp_segs;
u32 rcv_bytes;
u32 rcv_unicasts;
u32 rcv_other_error;
u32 rcv_drops;
};
struct xmt_statsgb {
u64 xmit_tcp_bytes;
u64 xmit_tcp_segs;
u64 xmit_bytes;
u64 xmit_collisions;
u64 xmit_unicasts;
u64 xmit_other_error;
u64 xmit_excess_collisions;
};
struct rcv_statsgb {
u64 rcv_tcp_bytes;
u64 rcv_tcp_segs;
u64 rcv_bytes;
u64 rcv_unicasts;
u64 rcv_other_error;
u64 rcv_drops;
};
struct slic_stats {
union {
struct {
struct xmt_stats xmt100;
struct rcv_stats rcv100;
} stats_100;
struct {
struct xmt_statsgb xmtGB;
struct rcv_statsgb rcvGB;
} stats_GB;
} u;
};
#define xmit_tcp_segs100 u.stats_100.xmt100.xmit_tcp_segs
#define xmit_tcp_bytes100 u.stats_100.xmt100.xmit_tcp_bytes
#define xmit_bytes100 u.stats_100.xmt100.xmit_bytes
#define xmit_collisions100 u.stats_100.xmt100.xmit_collisions
#define xmit_unicasts100 u.stats_100.xmt100.xmit_unicasts
#define xmit_other_error100 u.stats_100.xmt100.xmit_other_error
#define xmit_excess_collisions100 u.stats_100.xmt100.xmit_excess_collisions
#define rcv_tcp_segs100 u.stats_100.rcv100.rcv_tcp_segs
#define rcv_tcp_bytes100 u.stats_100.rcv100.rcv_tcp_bytes
#define rcv_bytes100 u.stats_100.rcv100.rcv_bytes
#define rcv_unicasts100 u.stats_100.rcv100.rcv_unicasts
#define rcv_other_error100 u.stats_100.rcv100.rcv_other_error
#define rcv_drops100 u.stats_100.rcv100.rcv_drops
#define xmit_tcp_segs_gb u.stats_GB.xmtGB.xmit_tcp_segs
#define xmit_tcp_bytes_gb u.stats_GB.xmtGB.xmit_tcp_bytes
#define xmit_bytes_gb u.stats_GB.xmtGB.xmit_bytes
#define xmit_collisions_gb u.stats_GB.xmtGB.xmit_collisions
#define xmit_unicasts_gb u.stats_GB.xmtGB.xmit_unicasts
#define xmit_other_error_gb u.stats_GB.xmtGB.xmit_other_error
#define xmit_excess_collisions_gb u.stats_GB.xmtGB.xmit_excess_collisions
#define rcv_tcp_segs_gb u.stats_GB.rcvGB.rcv_tcp_segs
#define rcv_tcp_bytes_gb u.stats_GB.rcvGB.rcv_tcp_bytes
#define rcv_bytes_gb u.stats_GB.rcvGB.rcv_bytes
#define rcv_unicasts_gb u.stats_GB.rcvGB.rcv_unicasts
#define rcv_other_error_gb u.stats_GB.rcvGB.rcv_other_error
#define rcv_drops_gb u.stats_GB.rcvGB.rcv_drops
struct slic_config_mac {
unsigned char macaddrA[6];
};
#define ATK_FRU_FORMAT 0x00
#define VENDOR1_FRU_FORMAT 0x01
#define VENDOR2_FRU_FORMAT 0x02
#define VENDOR3_FRU_FORMAT 0x03
#define VENDOR4_FRU_FORMAT 0x04
#define NO_FRU_FORMAT 0xFF
struct atk_fru {
unsigned char assembly[6];
unsigned char revision[2];
unsigned char serial[14];
unsigned char pad[3];
};
struct vendor1_fru {
unsigned char commodity;
unsigned char assembly[4];
unsigned char revision[2];
unsigned char supplier[2];
unsigned char date[2];
unsigned char sequence[3];
unsigned char pad[13];
};
struct vendor2_fru {
unsigned char part[8];
unsigned char supplier[5];
unsigned char date[3];
unsigned char sequence[4];
unsigned char pad[7];
};
struct vendor3_fru {
unsigned char assembly[6];
unsigned char revision[2];
unsigned char serial[14];
unsigned char pad[3];
};
struct vendor4_fru {
unsigned char number[8];
unsigned char part[8];
unsigned char version[8];
unsigned char pad[3];
};
union oemfru {
struct vendor1_fru vendor1_fru;
struct vendor2_fru vendor2_fru;
struct vendor3_fru vendor3_fru;
struct vendor4_fru vendor4_fru;
};
/*
SLIC EEPROM structure for Mojave
*/
struct slic_eeprom {
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
ushort FlashSize; /* 02 Flash size */
ushort EepromSize; /* 03 EEPROM Size */
ushort VendorId; /* 04 Vendor ID */
ushort DeviceId; /* 05 Device ID */
unsigned char RevisionId; /* 06 Revision ID */
unsigned char ClassCode[3]; /* 07 Class Code */
unsigned char DbgIntPin; /* 08 Debug Interrupt pin */
unsigned char NetIntPin0; /* Network Interrupt Pin */
unsigned char MinGrant; /* 09 Minimum grant */
unsigned char MaxLat; /* Maximum Latency */
ushort PciStatus; /* 10 PCI Status */
ushort SubSysVId; /* 11 Subsystem Vendor Id */
ushort SubSysId; /* 12 Subsystem ID */
ushort DbgDevId; /* 13 Debug Device Id */
ushort DramRomFn; /* 14 Dram/Rom function */
ushort DSize2Pci; /* 15 DRAM size to PCI (bytes * 64K) */
ushort RSize2Pci; /* 16 ROM extension size to PCI (bytes * 4k) */
unsigned char NetIntPin1;/* 17 Network Interface Pin 1
(simba/leone only) */
unsigned char NetIntPin2; /*Network Interface Pin 2 (simba/leone only)*/
union {
unsigned char NetIntPin3;/*18 Network Interface Pin 3
(simba only)*/
unsigned char FreeTime;/*FreeTime setting (leone/mojave only) */
} u1;
unsigned char TBIctl; /* 10-bit interface control (Mojave only) */
ushort DramSize; /* 19 DRAM size (bytes * 64k) */
union {
struct {
/* Mac Interface Specific portions */
struct slic_config_mac MacInfo[SLIC_NBR_MACS];
} mac; /* MAC access for all boards */
struct {
/* use above struct for MAC access */
struct slic_config_mac pad[SLIC_NBR_MACS - 1];
ushort DeviceId2; /* Device ID for 2nd
PCI function */
unsigned char IntPin2; /* Interrupt pin for
2nd PCI function */
unsigned char ClassCode2[3]; /* Class Code for 2nd
PCI function */
} mojave; /* 2nd function access for gigabit board */
} u2;
ushort CfgByte6; /* Config Byte 6 */
ushort PMECapab; /* Power Mgment capabilities */
ushort NwClkCtrls; /* NetworkClockControls */
unsigned char FruFormat; /* Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
unsigned char OemFruFormat; /* optional OEM FRU format type */
union oemfru OemFru; /* optional OEM FRU information */
unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 cksum bytes
*(if OEM FRU info exists) and two unusable
* bytes at the end */
};
/* SLIC EEPROM structure for Oasis */
struct oslic_eeprom {
ushort Id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
ushort EecodeSize; /* 01 Size of EEPROM Codes (bytes * 4)*/
ushort FlashConfig0; /* 02 Flash Config for SPI device 0 */
ushort FlashConfig1; /* 03 Flash Config for SPI device 1 */
ushort VendorId; /* 04 Vendor ID */
ushort DeviceId; /* 05 Device ID (function 0) */
unsigned char RevisionId; /* 06 Revision ID */
unsigned char ClassCode[3]; /* 07 Class Code for PCI function 0 */
unsigned char IntPin1; /* 08 Interrupt pin for PCI function 1*/
unsigned char ClassCode2[3]; /* 09 Class Code for PCI function 1 */
unsigned char IntPin2; /* 10 Interrupt pin for PCI function 2*/
unsigned char IntPin0; /* Interrupt pin for PCI function 0*/
unsigned char MinGrant; /* 11 Minimum grant */
unsigned char MaxLat; /* Maximum Latency */
ushort SubSysVId; /* 12 Subsystem Vendor Id */
ushort SubSysId; /* 13 Subsystem ID */
ushort FlashSize; /* 14 Flash size (bytes / 4K) */
ushort DSize2Pci; /* 15 DRAM size to PCI (bytes / 64K) */
ushort RSize2Pci; /* 16 Flash (ROM extension) size to
PCI (bytes / 4K) */
ushort DeviceId1; /* 17 Device Id (function 1) */
ushort DeviceId2; /* 18 Device Id (function 2) */
ushort CfgByte6; /* 19 Device Status Config Bytes 6-7 */
ushort PMECapab; /* 20 Power Mgment capabilities */
unsigned char MSICapab; /* 21 MSI capabilities */
unsigned char ClockDivider; /* Clock divider */
ushort PciStatusLow; /* 22 PCI Status bits 15:0 */
ushort PciStatusHigh; /* 23 PCI Status bits 31:16 */
ushort DramConfigLow; /* 24 DRAM Configuration bits 15:0 */
ushort DramConfigHigh; /* 25 DRAM Configuration bits 31:16 */
ushort DramSize; /* 26 DRAM size (bytes / 64K) */
ushort GpioTbiCtl;/* 27 GPIO/TBI controls for functions 1/0 */
ushort EepromSize; /* 28 EEPROM Size */
struct slic_config_mac MacInfo[2]; /* 29 MAC addresses (2 ports) */
unsigned char FruFormat; /* 35 Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
unsigned char OemFruFormat; /* optional OEM FRU format type */
union oemfru OemFru; /* optional OEM FRU information */
unsigned char Pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
* (if OEM FRU info exists) and two unusable
* bytes at the end
*/
};
#define MAX_EECODE_SIZE sizeof(struct slic_eeprom)
#define MIN_EECODE_SIZE 0x62 /* code size without optional OEM FRU stuff */
/* SLIC CONFIG structure
This structure lives in the CARD structure and is valid for all
board types. It is filled in from the appropriate EEPROM structure
by SlicGetConfigData().
*/
struct slic_config {
bool EepromValid; /* Valid EEPROM flag (checksum good?) */
ushort DramSize; /* DRAM size (bytes / 64K) */
struct slic_config_mac MacInfo[SLIC_NBR_MACS]; /* MAC addresses */
unsigned char FruFormat; /* Alacritech FRU format type */
struct atk_fru AtkFru; /* Alacritech FRU information */
unsigned char OemFruFormat; /* optional OEM FRU format type */
union {
struct vendor1_fru vendor1_fru;
struct vendor2_fru vendor2_fru;
struct vendor3_fru vendor3_fru;
struct vendor4_fru vendor4_fru;
} OemFru;
};
#pragma pack()
#endif

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drivers/staging/slicoss/slicinc.h Normal file
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/**************************************************************************
*
* Copyright (c) 2000-2002 Alacritech, Inc. All rights reserved.
*
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: slicinc.h
*
* This file contains all other include files and prototype definitions
* for the SLICOSS driver.
*/
#ifndef _SLIC_INCLUDE_H_
#define _SLIC_INCLUDE_H_
#include "slic_os.h"
#include "slicdbg.h"
#include "slichw.h"
#include "slic.h"
static int slic_entry_probe(struct pci_dev *pcidev,
const struct pci_device_id *ent);
static void slic_entry_remove(struct pci_dev *pcidev);
static void slic_init_driver(void);
static int slic_entry_open(struct net_device *dev);
static int slic_entry_halt(struct net_device *dev);
static int slic_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
static int slic_xmit_start(struct sk_buff *skb, struct net_device *dev);
static void slic_xmit_fail(struct adapter *adapter,
struct sk_buff *skb,
void *cmd,
u32 skbtype,
u32 status);
static void slic_config_pci(struct pci_dev *pcidev);
static struct sk_buff *slic_rcvqueue_getnext(struct adapter *adapter);
static inline void slic_reg32_write(void __iomem *reg, u32 value, uint flush);
static inline void slic_reg64_write(struct adapter *adapter, void __iomem *reg,
u32 value, void __iomem *regh, u32 paddrh, uint flush);
#if SLIC_GET_STATS_ENABLED
static struct net_device_stats *slic_get_stats(struct net_device *dev);
#endif
static int slic_mac_set_address(struct net_device *dev, void *ptr);
static void slic_rcv_handler(struct adapter *adapter);
static void slic_link_event_handler(struct adapter *adapter);
static void slic_xmit_complete(struct adapter *adapter);
static void slic_upr_request_complete(struct adapter *adapter, u32 isr);
static int slic_rspqueue_init(struct adapter *adapter);
static int slic_rspqueue_reset(struct adapter *adapter);
static void slic_rspqueue_free(struct adapter *adapter);
static struct slic_rspbuf *slic_rspqueue_getnext(struct adapter *adapter);
static void slic_cmdqmem_init(struct adapter *adapter);
static void slic_cmdqmem_free(struct adapter *adapter);
static u32 *slic_cmdqmem_addpage(struct adapter *adapter);
static int slic_cmdq_init(struct adapter *adapter);
static void slic_cmdq_free(struct adapter *adapter);
static void slic_cmdq_reset(struct adapter *adapter);
static void slic_cmdq_addcmdpage(struct adapter *adapter, u32 *page);
static void slic_cmdq_getdone(struct adapter *adapter);
static void slic_cmdq_putdone_irq(struct adapter *adapter,
struct slic_hostcmd *cmd);
static struct slic_hostcmd *slic_cmdq_getfree(struct adapter *adapter);
static int slic_rcvqueue_init(struct adapter *adapter);
static int slic_rcvqueue_reset(struct adapter *adapter);
static int slic_rcvqueue_fill(struct adapter *adapter);
static u32 slic_rcvqueue_reinsert(struct adapter *adapter, struct sk_buff *skb);
static void slic_rcvqueue_free(struct adapter *adapter);
static void slic_rcv_handle_error(struct adapter *adapter,
struct slic_rcvbuf *rcvbuf);
static void slic_adapter_set_hwaddr(struct adapter *adapter);
static int slic_card_init(struct sliccard *card, struct adapter *adapter);
static void slic_intagg_set(struct adapter *adapter, u32 value);
static int slic_card_download(struct adapter *adapter);
static u32 slic_card_locate(struct adapter *adapter);
static void slic_if_stop_queue(struct adapter *adapter);
static void slic_if_start_queue(struct adapter *adapter);
static int slic_if_init(struct adapter *adapter);
static int slic_adapter_allocresources(struct adapter *adapter);
static void slic_adapter_freeresources(struct adapter *adapter);
static void slic_link_config(struct adapter *adapter, u32 linkspeed,
u32 linkduplex);
static void slic_unmap_mmio_space(struct adapter *adapter);
static void slic_card_cleanup(struct sliccard *card);
static void slic_init_cleanup(struct adapter *adapter);
static void slic_soft_reset(struct adapter *adapter);
static bool slic_mac_filter(struct adapter *adapter,
struct ether_header *ether_frame);
static void slic_mac_address_config(struct adapter *adapter);
static void slic_mac_config(struct adapter *adapter);
static void slic_mcast_set_mask(struct adapter *adapter);
static int slic_mcast_add_list(struct adapter *adapter, char *address);
static unsigned char slic_mcast_get_mac_hash(char *macaddr);
static void slic_mcast_set_bit(struct adapter *adapter, char *address);
static void slic_config_set(struct adapter *adapter, bool linkchange);
static void slic_config_clear(struct adapter *adapter);
static void slic_config_get(struct adapter *adapter, u32 config,
u32 configh);
static void slic_timer_load_check(ulong context);
static void slic_timer_ping(ulong dev);
static void slic_assert_fail(void);
static ushort slic_eeprom_cksum(char *m, int len);
/* upr */
static void slic_upr_start(struct adapter *adapter);
static void slic_link_upr_complete(struct adapter *adapter, u32 Isr);
static int slic_upr_request(struct adapter *adapter,
u32 upr_request,
u32 upr_data,
u32 upr_data_h,
u32 upr_buffer,
u32 upr_buffer_h);
static int slic_upr_queue_request(struct adapter *adapter,
u32 upr_request,
u32 upr_data,
u32 upr_data_h,
u32 upr_buffer,
u32 upr_buffer_h);
static void slic_mcast_set_list(struct net_device *dev);
static void slic_mcast_init_crc32(void);
#if SLIC_DUMP_ENABLED
static int slic_dump_thread(void *context);
static uint slic_init_dump_thread(struct sliccard *card);
static unsigned char slic_get_dump_index(char *path);
static u32 slic_dump_card(struct sliccard *card, bool resume);
static u32 slic_dump_halt(struct sliccard *card, unsigned char proc);
static u32 slic_dump_reg(struct sliccard *card, unsigned char proc);
static u32 slic_dump_data(struct sliccard *card, u32 addr,
ushort count, unsigned char desc);
static u32 slic_dump_queue(struct sliccard *card, u32 buf_phys,
u32 buf_physh, u32 queue);
static u32 slic_dump_load_queue(struct sliccard *card, u32 data,
u32 queue);
static u32 slic_dump_cam(struct sliccard *card, u32 addr,
u32 count, unsigned char desc);
static u32 slic_dump_resume(struct sliccard *card, unsigned char proc);
static u32 slic_dump_send_cmd(struct sliccard *card, u32 cmd_phys,
u32 cmd_physh, u32 buf_phys,
u32 buf_physh);
#define create_file(x) STATUS_SUCCESS
#define write_file(w, x, y, z) STATUS_SUCCESS
#define close_file(x) STATUS_SUCCESS
#define read_file(w, x, y, z) STATUS_SUCCESS
#define open_file(x) STATUS_SUCCESS
/* PAGE_SIZE * 16 */
#define DUMP_PAGE_SIZE 0xFFFF
#define DUMP_PAGE_SIZE_HALF 0x7FFE
#endif
#endif /* _SLIC_INCLUDE_H_ */

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#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
static int __init staging_init(void)
{
return 0;
}
static void __exit staging_exit(void)
{
}
module_init(staging_init);
module_exit(staging_exit);
MODULE_AUTHOR("Greg Kroah-Hartman");
MODULE_DESCRIPTION("Staging Core");
MODULE_LICENSE("GPL");

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config SXG
tristate "Alacritech SLIC Technology Non-Accelerated 10Gbe support"
depends on PCI && NETDEV_10000
default n
help
This driver supports the Alacritech SLIC Technology Non-Accelerated
10Gbe network cards.
To compile this driver as a module, choose
M here: the module will be called sxg.

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obj-$(CONFIG_SXG) += sxg.o

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This is the rough cut at a driver for the Alacritech SLIC Technology
Non-Accelerated 10Gbe network driver.
TODO:
- lindent the code
- remove typedefs
- remove wrappers
- checkpatch.pl cleanups
- new functionality that the card needs
Please send patches to:
Greg Kroah-Hartman <gregkh@suse.de>
for any cleanups that you do to this driver.

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/**************************************************************************
*
* Copyright © 2000-2008 Alacritech, Inc. All rights reserved.
*
* $Id: sxg.h,v 1.3 2008/07/24 17:25:08 chris Exp $
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY ALACRITECH, INC. ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL ALACRITECH, INC. OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* The views and conclusions contained in the software and documentation
* are those of the authors and should not be interpreted as representing
* official policies, either expressed or implied, of Alacritech, Inc.
*
**************************************************************************/
/*
* FILENAME: sxg.h
*
* This is the base set of header definitions for the SXG driver.
*/
#ifndef __SXG_DRIVER_H__
#define __SXG_DRIVER_H__
#define p_net_device struct net_device *
// SXG_STATS - Probably move these to someplace where
// the slicstat (sxgstat?) program can get them.
typedef struct _SXG_STATS {
// Xmt
u32 XmtNBL; // Offload send NBL count
u64 DumbXmtBytes; // Dumbnic send bytes
u64 SlowXmtBytes; // Slowpath send bytes
u64 FastXmtBytes; // Fastpath send bytes
u64 DumbXmtPkts; // Dumbnic send packets
u64 SlowXmtPkts; // Slowpath send packets
u64 FastXmtPkts; // Fastpath send packets
u64 DumbXmtUcastPkts; // directed packets
u64 DumbXmtMcastPkts; // Multicast packets
u64 DumbXmtBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
u64 DumbXmtUcastBytes; // OID_GEN_DIRECTED_BYTES_XMIT
u64 DumbXmtMcastBytes; // OID_GEN_MULTICAST_BYTES_XMIT
u64 DumbXmtBcastBytes; // OID_GEN_BROADCAST_BYTES_XMIT
u64 XmtErrors; // OID_GEN_XMIT_ERROR
u64 XmtDiscards; // OID_GEN_XMIT_DISCARDS
u64 XmtOk; // OID_GEN_XMIT_OK
u64 XmtQLen; // OID_GEN_TRANSMIT_QUEUE_LENGTH
u64 XmtZeroFull; // Transmit ring zero full
// Rcv
u32 RcvNBL; // Offload recieve NBL count
u64 DumbRcvBytes; // dumbnic recv bytes
u64 DumbRcvUcastBytes; // OID_GEN_DIRECTED_BYTES_RCV
u64 DumbRcvMcastBytes; // OID_GEN_MULTICAST_BYTES_RCV
u64 DumbRcvBcastBytes; // OID_GEN_BROADCAST_BYTES_RCV
u64 SlowRcvBytes; // Slowpath recv bytes
u64 FastRcvBytes; // Fastpath recv bytes
u64 DumbRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
u64 DumbRcvTcpPkts; // See SxgCollectStats
u64 DumbRcvUcastPkts; // directed packets
u64 DumbRcvMcastPkts; // Multicast packets
u64 DumbRcvBcastPkts; // OID_GEN_BROADCAST_FRAMES_RCV
u64 SlowRcvPkts; // OID_GEN_DIRECTED_FRAMES_RCV
u64 RcvErrors; // OID_GEN_RCV_ERROR
u64 RcvDiscards; // OID_GEN_RCV_DISCARDS
u64 RcvNoBuffer; // OID_GEN_RCV_NO_BUFFER
u64 PdqFull; // Processed Data Queue Full
u64 EventRingFull; // Event ring full
// Verbose stats
u64 MaxSends; // Max sends outstanding
u64 NoSglBuf; // SGL buffer allocation failure
u64 SglFail; // NDIS SGL failure
u64 SglAsync; // NDIS SGL failure
u64 NoMem; // Memory allocation failure
u64 NumInts; // Interrupts
u64 FalseInts; // Interrupt with ISR == 0
u64 XmtDrops; // No sahara DRAM buffer for xmt
// Sahara receive status
u64 TransportCsum; // SXG_RCV_STATUS_TRANSPORT_CSUM
u64 TransportUflow; // SXG_RCV_STATUS_TRANSPORT_UFLOW
u64 TransportHdrLen; // SXG_RCV_STATUS_TRANSPORT_HDRLEN
u64 NetworkCsum; // SXG_RCV_STATUS_NETWORK_CSUM:
u64 NetworkUflow; // SXG_RCV_STATUS_NETWORK_UFLOW:
u64 NetworkHdrLen; // SXG_RCV_STATUS_NETWORK_HDRLEN:
u64 Parity; // SXG_RCV_STATUS_PARITY
u64 LinkParity; // SXG_RCV_STATUS_LINK_PARITY:
u64 LinkEarly; // SXG_RCV_STATUS_LINK_EARLY:
u64 LinkBufOflow; // SXG_RCV_STATUS_LINK_BUFOFLOW:
u64 LinkCode; // SXG_RCV_STATUS_LINK_CODE:
u64 LinkDribble; // SXG_RCV_STATUS_LINK_DRIBBLE:
u64 LinkCrc; // SXG_RCV_STATUS_LINK_CRC:
u64 LinkOflow; // SXG_RCV_STATUS_LINK_OFLOW:
u64 LinkUflow; // SXG_RCV_STATUS_LINK_UFLOW:
} SXG_STATS, *PSXG_STATS;
/****************************************************************************
* DUMB-NIC Send path definitions
****************************************************************************/
#define SXG_COMPLETE_DUMB_SEND(_pAdapt, _skb) { \
ASSERT(_skb); \
dev_kfree_skb_irq(_skb); \
}
#define SXG_DROP_DUMB_SEND(_pAdapt, _skb) { \
ASSERT(_skb); \
dev_kfree_skb(_skb); \
}
// Locate current receive header buffer location. Use this
// instead of RcvDataHdr->VirtualAddress since the data
// may have been offset by SXG_ADVANCE_MDL_OFFSET
#define SXG_RECEIVE_DATA_LOCATION(_RcvDataHdr) (_RcvDataHdr)->skb->data
/************************************************************************
* Dumb-NIC receive processing
************************************************************************/
// Define an SXG_PACKET as an NDIS_PACKET
#define PSXG_PACKET struct sk_buff *
// Indications array size
#define SXG_RCV_ARRAYSIZE 64
#define SXG_ALLOCATE_RCV_PACKET(_pAdapt, _RcvDataBufferHdr) { \
struct sk_buff * skb; \
skb = alloc_skb(2048, GFP_ATOMIC); \
if (skb) { \
(_RcvDataBufferHdr)->skb = skb; \
skb->next = NULL; \
} else { \
(_RcvDataBufferHdr)->skb = NULL; \
} \
}
#define SXG_FREE_RCV_PACKET(_RcvDataBufferHdr) { \
if((_RcvDataBufferHdr)->skb) { \
dev_kfree_skb((_RcvDataBufferHdr)->skb); \
} \
}
// Macro to add a NDIS_PACKET to an indication array
// If we fill up our array of packet pointers, then indicate this
// block up now and start on a new one.
#define SXG_ADD_RCV_PACKET(_pAdapt, _Packet, _PrevPacket, _IndicationList, _NumPackets) { \
(_IndicationList)[_NumPackets] = (_Packet); \
(_NumPackets)++; \
if((_NumPackets) == SXG_RCV_ARRAYSIZE) { \
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
(_NumPackets), 0, 0, 0); \
netif_rx((_IndicationList),(_NumPackets)); \
(_NumPackets) = 0; \
} \
}
#define SXG_INDICATE_PACKETS(_pAdapt, _IndicationList, _NumPackets) { \
if(_NumPackets) { \
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "IndicRcv", \
(_NumPackets), 0, 0, 0); \
netif_rx((_IndicationList),(_NumPackets)); \
(_NumPackets) = 0; \
} \
}
#define SXG_REINIATIALIZE_PACKET(_Packet) \
{} /*_NdisReinitializePacket(_Packet)*/ /* this is not necessary with an skb */
// Definitions to initialize Dumb-nic Receive NBLs
#define SXG_RCV_PACKET_BUFFER_HDR(_Packet) (((PSXG_RCV_NBL_RESERVED)((_Packet)->MiniportReservedEx))->RcvDataBufferHdr)
#define SXG_RCV_SET_CHECKSUM_INFO(_Packet, _Cpi) \
NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), TcpIpChecksumPacketInfo) = (PVOID)(_Cpi)
#define SXG_RCV_SET_TOEPLITZ(_Packet, _Toeplitz, _Type, _Function) { \
NDIS_PACKET_SET_HASH_VALUE((_Packet), (_Toeplitz)); \
NDIS_PACKET_SET_HASH_TYPE((_Packet), (_Type)); \
NDIS_PACKET_SET_HASH_FUNCTION((_Packet), (_Function)); \
}
#define SXG_RCV_SET_VLAN_INFO(_Packet, _VlanId, _Priority) { \
NDIS_PACKET_8021Q_INFO _Packet8021qInfo; \
_Packet8021qInfo.TagHeader.VlanId = (_VlanId); \
_Packet8021qInfo.TagHeader.UserPriority = (_Priority); \
NDIS_PER_PACKET_INFO_FROM_PACKET((_Packet), Ieee8021QNetBufferListInfo) = \
_Packet8021qInfo.Value; \
}
#define SXG_ADJUST_RCV_PACKET(_Packet, _RcvDataBufferHdr, _Event) { \
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "DumbRcv", \
(_RcvDataBufferHdr), (_Packet), \
(_Event)->Status, 0); \
ASSERT((_Event)->Length <= (_RcvDataBufferHdr)->Size); \
Packet->len = (_Event)->Length; \
}
///////////////////////////////////////////////////////////////////////////////
// Macros to free a receive data buffer and receive data descriptor block
///////////////////////////////////////////////////////////////////////////////
// NOTE - Lock must be held with RCV macros
#define SXG_GET_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
PLIST_ENTRY _ple; \
_Hdr = NULL; \
if((_pAdapt)->FreeRcvBufferCount) { \
ASSERT(!(IsListEmpty(&(_pAdapt)->FreeRcvBuffers))); \
_ple = RemoveHeadList(&(_pAdapt)->FreeRcvBuffers); \
(_Hdr) = container_of(_ple, SXG_RCV_DATA_BUFFER_HDR, FreeList); \
(_pAdapt)->FreeRcvBufferCount--; \
ASSERT((_Hdr)->State == SXG_BUFFER_FREE); \
} \
}
#define SXG_FREE_RCV_DATA_BUFFER(_pAdapt, _Hdr) { \
SXG_TRACE(TRACE_SXG, SxgTraceBuffer, TRACE_NOISY, "RtnDHdr", \
(_Hdr), (_pAdapt)->FreeRcvBufferCount, \
(_Hdr)->State, (_Hdr)->VirtualAddress); \
/* SXG_RESTORE_MDL_OFFSET(_Hdr); */ \
(_pAdapt)->FreeRcvBufferCount++; \
ASSERT(((_pAdapt)->AllRcvBlockCount * SXG_RCV_DESCRIPTORS_PER_BLOCK) >= (_pAdapt)->FreeRcvBufferCount); \
ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
(_Hdr)->State = SXG_BUFFER_FREE; \
InsertTailList(&(_pAdapt)->FreeRcvBuffers, &((_Hdr)->FreeList)); \
}
#define SXG_FREE_RCV_DESCRIPTOR_BLOCK(_pAdapt, _Hdr) { \
ASSERT((_Hdr)->State != SXG_BUFFER_FREE); \
(_Hdr)->State = SXG_BUFFER_FREE; \
(_pAdapt)->FreeRcvBlockCount++; \
ASSERT((_pAdapt)->AllRcvBlockCount >= (_pAdapt)->FreeRcvBlockCount); \
InsertTailList(&(_pAdapt)->FreeRcvBlocks, &(_Hdr)->FreeList); \
}
// SGL macros
#define SXG_FREE_SGL_BUFFER(_pAdapt, _Sgl, _NB) { \
spin_lock(&(_pAdapt)->SglQLock); \
(_pAdapt)->FreeSglBufferCount++; \
ASSERT((_pAdapt)->AllSglBufferCount >= (_pAdapt)->FreeSglBufferCount);\
ASSERT(!((_Sgl)->State & SXG_BUFFER_FREE)); \
(_Sgl)->State = SXG_BUFFER_FREE; \
InsertTailList(&(_pAdapt)->FreeSglBuffers, &(_Sgl)->FreeList); \
spin_unlock(&(_pAdapt)->SglQLock); \
}
// Get an SGL buffer from the free queue. The first part of this macro
// attempts to keep ahead of buffer depletion by allocating more when
// we hit a minimum threshold. Note that we don't grab the lock
// until after that. We're dealing with round numbers here, so we don't need to,
// and not grabbing it avoids a possible double-trip.
#define SXG_GET_SGL_BUFFER(_pAdapt, _Sgl) { \
PLIST_ENTRY _ple; \
if ((_pAdapt->FreeSglBufferCount < SXG_MIN_SGL_BUFFERS) && \
(_pAdapt->AllSglBufferCount < SXG_MAX_SGL_BUFFERS) && \
(_pAdapt->AllocationsPending == 0)) { \
sxg_allocate_buffer_memory(_pAdapt, \
(sizeof(SXG_SCATTER_GATHER) + SXG_SGL_BUF_SIZE),\
SXG_BUFFER_TYPE_SGL); \
} \
_Sgl = NULL; \
spin_lock(&(_pAdapt)->SglQLock); \
if((_pAdapt)->FreeSglBufferCount) { \
ASSERT(!(IsListEmpty(&(_pAdapt)->FreeSglBuffers))); \
_ple = RemoveHeadList(&(_pAdapt)->FreeSglBuffers); \
(_Sgl) = container_of(_ple, SXG_SCATTER_GATHER, FreeList); \
(_pAdapt)->FreeSglBufferCount--; \
ASSERT((_Sgl)->State == SXG_BUFFER_FREE); \
(_Sgl)->State = SXG_BUFFER_BUSY; \
(_Sgl)->pSgl = NULL; \
} \
spin_unlock(&(_pAdapt)->SglQLock); \
}
//
// SXG_MULTICAST_ADDRESS
//
// Linked list of multicast addresses.
typedef struct _SXG_MULTICAST_ADDRESS {
unsigned char Address[6];
struct _SXG_MULTICAST_ADDRESS *Next;
} SXG_MULTICAST_ADDRESS, *PSXG_MULTICAST_ADDRESS;
// Structure to maintain chimney send and receive buffer queues.
// This structure maintains NET_BUFFER_LIST queues that are
// given to us via the Chimney MiniportTcpOffloadSend and
// MiniportTcpOffloadReceive routines. This structure DOES NOT
// manage our data buffer queue
typedef struct _SXG_BUFFER_QUEUE {
u32 Type; // Slow or fast - See below
u32 Direction; // Xmt or Rcv
u32 Bytes; // Byte count
u32 * Head; // Send queue head
u32 * Tail; // Send queue tail
// PNET_BUFFER_LIST NextNBL; // Short cut - next NBL
// PNET_BUFFER NextNB; // Short cut - next NB
} SXG_BUFFER_QUEUE, *PSXG_BUFFER_QUEUE;
#define SXG_SLOW_SEND_BUFFER 0
#define SXG_FAST_SEND_BUFFER 1
#define SXG_RECEIVE_BUFFER 2
#define SXG_INIT_BUFFER(_Buffer, _Type) { \
(_Buffer)->Type = (_Type); \
if((_Type) == SXG_RECEIVE_BUFFER) { \
(_Buffer)->Direction = 0; \
} else { \
(_Buffer)->Direction = NDIS_SG_LIST_WRITE_TO_DEVICE; \
} \
(_Buffer)->Bytes = 0; \
(_Buffer)->Head = NULL; \
(_Buffer)->Tail = NULL; \
}
#define SXG_RSS_CPU_COUNT(_pAdapt) \
((_pAdapt)->RssEnabled ? NR_CPUS : 1)
/****************************************************************************
* DRIVER and ADAPTER structures
****************************************************************************/
// Adapter states - These states closely match the adapter states
// documented in the DDK (with a few exceptions).
typedef enum _SXG_STATE {
SXG_STATE_INITIALIZING, // Initializing
SXG_STATE_BOOTDIAG, // Boot-Diagnostic mode
SXG_STATE_PAUSING, // Pausing
SXG_STATE_PAUSED, // Paused
SXG_STATE_RUNNING, // Running
SXG_STATE_RESETTING, // Reset in progress
SXG_STATE_SLEEP, // Sleeping
SXG_STATE_DIAG, // Diagnostic mode
SXG_STATE_HALTING, // Halting
SXG_STATE_HALTED, // Down or not-initialized
SXG_STATE_SHUTDOWN // shutdown
} SXG_STATE, *PSXG_STATE;
// Link state
typedef enum _SXG_LINK_STATE {
SXG_LINK_DOWN,
SXG_LINK_UP
} SXG_LINK_STATE, *PSXG_LINK_STATE;
// Link initialization timeout in 100us units
#define SXG_LINK_TIMEOUT 100000 // 10 Seconds - REDUCE!
// Microcode file selection codes
typedef enum _SXG_UCODE_SEL {
SXG_UCODE_SAHARA, // Sahara ucode
SXG_UCODE_SDIAGCPU, // Sahara CPU diagnostic ucode
SXG_UCODE_SDIAGSYS // Sahara system diagnostic ucode
} SXG_UCODE_SEL;
#define SXG_DISABLE_ALL_INTERRUPTS(_padapt) sxg_disable_interrupt(_padapt)
#define SXG_ENABLE_ALL_INTERRUPTS(_padapt) sxg_enable_interrupt(_padapt)
// This probably lives in a proto.h file. Move later
#define SXG_MULTICAST_PACKET(_pether) ((_pether)->ether_dhost[0] & 0x01)
#define SXG_BROADCAST_PACKET(_pether) ((*(u32 *)(_pether)->ether_dhost == 0xFFFFFFFF) && \
(*(u16 *)&(_pether)->ether_dhost[4] == 0xFFFF))
// For DbgPrints
#define SXG_ID DPFLTR_IHVNETWORK_ID
#define SXG_ERROR DPFLTR_ERROR_LEVEL
//
// SXG_DRIVER structure -
//
// contains information about the sxg driver. There is only
// one of these, and it is defined as a global.
typedef struct _SXG_DRIVER {
struct _adapter_t *Adapters; // Linked list of adapters
ushort AdapterID; // Maintain unique adapter ID
} SXG_DRIVER, *PSXG_DRIVER;
#ifdef STATUS_SUCCESS
#undef STATUS_SUCCESS
#endif
#define STATUS_SUCCESS 0
#define STATUS_PENDING 0
#define STATUS_FAILURE -1
#define STATUS_ERROR -2
#define STATUS_NOT_SUPPORTED -3
#define STATUS_BUFFER_TOO_SHORT -4
#define STATUS_RESOURCES -5
#define SLIC_MAX_CARDS 32
#define SLIC_MAX_PORTS 4 /* Max # of ports per card */
#if SLIC_DUMP_ENABLED
// Dump buffer size
//
// This cannot be bigger than the max DMA size the card supports,
// given the current code structure in the host and ucode.
// Mojave supports 16K, Oasis supports 16K-1, so
// just set this at 15K, shouldnt make that much of a diff.
#define DUMP_BUF_SIZE 0x3C00
#endif
#define MIN(a, b) ((u32)(a) < (u32)(b) ? (a) : (b))
#define MAX(a, b) ((u32)(a) > (u32)(b) ? (a) : (b))
typedef struct _mcast_address_t
{
unsigned char address[6];
struct _mcast_address_t *next;
} mcast_address_t, *p_mcast_address_t;
#define CARD_DOWN 0x00000000
#define CARD_UP 0x00000001
#define CARD_FAIL 0x00000002
#define CARD_DIAG 0x00000003
#define CARD_SLEEP 0x00000004
#define ADAPT_DOWN 0x00
#define ADAPT_UP 0x01
#define ADAPT_FAIL 0x02
#define ADAPT_RESET 0x03
#define ADAPT_SLEEP 0x04
#define ADAPT_FLAGS_BOOTTIME 0x0001
#define ADAPT_FLAGS_IS64BIT 0x0002
#define ADAPT_FLAGS_PENDINGLINKDOWN 0x0004
#define ADAPT_FLAGS_FIBERMEDIA 0x0008
#define ADAPT_FLAGS_LOCKS_ALLOCED 0x0010
#define ADAPT_FLAGS_INT_REGISTERED 0x0020
#define ADAPT_FLAGS_LOAD_TIMER_SET 0x0040
#define ADAPT_FLAGS_STATS_TIMER_SET 0x0080
#define ADAPT_FLAGS_RESET_TIMER_SET 0x0100
#define LINK_DOWN 0x00
#define LINK_CONFIG 0x01
#define LINK_UP 0x02
#define LINK_10MB 0x00
#define LINK_100MB 0x01
#define LINK_AUTOSPEED 0x02
#define LINK_1000MB 0x03
#define LINK_10000MB 0x04
#define LINK_HALFD 0x00
#define LINK_FULLD 0x01
#define LINK_AUTOD 0x02
#define MAC_DIRECTED 0x00000001
#define MAC_BCAST 0x00000002
#define MAC_MCAST 0x00000004
#define MAC_PROMISC 0x00000008
#define MAC_LOOPBACK 0x00000010
#define MAC_ALLMCAST 0x00000020
#define SLIC_DUPLEX(x) ((x==LINK_FULLD) ? "FDX" : "HDX")
#define SLIC_SPEED(x) ((x==LINK_100MB) ? "100Mb" : ((x==LINK_1000MB) ? "1000Mb" : " 10Mb"))
#define SLIC_LINKSTATE(x) ((x==LINK_DOWN) ? "Down" : "Up ")
#define SLIC_ADAPTER_STATE(x) ((x==ADAPT_UP) ? "UP" : "Down")
#define SLIC_CARD_STATE(x) ((x==CARD_UP) ? "UP" : "Down")
typedef struct _ether_header
{
unsigned char ether_dhost[6];
unsigned char ether_shost[6];
ushort ether_type;
} ether_header, *p_ether_header;
#define NUM_CFG_SPACES 2
#define NUM_CFG_REGS 64
typedef struct _physcard_t
{
struct _adapter_t *adapter[SLIC_MAX_PORTS];
struct _physcard_t *next;
unsigned int adapters_allocd;
} physcard_t, *p_physcard_t;
typedef struct _sxgbase_driver
{
spinlock_t driver_lock;
unsigned long flags; /* irqsave for spinlock */
u32 num_sxg_cards;
u32 num_sxg_ports;
u32 num_sxg_ports_active;
u32 dynamic_intagg;
p_physcard_t phys_card;
} sxgbase_driver_t;
typedef struct _adapter_t
{
void * ifp;
unsigned int port;
p_physcard_t physcard;
unsigned int physport;
unsigned int cardindex;
unsigned int card_size;
unsigned int chipid;
unsigned int busnumber;
unsigned int slotnumber;
unsigned int functionnumber;
ushort vendid;
ushort devid;
ushort subsysid;
u32 irq;
void * sxg_adapter;
u32 nBusySend;
void __iomem * base_addr;
u32 memorylength;
u32 drambase;
u32 dramlength;
unsigned int queues_initialized;
unsigned int allocated;
unsigned int activated;
u32 intrregistered;
unsigned int isp_initialized;
unsigned int gennumber;
u32 curaddrupper;
u32 isrcopy;
unsigned char state;
unsigned char linkstate;
unsigned char linkspeed;
unsigned char linkduplex;
unsigned int flags;
unsigned char macaddr[6];
unsigned char currmacaddr[6];
u32 macopts;
ushort devflags_prev;
u64 mcastmask;
p_mcast_address_t mcastaddrs;
struct timer_list pingtimer;
u32 pingtimerset;
struct timer_list statstimer;
u32 statstimerset;
struct timer_list vpci_timer;
u32 vpci_timerset;
struct timer_list loadtimer;
u32 loadtimerset;
u32 xmitq_full;
u32 all_reg_writes;
u32 icr_reg_writes;
u32 isr_reg_writes;
u32 error_interrupts;
u32 error_rmiss_interrupts;
u32 rx_errors;
u32 rcv_drops;
u32 rcv_interrupts;
u32 xmit_interrupts;
u32 linkevent_interrupts;
u32 upr_interrupts;
u32 num_isrs;
u32 false_interrupts;
u32 tx_packets;
u32 xmit_completes;
u32 tx_drops;
u32 rcv_broadcasts;
u32 rcv_multicasts;
u32 rcv_unicasts;
u32 max_isr_rcvs;
u32 max_isr_xmits;
u32 rcv_interrupt_yields;
u32 intagg_period;
struct net_device_stats stats;
u32 * MiniportHandle; // Our miniport handle
SXG_STATE State; // Adapter state
SXG_LINK_STATE LinkState; // Link state
u64 LinkSpeed; // Link Speed
u32 PowerState; // NDIS power state
struct _adapter_t *Next; // Linked list
ushort AdapterID; // 1..n
unsigned char MacAddr[6]; // Our permanent HW mac address
unsigned char CurrMacAddr[6]; // Our Current mac address
p_net_device netdev;
p_net_device next_netdevice;
struct pci_dev * pcidev;
PSXG_MULTICAST_ADDRESS MulticastAddrs; // Multicast list
u64 MulticastMask; // Multicast mask
u32 * InterruptHandle; // Register Interrupt handle
u32 InterruptLevel; // From Resource list
u32 InterruptVector; // From Resource list
spinlock_t AdapterLock; /* Serialize access adapter routines */
spinlock_t Bit64RegLock; /* For writing 64-bit addresses */
PSXG_HW_REGS HwRegs; // Sahara HW Register Memory (BAR0/1)
PSXG_UCODE_REGS UcodeRegs; // Microcode Register Memory (BAR2/3)
PSXG_TCB_REGS TcbRegs; // Same as Ucode regs - See sxghw.h
ushort ResetDpcCount; // For timeout
ushort RssDpcCount; // For timeout
ushort VendorID; // Vendor ID
ushort DeviceID; // Device ID
ushort SubSystemID; // Sub-System ID
ushort FrameSize; // Maximum frame size
u32 * DmaHandle; // NDIS DMA handle
u32 * PacketPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
u32 * BufferPoolHandle; // Used with NDIS 5.2 only. Don't ifdef out
u32 MacFilter; // NDIS MAC Filter
ushort IpId; // For slowpath
PSXG_EVENT_RING EventRings; // Host event rings. 1/CPU to 16 max
dma_addr_t PEventRings; // Physical address
u32 NextEvent[SXG_MAX_RSS]; // Current location in ring
dma_addr_t PTcbBuffers; // TCB Buffers - physical address
dma_addr_t PTcbCompBuffers; // TCB Composite Buffers - phys addr
PSXG_XMT_RING XmtRings; // Transmit rings
dma_addr_t PXmtRings; // Transmit rings - physical address
SXG_RING_INFO XmtRingZeroInfo; // Transmit ring 0 info
spinlock_t XmtZeroLock; /* Transmit ring 0 lock */
u32 * XmtRingZeroIndex; // Shared XMT ring 0 index
dma_addr_t PXmtRingZeroIndex; // Shared XMT ring 0 index - physical
LIST_ENTRY FreeProtocolHeaders;// Free protocol headers
u32 FreeProtoHdrCount; // Count
void * ProtocolHeaders; // Block of protocol header
dma_addr_t PProtocolHeaders; // Block of protocol headers - phys
PSXG_RCV_RING RcvRings; // Receive rings
dma_addr_t PRcvRings; // Receive rings - physical address
SXG_RING_INFO RcvRingZeroInfo; // Receive ring 0 info
u32 * Isr; // Interrupt status register
dma_addr_t PIsr; // ISR - physical address
u32 IsrCopy[SXG_MAX_RSS]; // Copy of ISR
ushort InterruptsEnabled; // Bitmask of enabled vectors
unsigned char * IndirectionTable; // RSS indirection table
dma_addr_t PIndirectionTable; // Physical address
ushort RssTableSize; // From NDIS_RECEIVE_SCALE_PARAMETERS
ushort HashKeySize; // From NDIS_RECEIVE_SCALE_PARAMETERS
unsigned char HashSecretKey[40]; // rss key
u32 HashInformation;
// Receive buffer queues
spinlock_t RcvQLock; /* Receive Queue Lock */
LIST_ENTRY FreeRcvBuffers; // Free SXG_DATA_BUFFER queue
LIST_ENTRY FreeRcvBlocks; // Free SXG_RCV_DESCRIPTOR_BLOCK Q
LIST_ENTRY AllRcvBlocks; // All SXG_RCV_BLOCKs
ushort FreeRcvBufferCount; // Number of free rcv data buffers
ushort FreeRcvBlockCount; // # of free rcv descriptor blocks
ushort AllRcvBlockCount; // Number of total receive blocks
ushort ReceiveBufferSize; // SXG_RCV_DATA/JUMBO_BUFFER_SIZE only
u32 AllocationsPending; // Receive allocation pending
u32 RcvBuffersOnCard; // SXG_DATA_BUFFERS owned by card
// SGL buffers
spinlock_t SglQLock; /* SGL Queue Lock */
LIST_ENTRY FreeSglBuffers; // Free SXG_SCATTER_GATHER
LIST_ENTRY AllSglBuffers; // All SXG_SCATTER_GATHER
ushort FreeSglBufferCount; // Number of free SGL buffers
ushort AllSglBufferCount; // Number of total SGL buffers
u32 CurrentTime; // Tick count
u32 FastpathConnections;// # of fastpath connections
// Various single-bit flags:
u32 BasicAllocations:1; // Locks and listheads
u32 IntRegistered:1; // Interrupt registered
u32 PingOutstanding:1; // Ping outstanding to card
u32 Dead:1; // Card dead
u32 DumpDriver:1; // OID_SLIC_DRIVER_DUMP request
u32 DumpCard:1; // OID_SLIC_CARD_DUMP request
u32 DumpCmdRunning:1; // Dump command in progress
u32 DebugRunning:1; // AGDB debug in progress
u32 JumboEnabled:1; // Jumbo frames enabled
u32 MsiEnabled:1; // MSI interrupt enabled
u32 RssEnabled:1; // RSS Enabled
u32 FailOnBadEeprom:1; // Fail on Bad Eeprom
u32 DiagStart:1; // Init adapter for diagnostic start
// Stats
u32 PendingRcvCount; // Outstanding rcv indications
u32 PendingXmtCount; // Outstanding send requests
SXG_STATS Stats; // Statistics
u32 ReassBufs; // Number of reassembly buffers
// Card Crash Info
ushort CrashLocation; // Microcode crash location
unsigned char CrashCpu; // Sahara CPU ID
// Diagnostics
// PDIAG_CMD DiagCmds; // List of free diagnostic commands
// PDIAG_BUFFER DiagBuffers; // List of free diagnostic buffers
// PDIAG_REQ DiagReqQ; // List of outstanding (asynchronous) diag requests
// u32 DiagCmdTimeout; // Time out for diag cmds (seconds) XXXTODO - replace with SXG_PARAM var?
// unsigned char DiagDmaDesc[DMA_CPU_CTXS]; // Free DMA descriptors bit field (32 CPU ctx * 8 DMA ctx)
/////////////////////////////////////////////////////////////////////
// Put preprocessor-conditional fields at the end so we don't
// have to recompile sxgdbg everytime we reconfigure the driver
/////////////////////////////////////////////////////////////////////
void * PendingSetRss; // Pending RSS parameter change
u32 IPv4HdrSize; // Shared 5.2/6.0 encap param
unsigned char * InterruptInfo; // Allocated by us during AddDevice
#if defined(CONFIG_X86)
u32 AddrUpper; // Upper 32 bits of 64-bit register
#endif
//#if SXG_FAILURE_DUMP
// NDIS_EVENT DumpThreadEvent; // syncronize dump thread
// BOOLEAN DumpThreadRunning; // termination flag
// PSXG_DUMP_CMD DumpBuffer; // 68k - Cmd and Buffer
// dma_addr_t PDumpBuffer; // Physical address
//#endif // SXG_FAILURE_DUMP
} adapter_t, *p_adapter_t;
#if SLIC_DUMP_ENABLED
#define SLIC_DUMP_REQUESTED 1
#define SLIC_DUMP_IN_PROGRESS 2
#define SLIC_DUMP_DONE 3
/****************************************************************************
*
* Microcode crash information structure. This
* structure is written out to the card's SRAM when the microcode panic's.
*
****************************************************************************/
typedef struct _slic_crash_info {
ushort cpu_id;
ushort crash_pc;
} slic_crash_info, *p_slic_crash_info;
#define CRASH_INFO_OFFSET 0x155C
#endif
#define UPDATE_STATS(largestat, newstat, oldstat) \
{ \
if ((newstat) < (oldstat)) \
(largestat) += ((newstat) + (0xFFFFFFFF - oldstat + 1)); \
else \
(largestat) += ((newstat) - (oldstat)); \
}
#define UPDATE_STATS_GB(largestat, newstat, oldstat) \
{ \
(largestat) += ((newstat) - (oldstat)); \
}
#define ETHER_EQ_ADDR(_AddrA, _AddrB, _Result) \
{ \
_Result = TRUE; \
if (*(u32 *)(_AddrA) != *(u32 *)(_AddrB)) \
_Result = FALSE; \
if (*(u16 *)(&((_AddrA)[4])) != *(u16 *)(&((_AddrB)[4]))) \
_Result = FALSE; \
}
#define ETHERMAXFRAME 1514
#define JUMBOMAXFRAME 9014
#if defined(CONFIG_X86_64) || defined(CONFIG_IA64)
#define SXG_GET_ADDR_LOW(_addr) (u32)((u64)(_addr) & 0x00000000FFFFFFFF)
#define SXG_GET_ADDR_HIGH(_addr) (u32)(((u64)(_addr) >> 32) & 0x00000000FFFFFFFF)
#else
#define SXG_GET_ADDR_LOW(_addr) (u32)_addr
#define SXG_GET_ADDR_HIGH(_addr) (u32)0
#endif
#define FLUSH TRUE
#define DONT_FLUSH FALSE
#define SIOCSLICDUMPCARD SIOCDEVPRIVATE+9
#define SIOCSLICSETINTAGG SIOCDEVPRIVATE+10
#define SIOCSLICTRACEDUMP SIOCDEVPRIVATE+11
#endif /* __SXG_DRIVER_H__ */

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