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Merge branch 'berlin/soc' into next/soc

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From Sebastian Hesselbarth:
* berlin/soc:
  ARM: add initial support for Marvell Berlin SoCs
  ARM: add Armada 1500-mini and Chromecast device tree files
  ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
  ARM: add Marvell Berlin UART0 lowlevel debug
  ARM: add Marvell Berlin SoCs to multi_v7_defconfig
  ARM: add Marvell Berlin SoC familiy to Marvell doc
  MAINTAINERS: add ARM Marvell Berlin SoC
  irqchip: add DesignWare APB ICTL interrupt controller

Signed-off-by: Kevin Hilman <khilman@linaro.org>
This commit is contained in:
Kevin Hilman 2013-12-20 08:58:25 -08:00
commit 23621799f2
19 changed files with 824 additions and 0 deletions

24
Documentation/arm/Marvell/README
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@ -211,6 +211,30 @@ MMP/MMP2 family (communication processor)
Linux kernel mach directory: arch/arm/mach-mmp
Linux kernel plat directory: arch/arm/plat-pxa
Berlin family (Digital Entertainment)
-------------------------------------
Flavors:
88DE3005, Armada 1500-mini
Design name: BG2CD
Core: ARM Cortex-A9, PL310 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500-mini/
88DE3100, Armada 1500
Design name: BG2
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
Homepage: http://www.marvell.com/digital-entertainment/armada-1500/
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
88DE????
Design name: BG3
Core: ARM Cortex-A15, CA15 integrated L2CC
Homepage: http://www.marvell.com/digital-entertainment/
Directory: arch/arm/mach-berlin
Comments:
* This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs
with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...).
Long-term plans
---------------

24
Documentation/devicetree/bindings/arm/marvell,berlin.txt Normal file
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@ -0,0 +1,24 @@
Marvell Berlin SoC Family Device Tree Bindings
---------------------------------------------------------------
Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500
shall have the following properties:
* Required root node properties:
compatible: must contain "marvell,berlin"
In addition, the above compatible shall be extended with the specific
SoC and board used. Currently known SoC compatibles are:
"marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100),
"marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
"marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????)
"marvell,berlin3" for Marvell Armada ? (BG3, 88DE????)
* Example:
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
...
}

32
Documentation/devicetree/bindings/interrupt-controller/snps,dw-apb-ictl.txt Normal file
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@ -0,0 +1,32 @@
Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
Synopsys DesignWare provides interrupt controller IP for APB known as
dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
APB bus, e.g. Marvell Armada 1500.
Required properties:
- compatible: shall be "snps,dw-apb-ictl"
- reg: physical base address of the controller and length of memory mapped
region starting with ENABLE_LOW register
- interrupt-controller: identifies the node as an interrupt controller
- #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
- interrupts: interrupt reference to primary interrupt controller
- interrupt-parent: (optional) reference specific primary interrupt controller
The interrupt sources map to the corresponding bits in the interrupt
registers, i.e.
- 0 maps to bit 0 of low interrupts,
- 1 maps to bit 1 of low interrupts,
- 32 maps to bit 0 of high interrupts,
- 33 maps to bit 1 of high interrupts,
- (optional) fast interrupts start at 64.
Example:
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};

6
MAINTAINERS
View file

@ -1032,6 +1032,12 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-mvebu/
ARM/Marvell Berlin SoC support
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-berlin/
ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>

2
arch/arm/Kconfig
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@ -911,6 +911,8 @@ source "arch/arm/mach-bcm/Kconfig"
source "arch/arm/mach-bcm2835/Kconfig"
source "arch/arm/mach-berlin/Kconfig"
source "arch/arm/mach-clps711x/Kconfig"
source "arch/arm/mach-cns3xxx/Kconfig"

10
arch/arm/Kconfig.debug
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@ -94,6 +94,14 @@ choice
depends on ARCH_BCM2835
select DEBUG_UART_PL01X
config DEBUG_BERLIN_UART
bool "Marvell Berlin SoC Debug UART"
depends on ARCH_BERLIN
select DEBUG_UART_8250
help
Say Y here if you want kernel low-level debugging support
on Marvell Berlin SoC based platforms.
config DEBUG_CLPS711X_UART1
bool "Kernel low-level debugging messages via UART1"
depends on ARCH_CLPS711X
@ -1011,6 +1019,7 @@ config DEBUG_UART_PHYS
default 0xf1012000 if DEBUG_MVEBU_UART_ALTERNATE
default 0xf1012000 if ARCH_DOVE || ARCH_KIRKWOOD || ARCH_MV78XX0 || \
ARCH_ORION5X
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8b00000 if DEBUG_HI3716_UART
default 0xfcb00000 if DEBUG_HI3620_UART
default 0xfe800000 if ARCH_IOP32X
@ -1036,6 +1045,7 @@ config DEBUG_UART_VIRT
default 0xf2100000 if DEBUG_PXA_UART1
default 0xf4090000 if ARCH_LPC32XX
default 0xf4200000 if ARCH_GEMINI
default 0xf7fc9000 if DEBUG_BERLIN_UART
default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
default 0xfb009000 if DEBUG_REALVIEW_STD_PORT

1
arch/arm/Makefile
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@ -148,6 +148,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
machine-$(CONFIG_ARCH_AT91) += at91
machine-$(CONFIG_ARCH_BCM) += bcm
machine-$(CONFIG_ARCH_BCM2835) += bcm2835
machine-$(CONFIG_ARCH_BERLIN) += berlin
machine-$(CONFIG_ARCH_CLPS711X) += clps711x
machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
machine-$(CONFIG_ARCH_DAVINCI) += davinci

3
arch/arm/boot/dts/Makefile
View file

@ -45,6 +45,9 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
bcm28155-ap.dtb
dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
dtb-$(CONFIG_ARCH_BERLIN) += \
berlin2-sony-nsz-gs7.dtb \
berlin2cd-google-chromecast.dtb
dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
da850-evm.dtb
dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \

29
arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts Normal file
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@ -0,0 +1,29 @@
/*
* Device Tree file for Sony NSZ-GS7
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "berlin2.dtsi"
/ {
model = "Sony NSZ-GS7";
compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1 GB */
};
};
&uart0 { status = "okay"; };

227
arch/arm/boot/dts/berlin2.dtsi Normal file
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@ -0,0 +1,227 @@
/*
* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500 (BG2) SoC";
compatible = "marvell,berlin2", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
cpu@1 {
compatible = "marvell,pj4b";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <1>;
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
l2: l2-cache-controller@ac0000 {
compatible = "marvell,tauros3-cache", "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
status = "disabled";
};
uart2: serial@b000 {
compatible = "snps,dw-apb-uart";
reg = <0xb000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <10>;
clocks = <&smclk>;
status = "disabled";
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

29
arch/arm/boot/dts/berlin2cd-google-chromecast.dts Normal file
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@ -0,0 +1,29 @@
/*
* Device Tree file for Google Chromecast
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
#include "berlin2cd.dtsi"
/ {
model = "Google Chromecast";
compatible = "google,chromecast", "marvell,berlin2cd", "marvell,berlin";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0x00000000 0x20000000>; /* 512 MB */
};
};
&uart0 { status = "okay"; };

210
arch/arm/boot/dts/berlin2cd.dtsi Normal file
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@ -0,0 +1,210 @@
/*
* Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Marvell Armada 1500-mini (BG2CD) SoC";
compatible = "marvell,berlin2cd", "marvell,berlin";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&l2>;
reg = <0>;
};
};
clocks {
smclk: sysmgr-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
cfgclk: cfg-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <75000000>;
};
sysclk: system-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <300000000>;
};
};
soc {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
ranges = <0 0xf7000000 0x1000000>;
l2: l2-cache-controller@ac0000 {
compatible = "arm,pl310-cache";
reg = <0xac0000 0x1000>;
cache-unified;
cache-level = <2>;
};
gic: interrupt-controller@ad1000 {
compatible = "arm,cortex-a9-gic";
reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
interrupt-controller;
#interrupt-cells = <3>;
};
local-timer@ad0600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xad0600 0x20>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysclk>;
};
apb@e80000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xe80000 0x10000>;
interrupt-parent = <&aic>;
timer0: timer@2c00 {
compatible = "snps,dw-apb-timer";
reg = <0x2c00 0x14>;
interrupts = <8>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer1: timer@2c14 {
compatible = "snps,dw-apb-timer";
reg = <0x2c14 0x14>;
interrupts = <9>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "okay";
};
timer2: timer@2c28 {
compatible = "snps,dw-apb-timer";
reg = <0x2c28 0x14>;
interrupts = <10>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer3: timer@2c3c {
compatible = "snps,dw-apb-timer";
reg = <0x2c3c 0x14>;
interrupts = <11>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer4: timer@2c50 {
compatible = "snps,dw-apb-timer";
reg = <0x2c50 0x14>;
interrupts = <12>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer5: timer@2c64 {
compatible = "snps,dw-apb-timer";
reg = <0x2c64 0x14>;
interrupts = <13>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer6: timer@2c78 {
compatible = "snps,dw-apb-timer";
reg = <0x2c78 0x14>;
interrupts = <14>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
timer7: timer@2c8c {
compatible = "snps,dw-apb-timer";
reg = <0x2c8c 0x14>;
interrupts = <15>;
clocks = <&cfgclk>;
clock-names = "timer";
status = "disabled";
};
aic: interrupt-controller@3000 {
compatible = "snps,dw-apb-ictl";
reg = <0x3000 0xc00>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
};
};
apb@fc0000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0xfc0000 0x10000>;
interrupt-parent = <&sic>;
uart0: serial@9000 {
compatible = "snps,dw-apb-uart";
reg = <0x9000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <8>;
clocks = <&smclk>;
status = "disabled";
};
uart1: serial@a000 {
compatible = "snps,dw-apb-uart";
reg = <0xa000 0x100>;
reg-shift = <2>;
reg-io-width = <1>;
interrupts = <9>;
clocks = <&smclk>;
status = "disabled";
};
sic: interrupt-controller@e000 {
compatible = "snps,dw-apb-ictl";
reg = <0xe000 0x400>;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
};
};
};
};

3
arch/arm/configs/multi_v7_defconfig
View file

@ -7,6 +7,9 @@ CONFIG_MACH_ARMADA_370=y
CONFIG_MACH_ARMADA_XP=y
CONFIG_ARCH_BCM=y
CONFIG_ARCH_BCM_MOBILE=y
CONFIG_ARCH_BERLIN=y
CONFIG_MACH_BERLIN_BG2=y
CONFIG_MACH_BERLIN_BG2CD=y
CONFIG_GPIO_PCA953X=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_ARCH_KEYSTONE=y

29
arch/arm/mach-berlin/Kconfig Normal file
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@ -0,0 +1,29 @@
config ARCH_BERLIN
bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
select ARM_GIC
select GENERIC_CLOCKEVENTS
select GENERIC_IRQ_CHIP
select COMMON_CLK
select DW_APB_ICTL
select DW_APB_TIMER_OF
if ARCH_BERLIN
menu "Marvell Berlin SoC variants"
config MACH_BERLIN_BG2
bool "Marvell Armada 1500 (BG2)"
select CACHE_L2X0
select CPU_PJ4B
select HAVE_ARM_TWD if SMP
select HAVE_SMP
config MACH_BERLIN_BG2CD
bool "Marvell Armada 1500-mini (BG2CD)"
select CACHE_L2X0
select CPU_V7
select HAVE_ARM_TWD if SMP
endmenu
endif

1
arch/arm/mach-berlin/Makefile Normal file
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@ -0,0 +1 @@
obj-y += berlin.o

39
arch/arm/mach-berlin/berlin.c Normal file
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@ -0,0 +1,39 @@
/*
* Device Tree support for Marvell Berlin SoCs.
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of_platform.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
static void __init berlin_init_machine(void)
{
/*
* with DT probing for L2CCs, berlin_init_machine can be removed.
* Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
*/
l2x0_of_init(0x70c00000, 0xfeffffff);
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
}
static const char * const berlin_dt_compat[] = {
"marvell,berlin",
NULL,
};
DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
.dt_compat = berlin_dt_compat,
.init_machine = berlin_init_machine,
MACHINE_END

4
drivers/irqchip/Kconfig
View file

@ -30,6 +30,10 @@ config ARM_VIC_NR
The maximum number of VICs available in the system, for
power management.
config DW_APB_ICTL
bool
select IRQ_DOMAIN
config IMGPDC_IRQ
bool
select GENERIC_IRQ_CHIP

1
drivers/irqchip/Makefile
View file

@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
obj-$(CONFIG_METAG) += irq-metag-ext.o
obj-$(CONFIG_METAG_PERFCOUNTER_IRQS) += irq-metag.o
obj-$(CONFIG_ARCH_MOXART) += irq-moxart.o

150
drivers/irqchip/irq-dw-apb-ictl.c Normal file
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@ -0,0 +1,150 @@
/*
* Synopsys DW APB ICTL irqchip driver.
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
*
* based on GPL'ed 2.6 kernel sources
* (c) Marvell International Ltd.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include "irqchip.h"
#define APB_INT_ENABLE_L 0x00
#define APB_INT_ENABLE_H 0x04
#define APB_INT_MASK_L 0x08
#define APB_INT_MASK_H 0x0c
#define APB_INT_FINALSTATUS_L 0x30
#define APB_INT_FINALSTATUS_H 0x34
static void dw_apb_ictl_handler(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_get_chip(irq);
struct irq_chip_generic *gc = irq_get_handler_data(irq);
struct irq_domain *d = gc->private;
u32 stat;
int n;
chained_irq_enter(chip, desc);
for (n = 0; n < gc->num_ct; n++) {
stat = readl_relaxed(gc->reg_base +
APB_INT_FINALSTATUS_L + 4 * n);
while (stat) {
u32 hwirq = ffs(stat) - 1;
generic_handle_irq(irq_find_mapping(d,
gc->irq_base + hwirq + 32 * n));
stat &= ~(1 << hwirq);
}
}
chained_irq_exit(chip, desc);
}
static int __init dw_apb_ictl_init(struct device_node *np,
struct device_node *parent)
{
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
struct resource r;
struct irq_domain *domain;
struct irq_chip_generic *gc;
void __iomem *iobase;
int ret, nrirqs, irq;
u32 reg;
/* Map the parent interrupt for the chained handler */
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) {
pr_err("%s: unable to parse irq\n", np->full_name);
return -EINVAL;
}
ret = of_address_to_resource(np, 0, &r);
if (ret) {
pr_err("%s: unable to get resource\n", np->full_name);
return ret;
}
if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {
pr_err("%s: unable to request mem region\n", np->full_name);
return -ENOMEM;
}
iobase = ioremap(r.start, resource_size(&r));
if (!iobase) {
pr_err("%s: unable to map resource\n", np->full_name);
ret = -ENOMEM;
goto err_release;
}
/*
* DW IP can be configured to allow 2-64 irqs. We can determine
* the number of irqs supported by writing into enable register
* and look for bits not set, as corresponding flip-flops will
* have been removed by sythesis tool.
*/
/* mask and enable all interrupts */
writel(~0, iobase + APB_INT_MASK_L);
writel(~0, iobase + APB_INT_MASK_H);
writel(~0, iobase + APB_INT_ENABLE_L);
writel(~0, iobase + APB_INT_ENABLE_H);
reg = readl(iobase + APB_INT_ENABLE_H);
if (reg)
nrirqs = 32 + fls(reg);
else
nrirqs = fls(readl(iobase + APB_INT_ENABLE_L));
domain = irq_domain_add_linear(np, nrirqs,
&irq_generic_chip_ops, NULL);
if (!domain) {
pr_err("%s: unable to add irq domain\n", np->full_name);
ret = -ENOMEM;
goto err_unmap;
}
ret = irq_alloc_domain_generic_chips(domain, 32, (nrirqs > 32) ? 2 : 1,
np->name, handle_level_irq, clr, 0,
IRQ_GC_INIT_MASK_CACHE);
if (ret) {
pr_err("%s: unable to alloc irq domain gc\n", np->full_name);
goto err_unmap;
}
gc = irq_get_domain_generic_chip(domain, 0);
gc->private = domain;
gc->reg_base = iobase;
gc->chip_types[0].regs.mask = APB_INT_MASK_L;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
if (nrirqs > 32) {
gc->chip_types[1].regs.mask = APB_INT_MASK_H;
gc->chip_types[1].chip.irq_mask = irq_gc_mask_set_bit;
gc->chip_types[1].chip.irq_unmask = irq_gc_mask_clr_bit;
}
irq_set_handler_data(irq, gc);
irq_set_chained_handler(irq, dw_apb_ictl_handler);
return 0;
err_unmap:
iounmap(iobase);
err_release:
release_mem_region(r.start, resource_size(&r));
return ret;
}
IRQCHIP_DECLARE(dw_apb_ictl,
"snps,dw-apb-ictl", dw_apb_ictl_init);