[PATCH] Change maxaligned_in_smp alignemnt macros to internodealigned_in_smp macros
____cacheline_maxaligned_in_smp is currently used to align critical structures and avoid false sharing. It uses per-arch L1_CACHE_SHIFT_MAX and people find L1_CACHE_SHIFT_MAX useless. However, we have been using ____cacheline_maxaligned_in_smp to align structures on the internode cacheline size. As per Andi's suggestion, following patch kills ____cacheline_maxaligned_in_smp and introduces INTERNODE_CACHE_SHIFT, which defaults to L1_CACHE_SHIFT for all arches. Arches needing L3/Internode cacheline alignment can define INTERNODE_CACHE_SHIFT in the arch asm/cache.h. Patch replaces ____cacheline_maxaligned_in_smp with ____cacheline_internodealigned_in_smp With this patch, L1_CACHE_SHIFT_MAX can be killed Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org> Signed-off-by: Shai Fultheim <shai@scalex86.org> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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9 changed files with 24 additions and 15 deletions
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@ -42,5 +42,5 @@ EXPORT_SYMBOL(init_task);
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* per-CPU TSS segments. Threads are completely 'soft' on Linux,
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* per-CPU TSS segments. Threads are completely 'soft' on Linux,
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* no more per-task TSS's.
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* no more per-task TSS's.
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*/
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*/
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DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;
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DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;
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@ -19,7 +19,7 @@
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#include <linux/cpu.h>
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#include <linux/cpu.h>
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#include <linux/delay.h>
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#include <linux/delay.h>
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DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_maxaligned_in_smp;
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DEFINE_PER_CPU(irq_cpustat_t, irq_stat) ____cacheline_internodealigned_in_smp;
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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#ifndef CONFIG_X86_LOCAL_APIC
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#ifndef CONFIG_X86_LOCAL_APIC
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@ -44,6 +44,6 @@ EXPORT_SYMBOL(init_task);
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* section. Since TSS's are completely CPU-local, we want them
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* section. Since TSS's are completely CPU-local, we want them
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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* on exact cacheline boundaries, to eliminate cacheline ping-pong.
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*/
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*/
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DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_maxaligned_in_smp = INIT_TSS;
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DEFINE_PER_CPU(struct tss_struct, init_tss) ____cacheline_internodealigned_in_smp = INIT_TSS;
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#define ALIGN_TO_4K __attribute__((section(".data.init_task")))
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#define ALIGN_TO_4K __attribute__((section(".data.init_task")))
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@ -45,12 +45,21 @@
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#endif /* CONFIG_SMP */
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#endif /* CONFIG_SMP */
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#endif
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#endif
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#if !defined(____cacheline_maxaligned_in_smp)
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/*
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* The maximum alignment needed for some critical structures
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* These could be inter-node cacheline sizes/L3 cacheline
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* size etc. Define this in asm/cache.h for your arch
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*/
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#ifndef INTERNODE_CACHE_SHIFT
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#define INTERNODE_CACHE_SHIFT L1_CACHE_SHIFT
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#endif
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#if !defined(____cacheline_internodealigned_in_smp)
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#if defined(CONFIG_SMP)
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#if defined(CONFIG_SMP)
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#define ____cacheline_maxaligned_in_smp \
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#define ____cacheline_internodealigned_in_smp \
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__attribute__((__aligned__(1 << (L1_CACHE_SHIFT_MAX))))
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__attribute__((__aligned__(1 << (INTERNODE_CACHE_SHIFT))))
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#else
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#else
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#define ____cacheline_maxaligned_in_smp
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#define ____cacheline_internodealigned_in_smp
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#endif
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#endif
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#endif
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#endif
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@ -801,7 +801,7 @@ typedef struct hwif_s {
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unsigned dma;
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unsigned dma;
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void (*led_act)(void *data, int rw);
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void (*led_act)(void *data, int rw);
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} ____cacheline_maxaligned_in_smp ide_hwif_t;
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} ____cacheline_internodealigned_in_smp ide_hwif_t;
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/*
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/*
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* internal ide interrupt handler type
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* internal ide interrupt handler type
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@ -38,7 +38,7 @@ struct pglist_data;
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#if defined(CONFIG_SMP)
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#if defined(CONFIG_SMP)
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struct zone_padding {
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struct zone_padding {
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char x[0];
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char x[0];
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} ____cacheline_maxaligned_in_smp;
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} ____cacheline_internodealigned_in_smp;
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#define ZONE_PADDING(name) struct zone_padding name;
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#define ZONE_PADDING(name) struct zone_padding name;
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#else
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#else
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#define ZONE_PADDING(name)
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#define ZONE_PADDING(name)
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@ -233,7 +233,7 @@ struct zone {
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* rarely used fields:
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* rarely used fields:
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*/
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*/
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char *name;
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char *name;
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} ____cacheline_maxaligned_in_smp;
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} ____cacheline_internodealigned_in_smp;
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/*
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/*
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@ -65,7 +65,7 @@ struct rcu_ctrlblk {
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long cur; /* Current batch number. */
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long cur; /* Current batch number. */
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long completed; /* Number of the last completed batch */
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long completed; /* Number of the last completed batch */
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int next_pending; /* Is the next batch already waiting? */
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int next_pending; /* Is the next batch already waiting? */
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} ____cacheline_maxaligned_in_smp;
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} ____cacheline_internodealigned_in_smp;
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/* Is batch a before batch b ? */
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/* Is batch a before batch b ? */
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static inline int rcu_batch_before(long a, long b)
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static inline int rcu_batch_before(long a, long b)
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@ -61,9 +61,9 @@ struct rcu_state {
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/* for current batch to proceed. */
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/* for current batch to proceed. */
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};
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};
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static struct rcu_state rcu_state ____cacheline_maxaligned_in_smp =
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static struct rcu_state rcu_state ____cacheline_internodealigned_in_smp =
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{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
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{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
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static struct rcu_state rcu_bh_state ____cacheline_maxaligned_in_smp =
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static struct rcu_state rcu_bh_state ____cacheline_internodealigned_in_smp =
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{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
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{.lock = SPIN_LOCK_UNLOCKED, .cpumask = CPU_MASK_NONE };
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DEFINE_PER_CPU(struct rcu_data, rcu_data) = { 0L };
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DEFINE_PER_CPU(struct rcu_data, rcu_data) = { 0L };
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@ -18,10 +18,10 @@
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*/
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*/
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#ifdef CONFIG_SPARSEMEM_EXTREME
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#ifdef CONFIG_SPARSEMEM_EXTREME
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struct mem_section *mem_section[NR_SECTION_ROOTS]
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struct mem_section *mem_section[NR_SECTION_ROOTS]
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____cacheline_maxaligned_in_smp;
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____cacheline_internodealigned_in_smp;
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#else
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#else
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struct mem_section mem_section[NR_SECTION_ROOTS][SECTIONS_PER_ROOT]
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struct mem_section mem_section[NR_SECTION_ROOTS][SECTIONS_PER_ROOT]
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____cacheline_maxaligned_in_smp;
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____cacheline_internodealigned_in_smp;
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#endif
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#endif
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EXPORT_SYMBOL(mem_section);
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EXPORT_SYMBOL(mem_section);
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