x86: Update io_apic.c to use new cpumask API
Impact: cleanup, consolidate patches, use new API Consolidate the following into a single patch to adapt to new sparseirq code in arch/x86/kernel/io_apic.c, add allocation of cpumask_var_t's in domain and old_domain, and reduce further merge conflicts. Only one file (arch/x86/kernel/io_apic.c) is changed in all of these patches. 0006-x86-io_apic-change-irq_cfg-domain-old_domain-to.patch 0007-x86-io_apic-set_desc_affinity.patch 0008-x86-io_apic-send_cleanup_vector.patch 0009-x86-io_apic-eliminate-remaining-cpumask_ts-from-st.patch 0021-x86-final-cleanups-in-io_apic-to-use-new-cpumask-AP.patch Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Signed-off-by: Mike Travis <travis@sgi.com>
This commit is contained in:
Mike Travis
parent
6eeb7c5a99
commit
22f65d31b2
1 changed files with 145 additions and 157 deletions
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@ -136,8 +136,8 @@ static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
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struct irq_cfg {
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struct irq_pin_list *irq_2_pin;
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cpumask_t domain;
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cpumask_t old_domain;
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cpumask_var_t domain;
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cpumask_var_t old_domain;
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unsigned move_cleanup_count;
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u8 vector;
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u8 move_in_progress : 1;
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@ -149,22 +149,22 @@ static struct irq_cfg irq_cfgx[] = {
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#else
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static struct irq_cfg irq_cfgx[NR_IRQS] = {
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#endif
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[0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
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[1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
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[2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
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[3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
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[4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
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[5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
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[6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
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[7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
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[8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
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[9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
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[10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
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[11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
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[12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
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[13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
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[14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
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[15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
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[0] = { .vector = IRQ0_VECTOR, },
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[1] = { .vector = IRQ1_VECTOR, },
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[2] = { .vector = IRQ2_VECTOR, },
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[3] = { .vector = IRQ3_VECTOR, },
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[4] = { .vector = IRQ4_VECTOR, },
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[5] = { .vector = IRQ5_VECTOR, },
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[6] = { .vector = IRQ6_VECTOR, },
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[7] = { .vector = IRQ7_VECTOR, },
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[8] = { .vector = IRQ8_VECTOR, },
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[9] = { .vector = IRQ9_VECTOR, },
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[10] = { .vector = IRQ10_VECTOR, },
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[11] = { .vector = IRQ11_VECTOR, },
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[12] = { .vector = IRQ12_VECTOR, },
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[13] = { .vector = IRQ13_VECTOR, },
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[14] = { .vector = IRQ14_VECTOR, },
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[15] = { .vector = IRQ15_VECTOR, },
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};
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void __init arch_early_irq_init(void)
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@ -180,6 +180,10 @@ void __init arch_early_irq_init(void)
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for (i = 0; i < count; i++) {
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desc = irq_to_desc(i);
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desc->chip_data = &cfg[i];
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alloc_bootmem_cpumask_var(&cfg[i].domain);
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alloc_bootmem_cpumask_var(&cfg[i].old_domain);
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if (i < NR_IRQS_LEGACY)
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cpumask_setall(cfg[i].domain);
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}
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}
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@ -204,6 +208,20 @@ static struct irq_cfg *get_one_free_irq_cfg(int cpu)
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node = cpu_to_node(cpu);
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cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
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if (cfg) {
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/* FIXME: needs alloc_cpumask_var_node() */
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if (!alloc_cpumask_var(&cfg->domain, GFP_ATOMIC)) {
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kfree(cfg);
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cfg = NULL;
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} else if (!alloc_cpumask_var(&cfg->old_domain, GFP_ATOMIC)) {
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free_cpumask_var(cfg->domain);
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kfree(cfg);
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cfg = NULL;
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} else {
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cpumask_clear(cfg->domain);
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cpumask_clear(cfg->old_domain);
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}
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}
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printk(KERN_DEBUG " alloc irq_cfg on cpu %d node %d\n", cpu, node);
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return cfg;
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@ -362,6 +380,26 @@ static void ioapic_mask_entry(int apic, int pin)
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}
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#ifdef CONFIG_SMP
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static void send_cleanup_vector(struct irq_cfg *cfg)
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{
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cpumask_var_t cleanup_mask;
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if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
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unsigned int i;
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cfg->move_cleanup_count = 0;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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cfg->move_cleanup_count++;
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for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
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send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
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} else {
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cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
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cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
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send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
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free_cpumask_var(cleanup_mask);
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}
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cfg->move_in_progress = 0;
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}
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static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
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{
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int apic, pin;
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@ -400,40 +438,52 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
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static int
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assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
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static void set_ioapic_affinity_irq_desc(struct irq_desc *desc,
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const struct cpumask *mask)
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/*
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* Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
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* of that, or returns BAD_APICID and leaves desc->affinity untouched.
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*/
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static unsigned int
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set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned long flags;
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unsigned int dest;
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cpumask_t tmp;
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unsigned int irq;
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if (!cpumask_intersects(mask, cpu_online_mask))
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return;
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return BAD_APICID;
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irq = desc->irq;
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cfg = desc->chip_data;
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if (assign_irq_vector(irq, cfg, mask))
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return;
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return BAD_APICID;
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cpumask_and(&desc->affinity, cfg->domain, mask);
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set_extra_move_desc(desc, mask);
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return cpu_mask_to_apicid_and(&desc->affinity, cpu_online_mask);
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}
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cpumask_and(&tmp, &cfg->domain, mask);
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dest = cpu_mask_to_apicid(&tmp);
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/*
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* Only the high 8 bits are valid.
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*/
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dest = SET_APIC_LOGICAL_ID(dest);
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static void
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set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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unsigned long flags;
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unsigned int dest;
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unsigned int irq;
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irq = desc->irq;
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cfg = desc->chip_data;
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spin_lock_irqsave(&ioapic_lock, flags);
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__target_IO_APIC_irq(irq, dest, cfg);
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cpumask_copy(&desc->affinity, mask);
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dest = set_desc_affinity(desc, mask);
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if (dest != BAD_APICID) {
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/* Only the high 8 bits are valid. */
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dest = SET_APIC_LOGICAL_ID(dest);
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__target_IO_APIC_irq(irq, dest, cfg);
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}
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spin_unlock_irqrestore(&ioapic_lock, flags);
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}
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static void set_ioapic_affinity_irq(unsigned int irq,
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const struct cpumask *mask)
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static void
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set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
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{
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struct irq_desc *desc;
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@ -1117,26 +1167,32 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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*/
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static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
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unsigned int old_vector;
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int cpu;
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cpumask_t tmp_mask;
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int cpu, err;
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cpumask_var_t tmp_mask;
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if ((cfg->move_in_progress) || cfg->move_cleanup_count)
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return -EBUSY;
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if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
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return -ENOMEM;
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old_vector = cfg->vector;
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if (old_vector) {
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cpus_and(tmp_mask, *mask, cpu_online_map);
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cpus_and(tmp_mask, cfg->domain, tmp_mask);
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if (!cpus_empty(tmp_mask))
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cpumask_and(tmp_mask, mask, cpu_online_mask);
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cpumask_and(tmp_mask, cfg->domain, tmp_mask);
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if (!cpumask_empty(tmp_mask)) {
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free_cpumask_var(tmp_mask);
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return 0;
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}
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}
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/* Only try and allocate irqs on cpus that are present */
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for_each_cpu_and(cpu, mask, &cpu_online_map) {
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err = -ENOSPC;
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for_each_cpu_and(cpu, mask, cpu_online_mask) {
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int new_cpu;
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int vector, offset;
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vector_allocation_domain(cpu, &tmp_mask);
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vector_allocation_domain(cpu, tmp_mask);
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vector = current_vector;
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offset = current_offset;
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@ -1156,7 +1212,7 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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if (vector == SYSCALL_VECTOR)
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goto next;
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#endif
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for_each_cpu_and(new_cpu, &tmp_mask, &cpu_online_map)
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for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
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if (per_cpu(vector_irq, new_cpu)[vector] != -1)
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goto next;
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/* Found one! */
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@ -1164,15 +1220,17 @@ __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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current_offset = offset;
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if (old_vector) {
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cfg->move_in_progress = 1;
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cfg->old_domain = cfg->domain;
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cpumask_copy(cfg->old_domain, cfg->domain);
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}
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for_each_cpu_and(new_cpu, &tmp_mask, &cpu_online_map)
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for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
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per_cpu(vector_irq, new_cpu)[vector] = irq;
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cfg->vector = vector;
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cfg->domain = tmp_mask;
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return 0;
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cpumask_copy(cfg->domain, tmp_mask);
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err = 0;
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break;
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}
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return -ENOSPC;
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free_cpumask_var(tmp_mask);
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return err;
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}
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static int
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@ -1189,23 +1247,20 @@ assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
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static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
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{
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cpumask_t mask;
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int cpu, vector;
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BUG_ON(!cfg->vector);
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vector = cfg->vector;
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cpus_and(mask, cfg->domain, cpu_online_map);
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for_each_cpu_mask_nr(cpu, mask)
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for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
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per_cpu(vector_irq, cpu)[vector] = -1;
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cfg->vector = 0;
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cpus_clear(cfg->domain);
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cpumask_clear(cfg->domain);
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if (likely(!cfg->move_in_progress))
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return;
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cpus_and(mask, cfg->old_domain, cpu_online_map);
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for_each_cpu_mask_nr(cpu, mask) {
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for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
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for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
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vector++) {
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if (per_cpu(vector_irq, cpu)[vector] != irq)
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@ -1230,7 +1285,7 @@ void __setup_vector_irq(int cpu)
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if (!desc)
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continue;
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cfg = desc->chip_data;
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if (!cpu_isset(cpu, cfg->domain))
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if (!cpumask_test_cpu(cpu, cfg->domain))
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continue;
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vector = cfg->vector;
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per_cpu(vector_irq, cpu)[vector] = irq;
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@ -1242,7 +1297,7 @@ void __setup_vector_irq(int cpu)
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continue;
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cfg = irq_cfg(irq);
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if (!cpu_isset(cpu, cfg->domain))
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if (!cpumask_test_cpu(cpu, cfg->domain))
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per_cpu(vector_irq, cpu)[vector] = -1;
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}
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}
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@ -1378,18 +1433,17 @@ static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_de
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{
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struct irq_cfg *cfg;
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struct IO_APIC_route_entry entry;
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cpumask_t mask;
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unsigned int dest;
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if (!IO_APIC_IRQ(irq))
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return;
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cfg = desc->chip_data;
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mask = *TARGET_CPUS;
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if (assign_irq_vector(irq, cfg, &mask))
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if (assign_irq_vector(irq, cfg, TARGET_CPUS))
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return;
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cpus_and(mask, cfg->domain, mask);
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dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
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apic_printk(APIC_VERBOSE,KERN_DEBUG
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"IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
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@ -1399,8 +1453,7 @@ static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq, struct irq_de
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if (setup_ioapic_entry(mp_ioapics[apic].mp_apicid, irq, &entry,
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cpu_mask_to_apicid(&mask), trigger, polarity,
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cfg->vector)) {
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dest, trigger, polarity, cfg->vector)) {
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printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
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mp_ioapics[apic].mp_apicid, pin);
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__clear_irq_vector(irq, cfg);
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@ -2122,7 +2175,7 @@ static int ioapic_retrigger_irq(unsigned int irq)
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unsigned long flags;
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spin_lock_irqsave(&vector_lock, flags);
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send_IPI_mask(&cpumask_of_cpu(first_cpu(cfg->domain)), cfg->vector);
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send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
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spin_unlock_irqrestore(&vector_lock, flags);
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return 1;
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@ -2175,15 +2228,13 @@ static void
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migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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{
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struct irq_cfg *cfg;
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cpumask_t tmpmask;
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struct irte irte;
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int modify_ioapic_rte;
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unsigned int dest;
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unsigned long flags;
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unsigned int irq;
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cpus_and(tmpmask, *mask, cpu_online_map);
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if (cpus_empty(tmpmask))
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if (!cpumask_intersects(mask, cpu_online_mask))
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return;
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irq = desc->irq;
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@ -2196,8 +2247,7 @@ migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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set_extra_move_desc(desc, mask);
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cpus_and(tmpmask, cfg->domain, *mask);
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dest = cpu_mask_to_apicid(&tmpmask);
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dest = cpu_mask_to_apicid_and(cfg->domain, mask);
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modify_ioapic_rte = desc->status & IRQ_LEVEL;
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if (modify_ioapic_rte) {
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@ -2214,14 +2264,10 @@ migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
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*/
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modify_irte(irq, &irte);
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if (cfg->move_in_progress) {
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cpus_and(tmpmask, cfg->old_domain, cpu_online_map);
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cfg->move_cleanup_count = cpus_weight(tmpmask);
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send_IPI_mask(&tmpmask, IRQ_MOVE_CLEANUP_VECTOR);
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cfg->move_in_progress = 0;
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}
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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desc->affinity = *mask;
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cpumask_copy(&desc->affinity, mask);
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}
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static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
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@ -2247,7 +2293,7 @@ static int migrate_irq_remapped_level_desc(struct irq_desc *desc)
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ret = 0;
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desc->status &= ~IRQ_MOVE_PENDING;
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cpus_clear(desc->pending_mask);
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cpumask_clear(&desc->pending_mask);
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unmask:
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unmask_IO_APIC_irq_desc(desc);
|
||||
|
|
@ -2333,7 +2379,7 @@ asmlinkage void smp_irq_move_cleanup_interrupt(void)
|
|||
if (!cfg->move_cleanup_count)
|
||||
goto unlock;
|
||||
|
||||
if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
|
||||
if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
|
||||
goto unlock;
|
||||
|
||||
__get_cpu_var(vector_irq)[vector] = -1;
|
||||
|
|
@ -2356,14 +2402,8 @@ static void irq_complete_move(struct irq_desc **descp)
|
|||
|
||||
vector = ~get_irq_regs()->orig_ax;
|
||||
me = smp_processor_id();
|
||||
if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
|
||||
cpumask_t cleanup_mask;
|
||||
|
||||
cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
|
||||
cfg->move_cleanup_count = cpus_weight(cleanup_mask);
|
||||
send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
|
||||
cfg->move_in_progress = 0;
|
||||
}
|
||||
if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
|
||||
send_cleanup_vector(cfg);
|
||||
}
|
||||
#else
|
||||
static inline void irq_complete_move(struct irq_desc **descp) {}
|
||||
|
|
@ -3088,16 +3128,13 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
|
|||
struct irq_cfg *cfg;
|
||||
int err;
|
||||
unsigned dest;
|
||||
cpumask_t tmp;
|
||||
|
||||
cfg = irq_cfg(irq);
|
||||
tmp = *TARGET_CPUS;
|
||||
err = assign_irq_vector(irq, cfg, &tmp);
|
||||
err = assign_irq_vector(irq, cfg, TARGET_CPUS);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
cpus_and(tmp, cfg->domain, tmp);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
|
||||
|
||||
#ifdef CONFIG_INTR_REMAP
|
||||
if (irq_remapped(irq)) {
|
||||
|
|
@ -3157,19 +3194,12 @@ static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
|
|||
struct irq_cfg *cfg;
|
||||
struct msi_msg msg;
|
||||
unsigned int dest;
|
||||
cpumask_t tmp;
|
||||
|
||||
if (!cpumask_intersects(mask, cpu_online_mask))
|
||||
dest = set_desc_affinity(desc, mask);
|
||||
if (dest == BAD_APICID)
|
||||
return;
|
||||
|
||||
cfg = desc->chip_data;
|
||||
if (assign_irq_vector(irq, cfg, mask))
|
||||
return;
|
||||
|
||||
set_extra_move_desc(desc, mask);
|
||||
|
||||
cpumask_and(&tmp, &cfg->domain, mask);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
|
||||
read_msi_msg_desc(desc, &msg);
|
||||
|
||||
|
|
@ -3179,7 +3209,6 @@ static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
|
|||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
|
||||
write_msi_msg_desc(desc, &msg);
|
||||
cpumask_copy(&desc->affinity, mask);
|
||||
}
|
||||
#ifdef CONFIG_INTR_REMAP
|
||||
/*
|
||||
|
|
@ -3192,24 +3221,15 @@ ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
|
|||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
struct irq_cfg *cfg;
|
||||
unsigned int dest;
|
||||
cpumask_t tmp, cleanup_mask;
|
||||
struct irte irte;
|
||||
|
||||
if (!cpumask_intersects(mask, cpu_online_mask))
|
||||
return;
|
||||
|
||||
if (get_irte(irq, &irte))
|
||||
return;
|
||||
|
||||
cfg = desc->chip_data;
|
||||
if (assign_irq_vector(irq, cfg, mask))
|
||||
dest = set_desc_affinity(desc, mask);
|
||||
if (dest == BAD_APICID)
|
||||
return;
|
||||
|
||||
set_extra_move_desc(desc, mask);
|
||||
|
||||
cpumask_and(&tmp, &cfg->domain, mask);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
|
||||
irte.vector = cfg->vector;
|
||||
irte.dest_id = IRTE_DEST(dest);
|
||||
|
||||
|
|
@ -3223,14 +3243,8 @@ ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
|
|||
* at the new destination. So, time to cleanup the previous
|
||||
* vector allocation.
|
||||
*/
|
||||
if (cfg->move_in_progress) {
|
||||
cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
|
||||
cfg->move_cleanup_count = cpus_weight(cleanup_mask);
|
||||
send_IPI_mask(&cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
|
||||
cfg->move_in_progress = 0;
|
||||
}
|
||||
|
||||
cpumask_copy(&desc->affinity, mask);
|
||||
if (cfg->move_in_progress)
|
||||
send_cleanup_vector(cfg);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -3421,25 +3435,18 @@ void arch_teardown_msi_irq(unsigned int irq)
|
|||
|
||||
#ifdef CONFIG_DMAR
|
||||
#ifdef CONFIG_SMP
|
||||
static void dmar_msi_set_affinity(unsigned int irq, const cpumask_t *mask)
|
||||
static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
struct irq_cfg *cfg;
|
||||
struct msi_msg msg;
|
||||
unsigned int dest;
|
||||
cpumask_t tmp;
|
||||
|
||||
if (!cpumask_intersects(mask, cpu_online_mask))
|
||||
dest = set_desc_affinity(desc, mask);
|
||||
if (dest == BAD_APICID)
|
||||
return;
|
||||
|
||||
cfg = desc->chip_data;
|
||||
if (assign_irq_vector(irq, cfg, mask))
|
||||
return;
|
||||
|
||||
set_extra_move_desc(desc, mask);
|
||||
|
||||
cpumask_and(&tmp, &cfg->domain, mask);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
|
||||
dmar_msi_read(irq, &msg);
|
||||
|
||||
|
|
@ -3449,7 +3456,6 @@ static void dmar_msi_set_affinity(unsigned int irq, const cpumask_t *mask)
|
|||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
|
||||
dmar_msi_write(irq, &msg);
|
||||
cpumask_copy(&desc->affinity, mask);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
|
@ -3483,25 +3489,18 @@ int arch_setup_dmar_msi(unsigned int irq)
|
|||
#ifdef CONFIG_HPET_TIMER
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static void hpet_msi_set_affinity(unsigned int irq, const cpumask_t *mask)
|
||||
static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
struct irq_cfg *cfg;
|
||||
struct msi_msg msg;
|
||||
unsigned int dest;
|
||||
cpumask_t tmp;
|
||||
|
||||
if (!cpumask_intersects(mask, cpu_online_mask))
|
||||
dest = set_desc_affinity(desc, mask);
|
||||
if (dest == BAD_APICID)
|
||||
return;
|
||||
|
||||
cfg = desc->chip_data;
|
||||
if (assign_irq_vector(irq, cfg, mask))
|
||||
return;
|
||||
|
||||
set_extra_move_desc(desc, mask);
|
||||
|
||||
cpumask_and(&tmp, &cfg->domain, mask);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
|
||||
hpet_msi_read(irq, &msg);
|
||||
|
||||
|
|
@ -3511,7 +3510,6 @@ static void hpet_msi_set_affinity(unsigned int irq, const cpumask_t *mask)
|
|||
msg.address_lo |= MSI_ADDR_DEST_ID(dest);
|
||||
|
||||
hpet_msi_write(irq, &msg);
|
||||
cpumask_copy(&desc->affinity, mask);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SMP */
|
||||
|
|
@ -3566,27 +3564,19 @@ static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
|
|||
write_ht_irq_msg(irq, &msg);
|
||||
}
|
||||
|
||||
static void set_ht_irq_affinity(unsigned int irq, const cpumask_t *mask)
|
||||
static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
|
||||
{
|
||||
struct irq_desc *desc = irq_to_desc(irq);
|
||||
struct irq_cfg *cfg;
|
||||
unsigned int dest;
|
||||
cpumask_t tmp;
|
||||
|
||||
if (!cpumask_intersects(mask, cpu_online_mask))
|
||||
dest = set_desc_affinity(desc, mask);
|
||||
if (dest == BAD_APICID)
|
||||
return;
|
||||
|
||||
cfg = desc->chip_data;
|
||||
if (assign_irq_vector(irq, cfg, mask))
|
||||
return;
|
||||
|
||||
set_extra_move_desc(desc, mask);
|
||||
|
||||
cpumask_and(&tmp, &cfg->domain, mask);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
|
||||
target_ht_irq(irq, dest, cfg->vector);
|
||||
cpumask_copy(&desc->affinity, mask);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -3606,7 +3596,6 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
|||
{
|
||||
struct irq_cfg *cfg;
|
||||
int err;
|
||||
cpumask_t tmp;
|
||||
|
||||
cfg = irq_cfg(irq);
|
||||
err = assign_irq_vector(irq, cfg, TARGET_CPUS);
|
||||
|
|
@ -3614,8 +3603,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
|||
struct ht_irq_msg msg;
|
||||
unsigned dest;
|
||||
|
||||
cpus_and(tmp, cfg->domain, tmp);
|
||||
dest = cpu_mask_to_apicid(&tmp);
|
||||
dest = cpu_mask_to_apicid_and(cfg->domain, TARGET_CPUS);
|
||||
|
||||
msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
|
||||
|
||||
|
|
@ -3651,7 +3639,7 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
|
|||
int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
|
||||
unsigned long mmr_offset)
|
||||
{
|
||||
const cpumask_t *eligible_cpu = &cpumask_of_cpu(cpu);
|
||||
const struct cpumask *eligible_cpu = cpumask_of(cpu);
|
||||
struct irq_cfg *cfg;
|
||||
int mmr_pnode;
|
||||
unsigned long mmr_value;
|
||||
|
|
@ -3891,7 +3879,7 @@ void __init setup_ioapic_dest(void)
|
|||
int pin, ioapic, irq, irq_entry;
|
||||
struct irq_desc *desc;
|
||||
struct irq_cfg *cfg;
|
||||
const cpumask_t *mask;
|
||||
const struct cpumask *mask;
|
||||
|
||||
if (skip_ioapic_setup == 1)
|
||||
return;
|
||||
|
|
|
|||
Loading…
Reference in a new issue