drm/radeon/kms/evergreen: set the clear state to the blit state
The hw stores a default clear state for registers in the context range that can be initialized when the CP is set up. Set the blit state as the default clear state and use the CLEAR_STATE packet to load the blit state rather than loading it from an IB. This reduces overhead when doing bo moves using the 3D engine. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Alex Deucher
Dave Airlie
parent
c3cceeddf0
commit
2281a378e1
4 changed files with 65 additions and 54 deletions
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@ -32,6 +32,7 @@
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#include "atom.h"
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#include "avivod.h"
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#include "evergreen_reg.h"
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#include "evergreen_blit_shaders.h"
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#define EVERGREEN_PFP_UCODE_SIZE 1120
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#define EVERGREEN_PM4_UCODE_SIZE 1376
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@ -1112,7 +1113,7 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
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static int evergreen_cp_start(struct radeon_device *rdev)
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{
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int r;
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int r, i;
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uint32_t cp_me;
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r = radeon_ring_lock(rdev, 7);
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@ -1132,16 +1133,39 @@ static int evergreen_cp_start(struct radeon_device *rdev)
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cp_me = 0xff;
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WREG32(CP_ME_CNTL, cp_me);
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r = radeon_ring_lock(rdev, 4);
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r = radeon_ring_lock(rdev, evergreen_default_size + 15);
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if (r) {
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DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
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return r;
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}
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/* init some VGT regs */
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
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radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
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radeon_ring_write(rdev, 0xe);
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radeon_ring_write(rdev, 0x10);
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/* setup clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
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for (i = 0; i < evergreen_default_size; i++)
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radeon_ring_write(rdev, evergreen_default_state[i]);
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radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
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radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
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/* set clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(rdev, 0);
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/* SQ_VTX_BASE_VTX_LOC */
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radeon_ring_write(rdev, 0xc0026f00);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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/* Clear consts */
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radeon_ring_write(rdev, 0xc0036f00);
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radeon_ring_write(rdev, 0x00000bc4);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_write(rdev, 0xffffffff);
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radeon_ring_unlock_commit(rdev);
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return 0;
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@ -230,7 +230,7 @@ draw_auto(struct radeon_device *rdev)
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}
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/* emits 20 */
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/* emits 30 */
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static void
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set_default_state(struct radeon_device *rdev)
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{
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@ -243,8 +243,6 @@ set_default_state(struct radeon_device *rdev)
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int num_hs_threads, num_ls_threads;
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int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
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int num_hs_stack_entries, num_ls_stack_entries;
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u64 gpu_addr;
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int dwords;
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switch (rdev->family) {
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case CHIP_CEDAR:
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@ -369,13 +367,9 @@ set_default_state(struct radeon_device *rdev)
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sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
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NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
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/* emit an IB pointing at default state */
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dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
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radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
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radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
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radeon_ring_write(rdev, dwords);
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/* set clear context state */
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radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
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radeon_ring_write(rdev, 0);
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/* disable dyn gprs */
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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@ -396,6 +390,25 @@ set_default_state(struct radeon_device *rdev)
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radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
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radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
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radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
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/* CONTEXT_CONTROL */
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radeon_ring_write(rdev, 0xc0012800);
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radeon_ring_write(rdev, 0x80000000);
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radeon_ring_write(rdev, 0x80000000);
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/* SQ_VTX_BASE_VTX_LOC */
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radeon_ring_write(rdev, 0xc0026f00);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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/* SET_SAMPLER */
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radeon_ring_write(rdev, 0xc0036e00);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000012);
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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}
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static inline uint32_t i2f(uint32_t input)
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@ -426,10 +439,8 @@ static inline uint32_t i2f(uint32_t input)
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int evergreen_blit_init(struct radeon_device *rdev)
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{
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u32 obj_size;
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int r, dwords;
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int r;
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void *ptr;
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u32 packet2s[16];
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int num_packet2s = 0;
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/* pin copy shader into vram if already initialized */
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if (rdev->r600_blit.shader_obj)
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@ -437,17 +448,8 @@ int evergreen_blit_init(struct radeon_device *rdev)
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mutex_init(&rdev->r600_blit.mutex);
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rdev->r600_blit.state_offset = 0;
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rdev->r600_blit.state_len = evergreen_default_size;
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dwords = rdev->r600_blit.state_len;
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while (dwords & 0xf) {
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packet2s[num_packet2s++] = PACKET2(0);
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dwords++;
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}
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obj_size = dwords * 4;
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_blit.state_len = 0;
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obj_size = 0;
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rdev->r600_blit.vs_offset = obj_size;
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obj_size += evergreen_vs_size * 4;
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@ -477,12 +479,6 @@ int evergreen_blit_init(struct radeon_device *rdev)
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return r;
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}
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memcpy_toio(ptr + rdev->r600_blit.state_offset,
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evergreen_default_state, rdev->r600_blit.state_len * 4);
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if (num_packet2s)
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memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
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packet2s, num_packet2s * 4);
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memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
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memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
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radeon_bo_kunmap(rdev->r600_blit.shader_obj);
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@ -566,7 +562,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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/* calculate number of loops correctly */
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 36; /* shaders + def state */
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ring_size += 46; /* shaders + def state */
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ring_size += 10; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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ring_size += 10; /* fence emit for done copy */
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@ -574,7 +570,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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if (r)
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return r;
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set_default_state(rdev); /* 20 */
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set_default_state(rdev); /* 30 */
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set_shaders(rdev); /* 16 */
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return 0;
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}
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@ -39,10 +39,6 @@
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const u32 evergreen_default_state[] =
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{
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0xc0012800, /* CONTEXT_CONTROL */
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0x80000000,
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0x80000000,
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0xc0016900,
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0x0000023b,
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0x00000000, /* SQ_LDS_ALLOC_PS */
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@ -63,17 +59,11 @@ const u32 evergreen_default_state[] =
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0x00000000,
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0x00000000,
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0xc0026f00,
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0x00000000,
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0x00000000, /* SQ_VTX_BASE_VTX_LOC */
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0x00000000,
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0xc0026900,
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0x00000010,
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0x00000000, /* DB_Z_INFO */
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0x00000000, /* DB_STENCIL_INFO */
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0xc0016900,
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0x00000200,
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0x00000000, /* DB_DEPTH_CONTROL */
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@ -303,11 +293,10 @@ const u32 evergreen_default_state[] =
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0x00000000, /* */
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0x00000000, /* */
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0xc0036e00, /* SET_SAMPLER */
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0x00000000,
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0x00000012,
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0x00000000,
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0x00000000,
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0xc0026900,
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0x00000316,
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0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
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0x00000010, /* */
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};
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const u32 evergreen_vs[] =
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@ -658,6 +658,8 @@
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_PREAMBLE_CNTL 0x4A
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# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
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# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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#define PACKET3_RB_OFFSET 0x4B
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#define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
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#define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
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