MIPS: KVM: asm/kvm_host.h: Clean up whitespace
The whitespace in asm/kvm_host.h is quite inconsistent in places. Clean up the whole file to use tabs more consistently. When you use the --ignore-space-change argument to git diff this patch only changes line wrapping in TLB_IS_GLOBAL and TLB_IS_VALID macros. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Gleb Natapov <gleb@kernel.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Sanjay Lal <sanjayl@kymasys.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
James Hogan
Paolo Bonzini
parent
684a0b719d
commit
2202794548
1 changed files with 207 additions and 204 deletions
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@ -30,16 +30,16 @@
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/* Special address that contains the comm page, used for reducing # of traps */
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#define KVM_GUEST_COMMPAGE_ADDR 0x0
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#define KVM_GUEST_COMMPAGE_ADDR 0x0
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#define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
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((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
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#define KVM_GUEST_KUSEG 0x00000000UL
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#define KVM_GUEST_KSEG0 0x40000000UL
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#define KVM_GUEST_KSEG23 0x60000000UL
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#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
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#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
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#define KVM_GUEST_KUSEG 0x00000000UL
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#define KVM_GUEST_KSEG0 0x40000000UL
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#define KVM_GUEST_KSEG23 0x60000000UL
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#define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
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#define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
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#define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
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#define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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@ -52,17 +52,17 @@
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#define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
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#define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
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#define KVM_INVALID_PAGE 0xdeadbeef
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#define KVM_INVALID_INST 0xdeadbeef
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#define KVM_INVALID_ADDR 0xdeadbeef
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#define KVM_INVALID_PAGE 0xdeadbeef
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#define KVM_INVALID_INST 0xdeadbeef
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#define KVM_INVALID_ADDR 0xdeadbeef
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#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
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#define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
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#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
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#define MS_TO_NS(x) (x * 1E6L)
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#define GUEST_TICKS_PER_JIFFY (40000000/HZ)
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#define MS_TO_NS(x) (x * 1E6L)
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#define CAUSEB_DC 27
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#define CAUSEF_DC (_ULCAST_(1) << 27)
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#define CAUSEB_DC 27
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#define CAUSEF_DC (_ULCAST_(1) << 27)
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struct kvm;
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struct kvm_run;
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@ -126,8 +126,8 @@ struct kvm_arch {
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int commpage_tlb;
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};
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#define N_MIPS_COPROC_REGS 32
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#define N_MIPS_COPROC_SEL 8
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#define N_MIPS_COPROC_REGS 32
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#define N_MIPS_COPROC_SEL 8
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struct mips_coproc {
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unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
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@ -139,124 +139,124 @@ struct mips_coproc {
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/*
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* Coprocessor 0 register names
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*/
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#define MIPS_CP0_TLB_INDEX 0
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#define MIPS_CP0_TLB_RANDOM 1
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#define MIPS_CP0_TLB_LOW 2
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#define MIPS_CP0_TLB_LO0 2
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#define MIPS_CP0_TLB_LO1 3
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#define MIPS_CP0_TLB_CONTEXT 4
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#define MIPS_CP0_TLB_PG_MASK 5
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#define MIPS_CP0_TLB_WIRED 6
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#define MIPS_CP0_HWRENA 7
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#define MIPS_CP0_BAD_VADDR 8
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#define MIPS_CP0_COUNT 9
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#define MIPS_CP0_TLB_HI 10
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#define MIPS_CP0_COMPARE 11
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#define MIPS_CP0_STATUS 12
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#define MIPS_CP0_CAUSE 13
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#define MIPS_CP0_EXC_PC 14
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#define MIPS_CP0_PRID 15
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#define MIPS_CP0_CONFIG 16
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#define MIPS_CP0_LLADDR 17
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#define MIPS_CP0_WATCH_LO 18
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#define MIPS_CP0_WATCH_HI 19
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#define MIPS_CP0_TLB_XCONTEXT 20
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#define MIPS_CP0_ECC 26
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#define MIPS_CP0_CACHE_ERR 27
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#define MIPS_CP0_TAG_LO 28
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#define MIPS_CP0_TAG_HI 29
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#define MIPS_CP0_ERROR_PC 30
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#define MIPS_CP0_DEBUG 23
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#define MIPS_CP0_DEPC 24
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#define MIPS_CP0_PERFCNT 25
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#define MIPS_CP0_ERRCTL 26
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#define MIPS_CP0_DATA_LO 28
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#define MIPS_CP0_DATA_HI 29
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#define MIPS_CP0_DESAVE 31
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#define MIPS_CP0_TLB_INDEX 0
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#define MIPS_CP0_TLB_RANDOM 1
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#define MIPS_CP0_TLB_LOW 2
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#define MIPS_CP0_TLB_LO0 2
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#define MIPS_CP0_TLB_LO1 3
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#define MIPS_CP0_TLB_CONTEXT 4
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#define MIPS_CP0_TLB_PG_MASK 5
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#define MIPS_CP0_TLB_WIRED 6
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#define MIPS_CP0_HWRENA 7
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#define MIPS_CP0_BAD_VADDR 8
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#define MIPS_CP0_COUNT 9
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#define MIPS_CP0_TLB_HI 10
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#define MIPS_CP0_COMPARE 11
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#define MIPS_CP0_STATUS 12
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#define MIPS_CP0_CAUSE 13
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#define MIPS_CP0_EXC_PC 14
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#define MIPS_CP0_PRID 15
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#define MIPS_CP0_CONFIG 16
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#define MIPS_CP0_LLADDR 17
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#define MIPS_CP0_WATCH_LO 18
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#define MIPS_CP0_WATCH_HI 19
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#define MIPS_CP0_TLB_XCONTEXT 20
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#define MIPS_CP0_ECC 26
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#define MIPS_CP0_CACHE_ERR 27
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#define MIPS_CP0_TAG_LO 28
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#define MIPS_CP0_TAG_HI 29
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#define MIPS_CP0_ERROR_PC 30
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#define MIPS_CP0_DEBUG 23
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#define MIPS_CP0_DEPC 24
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#define MIPS_CP0_PERFCNT 25
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#define MIPS_CP0_ERRCTL 26
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#define MIPS_CP0_DATA_LO 28
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#define MIPS_CP0_DATA_HI 29
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#define MIPS_CP0_DESAVE 31
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#define MIPS_CP0_CONFIG_SEL 0
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#define MIPS_CP0_CONFIG1_SEL 1
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#define MIPS_CP0_CONFIG2_SEL 2
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#define MIPS_CP0_CONFIG3_SEL 3
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#define MIPS_CP0_CONFIG_SEL 0
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#define MIPS_CP0_CONFIG1_SEL 1
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#define MIPS_CP0_CONFIG2_SEL 2
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#define MIPS_CP0_CONFIG3_SEL 3
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/* Config0 register bits */
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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#define CP0C0_AR 10
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#define CP0C0_MT 7
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#define CP0C0_VI 3
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#define CP0C0_K0 0
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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#define CP0C0_AR 10
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#define CP0C0_MT 7
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#define CP0C0_VI 3
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#define CP0C0_K0 0
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/* Config1 register bits */
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#define CP0C1_M 31
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#define CP0C1_MMU 25
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#define CP0C1_IS 22
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#define CP0C1_IL 19
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#define CP0C1_IA 16
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#define CP0C1_DS 13
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#define CP0C1_DL 10
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#define CP0C1_DA 7
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#define CP0C1_C2 6
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#define CP0C1_MD 5
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#define CP0C1_PC 4
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#define CP0C1_WR 3
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#define CP0C1_CA 2
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#define CP0C1_EP 1
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#define CP0C1_FP 0
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#define CP0C1_M 31
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#define CP0C1_MMU 25
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#define CP0C1_IS 22
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#define CP0C1_IL 19
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#define CP0C1_IA 16
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#define CP0C1_DS 13
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#define CP0C1_DL 10
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#define CP0C1_DA 7
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#define CP0C1_C2 6
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#define CP0C1_MD 5
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#define CP0C1_PC 4
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#define CP0C1_WR 3
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#define CP0C1_CA 2
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#define CP0C1_EP 1
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#define CP0C1_FP 0
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/* Config2 Register bits */
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#define CP0C2_M 31
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#define CP0C2_TU 28
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#define CP0C2_TS 24
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#define CP0C2_TL 20
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#define CP0C2_TA 16
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#define CP0C2_SU 12
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#define CP0C2_SS 8
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#define CP0C2_SL 4
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#define CP0C2_SA 0
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#define CP0C2_M 31
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#define CP0C2_TU 28
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#define CP0C2_TS 24
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#define CP0C2_TL 20
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#define CP0C2_TA 16
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#define CP0C2_SU 12
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#define CP0C2_SS 8
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#define CP0C2_SL 4
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#define CP0C2_SA 0
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/* Config3 Register bits */
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#define CP0C3_M 31
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#define CP0C3_ISA_ON_EXC 16
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#define CP0C3_ULRI 13
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#define CP0C3_DSPP 10
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#define CP0C3_LPA 7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP 4
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#define CP0C3_MT 2
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#define CP0C3_SM 1
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#define CP0C3_TL 0
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#define CP0C3_M 31
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#define CP0C3_ISA_ON_EXC 16
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#define CP0C3_ULRI 13
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#define CP0C3_DSPP 10
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#define CP0C3_LPA 7
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#define CP0C3_VEIC 6
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#define CP0C3_VInt 5
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#define CP0C3_SP 4
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#define CP0C3_MT 2
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#define CP0C3_SM 1
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#define CP0C3_TL 0
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/* Have config1, Cacheable, noncoherent, write-back, write allocate*/
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#define MIPS_CONFIG0 \
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#define MIPS_CONFIG0 \
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((1 << CP0C0_M) | (0x3 << CP0C0_K0))
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/* Have config2, no coprocessor2 attached, no MDMX support attached,
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no performance counters, watch registers present,
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no code compression, EJTAG present, no FPU, no watch registers */
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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#define MIPS_CONFIG1 \
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((1 << CP0C1_M) | \
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(0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
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(0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
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(0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2 \
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#define MIPS_CONFIG2 \
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((1 << CP0C2_M))
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/* No config4, no DSP ASE, no large physaddr (PABITS),
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no external interrupt controller, no vectored interrupts,
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no 1kb pages, no SmartMIPS ASE, no trace logic */
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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#define MIPS_CONFIG3 \
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
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(0 << CP0C3_SM) | (0 << CP0C3_TL))
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/* MMU types, the first four entries have the same layout as the
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@ -274,36 +274,36 @@ enum mips_mmu_types {
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/*
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* Trap codes
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*/
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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#define T_INT 0 /* Interrupt pending */
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#define T_TLB_MOD 1 /* TLB modified fault */
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#define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
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#define T_TLB_ST_MISS 3 /* TLB miss on a store */
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#define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
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#define T_ADDR_ERR_ST 5 /* Address error on a store */
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#define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
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#define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
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#define T_SYSCALL 8 /* System call */
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#define T_BREAK 9 /* Breakpoint */
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#define T_RES_INST 10 /* Reserved instruction exception */
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#define T_COP_UNUSABLE 11 /* Coprocessor unusable */
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#define T_OVFLOW 12 /* Arithmetic overflow */
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/*
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* Trap definitions added for r4000 port.
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*/
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency exception */
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#define T_FPE 15 /* Floating point exception */
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#define T_WATCH 23 /* Watch address reference */
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#define T_VCED 31 /* Virtual coherency data */
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#define T_TRAP 13 /* Trap instruction */
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#define T_VCEI 14 /* Virtual coherency exception */
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#define T_FPE 15 /* Floating point exception */
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#define T_WATCH 23 /* Watch address reference */
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#define T_VCED 31 /* Virtual coherency data */
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/* Resume Flags */
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#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
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#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
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#define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
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#define RESUME_FLAG_HOST (1<<1) /* Resume host? */
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#define RESUME_GUEST 0
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#define RESUME_GUEST_DR RESUME_FLAG_DR
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#define RESUME_HOST RESUME_FLAG_HOST
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#define RESUME_GUEST 0
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#define RESUME_GUEST_DR RESUME_FLAG_DR
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#define RESUME_HOST RESUME_FLAG_HOST
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enum emulation_result {
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EMULATE_DONE, /* no further processing */
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@ -313,24 +313,27 @@ enum emulation_result {
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EMULATE_PRIV_FAIL,
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};
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#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
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#define MIPS3_PG_V 0x00000002 /* Valid */
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#define MIPS3_PG_NV 0x00000000
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#define MIPS3_PG_D 0x00000004 /* Dirty */
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#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
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#define MIPS3_PG_V 0x00000002 /* Valid */
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#define MIPS3_PG_NV 0x00000000
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#define MIPS3_PG_D 0x00000004 /* Dirty */
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#define mips3_paddr_to_tlbpfn(x) \
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(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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(((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
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#define mips3_tlbpfn_to_paddr(x) \
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((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
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((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
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#define MIPS3_PG_SHIFT 6
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#define MIPS3_PG_FRAME 0x3fffffc0
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#define MIPS3_PG_SHIFT 6
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#define MIPS3_PG_FRAME 0x3fffffc0
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#define VPN2_MASK 0xffffe000
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#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
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#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
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#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
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#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
|
||||
#define VPN2_MASK 0xffffe000
|
||||
#define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && \
|
||||
((x).tlb_lo1 & MIPS3_PG_G))
|
||||
#define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
|
||||
#define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
|
||||
#define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) \
|
||||
? ((x).tlb_lo1 & MIPS3_PG_V) \
|
||||
: ((x).tlb_lo0 & MIPS3_PG_V))
|
||||
|
||||
struct kvm_mips_tlb {
|
||||
long tlb_mask;
|
||||
|
|
@ -339,7 +342,7 @@ struct kvm_mips_tlb {
|
|||
long tlb_lo1;
|
||||
};
|
||||
|
||||
#define KVM_MIPS_GUEST_TLB_SIZE 64
|
||||
#define KVM_MIPS_GUEST_TLB_SIZE 64
|
||||
struct kvm_vcpu_arch {
|
||||
void *host_ebase, *guest_ebase;
|
||||
unsigned long host_stack;
|
||||
|
|
@ -400,65 +403,65 @@ struct kvm_vcpu_arch {
|
|||
};
|
||||
|
||||
|
||||
#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
|
||||
#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
|
||||
#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
|
||||
#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
|
||||
#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
|
||||
#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
|
||||
#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
|
||||
#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
|
||||
#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
|
||||
#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
|
||||
#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
|
||||
#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
|
||||
#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
|
||||
#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
|
||||
#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
|
||||
#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
|
||||
#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
|
||||
#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
|
||||
#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
|
||||
#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
|
||||
#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
|
||||
#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
|
||||
#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
|
||||
#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
|
||||
#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
|
||||
#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
|
||||
#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
|
||||
#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
|
||||
#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
|
||||
#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
|
||||
#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
|
||||
#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
|
||||
#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
|
||||
#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
|
||||
#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
|
||||
#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
|
||||
#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
|
||||
#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
|
||||
#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
|
||||
#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
|
||||
#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
|
||||
#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
|
||||
#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
|
||||
#define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
|
||||
#define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
|
||||
#define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
|
||||
#define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
|
||||
#define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
|
||||
#define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
|
||||
#define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
|
||||
#define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
|
||||
#define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
|
||||
#define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
|
||||
#define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
|
||||
#define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
|
||||
#define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
|
||||
#define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
|
||||
#define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
|
||||
#define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
|
||||
#define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
|
||||
#define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
|
||||
#define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
|
||||
#define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
|
||||
#define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
|
||||
#define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
|
||||
#define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
|
||||
#define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
|
||||
#define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
|
||||
#define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
|
||||
#define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
|
||||
#define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
|
||||
#define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
|
||||
#define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
|
||||
#define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
|
||||
#define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
|
||||
#define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
|
||||
#define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
|
||||
#define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
|
||||
#define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
|
||||
#define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
|
||||
#define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
|
||||
#define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
|
||||
#define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
|
||||
#define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
|
||||
#define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
|
||||
#define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
|
||||
|
||||
#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
|
||||
#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
|
||||
#define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
|
||||
#define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
|
||||
#define kvm_change_c0_guest_cause(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_cause(cop0, change); \
|
||||
kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
|
||||
#define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
|
||||
#define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
|
||||
#define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
|
||||
#define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
|
||||
#define kvm_change_c0_guest_cause(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_cause(cop0, change); \
|
||||
kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
|
||||
}
|
||||
#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
|
||||
#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
|
||||
#define kvm_change_c0_guest_ebase(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_ebase(cop0, change); \
|
||||
kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
|
||||
#define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
|
||||
#define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
|
||||
#define kvm_change_c0_guest_ebase(cop0, change, val) \
|
||||
{ \
|
||||
kvm_clear_c0_guest_ebase(cop0, change); \
|
||||
kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue