spi: omap2-mcspi: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode. Need to use endian neutral functions to read/write h/w registers. I.e instead of __raw_read[lw] and __raw_write[lw] functions code need to use read[lw]_relaxed and write[lw]_relaxed functions. If the first simply reads/writes register, the second will byteswap it if host operates in BE mode. Changes are trivial sed like replacement of __raw_xxx functions with xxx_relaxed variant. Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org> Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org> Signed-off-by: Mark Brown <broonie@linaro.org>
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6ce4eac1f6
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21b2ce5e99
1 changed files with 19 additions and 19 deletions
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@ -157,14 +157,14 @@ static inline void mcspi_write_reg(struct spi_master *master,
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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__raw_writel(val, mcspi->base + idx);
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writel_relaxed(val, mcspi->base + idx);
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}
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static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
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{
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struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
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return __raw_readl(mcspi->base + idx);
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return readl_relaxed(mcspi->base + idx);
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}
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static inline void mcspi_write_cs_reg(const struct spi_device *spi,
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@ -172,14 +172,14 @@ static inline void mcspi_write_cs_reg(const struct spi_device *spi,
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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__raw_writel(val, cs->base + idx);
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writel_relaxed(val, cs->base + idx);
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}
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static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
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{
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struct omap2_mcspi_cs *cs = spi->controller_state;
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return __raw_readl(cs->base + idx);
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return readl_relaxed(cs->base + idx);
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}
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static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
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@ -338,7 +338,7 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
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mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE, ctx->wakeupenable);
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list_for_each_entry(cs, &ctx->cs, node)
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__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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}
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static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
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@ -346,9 +346,9 @@ static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(1000);
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while (!(__raw_readl(reg) & bit)) {
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while (!(readl_relaxed(reg) & bit)) {
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if (time_after(jiffies, timeout)) {
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if (!(__raw_readl(reg) & bit))
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if (!(readl_relaxed(reg) & bit))
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return -ETIMEDOUT;
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else
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return 0;
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@ -675,7 +675,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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}
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dev_vdbg(&spi->dev, "write-%d %02x\n",
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word_len, *tx);
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__raw_writel(*tx++, tx_reg);
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writel_relaxed(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -687,7 +687,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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if (c == 1 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %02x\n",
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word_len, *(rx - 1));
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -701,7 +701,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %02x\n",
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word_len, *(rx - 1));
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}
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@ -722,7 +722,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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}
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dev_vdbg(&spi->dev, "write-%d %04x\n",
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word_len, *tx);
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__raw_writel(*tx++, tx_reg);
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writel_relaxed(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -734,7 +734,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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if (c == 2 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %04x\n",
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word_len, *(rx - 1));
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -748,7 +748,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %04x\n",
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word_len, *(rx - 1));
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}
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@ -769,7 +769,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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}
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dev_vdbg(&spi->dev, "write-%d %08x\n",
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word_len, *tx);
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__raw_writel(*tx++, tx_reg);
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writel_relaxed(*tx++, tx_reg);
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}
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if (rx != NULL) {
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -781,7 +781,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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if (c == 4 && tx == NULL &&
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(l & OMAP2_MCSPI_CHCONF_TURBO)) {
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omap2_mcspi_set_enable(spi, 0);
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %08x\n",
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word_len, *(rx - 1));
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if (mcspi_wait_for_reg_bit(chstat_reg,
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@ -795,7 +795,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
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omap2_mcspi_set_enable(spi, 0);
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}
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*rx++ = __raw_readl(rx_reg);
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*rx++ = readl_relaxed(rx_reg);
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dev_vdbg(&spi->dev, "read-%d %08x\n",
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word_len, *(rx - 1));
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}
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@ -1107,7 +1107,7 @@ static void omap2_mcspi_work(struct omap2_mcspi *mcspi, struct spi_message *m)
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/* RX_ONLY mode needs dummy data in TX reg */
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if (t->tx_buf == NULL)
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__raw_writel(0, cs->base
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writel_relaxed(0, cs->base
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+ OMAP2_MCSPI_TX0);
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if ((mcspi_dma->dma_rx && mcspi_dma->dma_tx) &&
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@ -1470,9 +1470,9 @@ static int omap2_mcspi_resume(struct device *dev)
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* change in account.
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*/
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cs->chconf0 |= OMAP2_MCSPI_CHCONF_FORCE;
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__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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cs->chconf0 &= ~OMAP2_MCSPI_CHCONF_FORCE;
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__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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writel_relaxed(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
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}
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}
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pm_runtime_mark_last_busy(mcspi->dev);
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