m68k: remove the dead PCI code
This patch removes the no longer used m68k PCI code. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Adrian Bunk
Linus Torvalds
parent
29c8a24672
commit
2171a19a24
6 changed files with 7 additions and 630 deletions
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@ -122,10 +122,6 @@ config ATARI
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this kernel on an Atari, say Y here and browse the material
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available in <file:Documentation/m68k>; otherwise say N.
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config PCI
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bool
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help
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config MAC
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bool "Macintosh support"
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select MMU_MOTOROLA if MMU
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@ -14,5 +14,4 @@ obj-y := entry.o process.o traps.o ints.o signal.o ptrace.o module.o \
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devres-y = ../../../kernel/irq/devres.o
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obj-$(CONFIG_PCI) += bios32.o
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obj-y$(CONFIG_MMU_SUN3) += dma.o # no, it's not a typo
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@ -1,516 +0,0 @@
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/*
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* bios32.c - PCI BIOS functions for m68k systems.
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*
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* Written by Wout Klaren.
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*
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* Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#if 0
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# define DBG_DEVS(args) printk args
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#else
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# define DBG_DEVS(args)
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#endif
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#ifdef CONFIG_PCI
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/*
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* PCI support for Linux/m68k. Currently only the Hades is supported.
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*
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* The support for PCI bridges in the DEC Alpha version has
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* been removed in this version.
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*/
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/uaccess.h>
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#define KB 1024
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#define MB (1024*KB)
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#define GB (1024*MB)
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#define MAJOR_REV 0
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#define MINOR_REV 5
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/*
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* Align VAL to ALIGN, which must be a power of two.
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*/
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#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
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/*
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* Offsets relative to the I/O and memory base addresses from where resources
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* are allocated.
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*/
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#define IO_ALLOC_OFFSET 0x00004000
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#define MEM_ALLOC_OFFSET 0x04000000
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/*
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* Declarations of hardware specific initialisation functions.
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*/
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extern struct pci_bus_info *init_hades_pci(void);
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/*
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* Bus info structure of the PCI bus. A pointer to this structure is
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* put in the sysdata member of the pci_bus structure.
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*/
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static struct pci_bus_info *bus_info;
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static int pci_modify = 1; /* If set, layout the PCI bus ourself. */
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static int skip_vga; /* If set do not modify base addresses
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of vga cards.*/
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static int disable_pci_burst; /* If set do not allow PCI bursts. */
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static unsigned int io_base;
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static unsigned int mem_base;
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/*
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* static void disable_dev(struct pci_dev *dev)
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*
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* Disable PCI device DEV so that it does not respond to I/O or memory
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* accesses.
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*
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* Parameters:
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*
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* dev - device to disable.
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*/
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static void __init disable_dev(struct pci_dev *dev)
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{
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unsigned short cmd;
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if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
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(dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
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(dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
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return;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
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pci_write_config_word(dev, PCI_COMMAND, cmd);
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}
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/*
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* static void layout_dev(struct pci_dev *dev)
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*
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* Layout memory and I/O for a device.
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*
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* Parameters:
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*
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* device - device to layout memory and I/O for.
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*/
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static void __init layout_dev(struct pci_dev *dev)
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{
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unsigned short cmd;
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unsigned int base, mask, size, reg;
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unsigned int alignto;
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int i;
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/*
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* Skip video cards if requested.
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*/
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if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
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(dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
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(dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
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return;
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pci_read_config_word(dev, PCI_COMMAND, &cmd);
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for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
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{
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/*
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* Figure out how much space and of what type this
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* device wants.
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*/
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pci_write_config_dword(dev, reg, 0xffffffff);
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pci_read_config_dword(dev, reg, &base);
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if (!base)
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{
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/* this base-address register is unused */
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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continue;
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}
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/*
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* We've read the base address register back after
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* writing all ones and so now we must decode it.
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*/
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if (base & PCI_BASE_ADDRESS_SPACE_IO)
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{
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/*
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* I/O space base address register.
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*/
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cmd |= PCI_COMMAND_IO;
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base &= PCI_BASE_ADDRESS_IO_MASK;
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mask = (~base << 1) | 0x1;
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size = (mask & base) & 0xffffffff;
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/*
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* Align to multiple of size of minimum base.
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*/
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alignto = max_t(unsigned int, 0x040, size);
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base = ALIGN(io_base, alignto);
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io_base = base + size;
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pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
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dev->resource[i].start = base;
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dev->resource[i].end = dev->resource[i].start + size - 1;
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dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
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DBG_DEVS(("layout_dev: IO address: %lX\n", base));
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}
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else
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{
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unsigned int type;
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/*
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* Memory space base address register.
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*/
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cmd |= PCI_COMMAND_MEMORY;
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type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
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base &= PCI_BASE_ADDRESS_MEM_MASK;
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mask = (~base << 1) | 0x1;
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size = (mask & base) & 0xffffffff;
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switch (type)
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{
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case PCI_BASE_ADDRESS_MEM_TYPE_32:
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case PCI_BASE_ADDRESS_MEM_TYPE_64:
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break;
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case PCI_BASE_ADDRESS_MEM_TYPE_1M:
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printk("bios32 WARNING: slot %d, function %d "
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"requests memory below 1MB---don't "
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"know how to do that.\n",
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PCI_SLOT(dev->devfn),
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PCI_FUNC(dev->devfn));
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continue;
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}
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/*
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* Align to multiple of size of minimum base.
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*/
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alignto = max_t(unsigned int, 0x1000, size);
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base = ALIGN(mem_base, alignto);
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mem_base = base + size;
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pci_write_config_dword(dev, reg, base);
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dev->resource[i].start = base;
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dev->resource[i].end = dev->resource[i].start + size - 1;
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dev->resource[i].flags = IORESOURCE_MEM;
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if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
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{
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/*
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* 64-bit address, set the highest 32 bits
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* to zero.
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*/
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reg += 4;
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pci_write_config_dword(dev, reg, 0);
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i++;
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dev->resource[i].start = 0;
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dev->resource[i].end = 0;
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dev->resource[i].flags = 0;
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}
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}
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}
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/*
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* Enable device:
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*/
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if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
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dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
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dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
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dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
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{
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/*
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* All of these (may) have I/O scattered all around
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* and may not use i/o-base address registers at all.
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* So we just have to always enable I/O to these
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* devices.
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*/
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cmd |= PCI_COMMAND_IO;
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}
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pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
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if (bus_info != NULL)
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bus_info->conf_device(dev); /* Machine dependent configuration. */
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DBG_DEVS(("layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
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dev->bus->number, PCI_SLOT(dev->devfn), dev->vendor, dev->device, dev->class));
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}
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/*
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* static void layout_bus(struct pci_bus *bus)
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*
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* Layout memory and I/O for all devices on the given bus.
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*
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* Parameters:
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*
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* bus - bus.
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*/
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static void __init layout_bus(struct pci_bus *bus)
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{
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unsigned int bio, bmem;
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struct pci_dev *dev;
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DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
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if (!bus->devices && !bus->children)
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return;
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/*
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* Align the current bases on appropriate boundaries (4K for
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* IO and 1MB for memory).
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*/
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bio = io_base = ALIGN(io_base, 4*KB);
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bmem = mem_base = ALIGN(mem_base, 1*MB);
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/*
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* PCI devices might have been setup by a PCI BIOS emulation
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* running under TOS. In these cases there is a
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* window during which two devices may have an overlapping
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* address range. To avoid this causing trouble, we first
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* turn off the I/O and memory address decoders for all PCI
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* devices. They'll be re-enabled only once all address
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* decoders are programmed consistently.
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*/
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DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
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for (dev = bus->devices; dev; dev = dev->sibling)
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{
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if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
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(dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
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disable_dev(dev);
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}
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/*
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* Allocate space to each device:
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*/
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DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
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for (dev = bus->devices; dev; dev = dev->sibling)
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{
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if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
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(dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
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layout_dev(dev);
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}
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DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
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}
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/*
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* static void pcibios_fixup(void)
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*
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* Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
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* true. This might be necessary because not every m68k machine with a PCI
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* bus has a PCI BIOS. This function should be called right after
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* pci_scan_bus() in pcibios_init().
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*/
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static void __init pcibios_fixup(void)
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{
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if (pci_modify)
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{
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/*
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* Set base addresses for allocation of I/O and memory space.
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*/
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io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
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mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
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/*
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* Scan the tree, allocating PCI memory and I/O space.
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*/
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layout_bus(pci_bus_b(pci_root.next));
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}
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/*
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* Fix interrupt assignments, etc.
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*/
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bus_info->fixup(pci_modify);
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}
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/*
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* static void pcibios_claim_resources(struct pci_bus *bus)
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*
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* Claim all resources that are assigned to devices on the given bus.
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*
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* Parameters:
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*
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* bus - bus.
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*/
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static void __init pcibios_claim_resources(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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int i;
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while (bus)
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{
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for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
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{
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for (i = 0; i < PCI_NUM_RESOURCES; i++)
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{
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struct resource *r = &dev->resource[i];
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struct resource *pr;
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struct pci_bus_info *bus_info = (struct pci_bus_info *) dev->sysdata;
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if ((r->start == 0) || (r->parent != NULL))
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continue;
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#if 1
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if (r->flags & IORESOURCE_IO)
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pr = &bus_info->io_space;
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else
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pr = &bus_info->mem_space;
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#else
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if (r->flags & IORESOURCE_IO)
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pr = &ioport_resource;
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else
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pr = &iomem_resource;
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#endif
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if (request_resource(pr, r) < 0)
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{
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printk(KERN_ERR "PCI: Address space collision on region %d of device %s\n", i, dev->name);
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}
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}
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}
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if (bus->children)
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pcibios_claim_resources(bus->children);
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bus = bus->next;
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}
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}
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/*
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* int pcibios_assign_resource(struct pci_dev *dev, int i)
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*
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* Assign a new address to a PCI resource.
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*
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* Parameters:
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*
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* dev - device.
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* i - resource.
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*
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* Result: 0 if successful.
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*/
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int __init pcibios_assign_resource(struct pci_dev *dev, int i)
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{
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struct resource *r = &dev->resource[i];
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struct resource *pr = pci_find_parent_resource(dev, r);
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unsigned long size = r->end + 1;
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if (!pr)
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return -EINVAL;
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if (r->flags & IORESOURCE_IO)
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{
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if (size > 0x100)
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return -EFBIG;
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if (allocate_resource(pr, r, size, bus_info->io_space.start +
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IO_ALLOC_OFFSET, bus_info->io_space.end, 1024))
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return -EBUSY;
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}
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else
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{
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if (allocate_resource(pr, r, size, bus_info->mem_space.start +
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MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
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return -EBUSY;
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}
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if (i < 6)
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pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
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return 0;
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}
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void __init pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev;
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void *sysdata;
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sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
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for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
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dev->sysdata = sysdata;
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}
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void __init pcibios_init(void)
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{
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printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
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bus_info = NULL;
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/* Hades code was:
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if (MACH_IS_HADES)
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bus_info = init_hades_pci();
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*/
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if (bus_info != NULL)
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{
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printk("PCI: Probing PCI hardware\n");
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pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
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pcibios_fixup();
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pcibios_claim_resources(pci_root);
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}
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else
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printk("PCI: No PCI bus detected\n");
|
||||
}
|
||||
|
||||
char * __init pcibios_setup(char *str)
|
||||
{
|
||||
if (!strcmp(str, "nomodify"))
|
||||
{
|
||||
pci_modify = 0;
|
||||
return NULL;
|
||||
}
|
||||
else if (!strcmp(str, "skipvga"))
|
||||
{
|
||||
skip_vga = 1;
|
||||
return NULL;
|
||||
}
|
||||
else if (!strcmp(str, "noburst"))
|
||||
{
|
||||
disable_pci_burst = 1;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return str;
|
||||
}
|
||||
#endif /* CONFIG_PCI */
|
||||
|
|
@ -11,10 +11,6 @@
|
|||
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
|
||||
extern void free_dma(unsigned int dmanr); /* release it again */
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
extern int isa_dma_bridge_buggy;
|
||||
#else
|
||||
#define isa_dma_bridge_buggy (0)
|
||||
#endif
|
||||
|
||||
#endif /* _M68K_DMA_H */
|
||||
|
|
|
|||
|
|
@ -7,15 +7,12 @@
|
|||
* - added skeleton for GG-II and Amiga PCMCIA
|
||||
* 2/3/01 RZ: - moved a few more defs into raw_io.h
|
||||
*
|
||||
* inX/outX/readX/writeX should not be used by any driver unless it does
|
||||
* ISA or PCI access. Other drivers should use function defined in raw_io.h
|
||||
* inX/outX should not be used by any driver unless it does
|
||||
* ISA access. Other drivers should use function defined in raw_io.h
|
||||
* or define its own macros on top of these.
|
||||
*
|
||||
* inX(),outX() are for PCI and ISA I/O
|
||||
* readX(),writeX() are for PCI memory
|
||||
* inX(),outX() are for ISA I/O
|
||||
* isa_readX(),isa_writeX() are for ISA memory
|
||||
*
|
||||
* moved mem{cpy,set}_*io inside CONFIG_PCI
|
||||
*/
|
||||
|
||||
#ifndef _IO_H
|
||||
|
|
@ -256,10 +253,7 @@ static inline void isa_delay(void)
|
|||
(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
|
||||
raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
|
||||
|
||||
#endif /* CONFIG_ISA */
|
||||
|
||||
|
||||
#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
|
||||
#define inb isa_inb
|
||||
#define inb_p isa_inb_p
|
||||
#define outb isa_outb
|
||||
|
|
@ -282,55 +276,9 @@ static inline void isa_delay(void)
|
|||
#define readw isa_readw
|
||||
#define writeb isa_writeb
|
||||
#define writew isa_writew
|
||||
#endif /* CONFIG_ISA */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
#else /* CONFIG_ISA */
|
||||
|
||||
#define readl(addr) in_le32(addr)
|
||||
#define writel(val,addr) out_le32((addr),(val))
|
||||
|
||||
/* those can be defined for both ISA and PCI - it won't work though */
|
||||
#define readb(addr) in_8(addr)
|
||||
#define readw(addr) in_le16(addr)
|
||||
#define writeb(val,addr) out_8((addr),(val))
|
||||
#define writew(val,addr) out_le16((addr),(val))
|
||||
|
||||
#define readb_relaxed(addr) readb(addr)
|
||||
#define readw_relaxed(addr) readw(addr)
|
||||
#define readl_relaxed(addr) readl(addr)
|
||||
|
||||
#ifndef CONFIG_ISA
|
||||
#define inb(port) in_8(port)
|
||||
#define outb(val,port) out_8((port),(val))
|
||||
#define inw(port) in_le16(port)
|
||||
#define outw(val,port) out_le16((port),(val))
|
||||
#define inl(port) in_le32(port)
|
||||
#define outl(val,port) out_le32((port),(val))
|
||||
|
||||
#else
|
||||
/*
|
||||
* kernel with both ISA and PCI compiled in, those have
|
||||
* conflicting defs for in/out. Simply consider port < 1024
|
||||
* ISA and everything else PCI. read,write not defined
|
||||
* in this case
|
||||
*/
|
||||
#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
|
||||
#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
|
||||
#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
|
||||
#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
|
||||
#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
|
||||
#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))
|
||||
|
||||
#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
|
||||
#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
|
||||
#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
|
||||
#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
|
||||
#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
|
||||
#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
|
||||
#endif
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
|
||||
/*
|
||||
* We need to define dummy functions for GENERIC_IOMAP support.
|
||||
*/
|
||||
|
|
@ -357,11 +305,11 @@ static inline void isa_delay(void)
|
|||
#define writeb(val,addr) out_8((addr),(val))
|
||||
#define readw(addr) in_le16(addr)
|
||||
#define writew(val,addr) out_le16((addr),(val))
|
||||
#endif
|
||||
#if !defined(CONFIG_PCI)
|
||||
|
||||
#endif /* CONFIG_ISA */
|
||||
|
||||
#define readl(addr) in_le32(addr)
|
||||
#define writel(val,addr) out_le32((addr),(val))
|
||||
#endif
|
||||
|
||||
#define mmiowb()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,54 +1,8 @@
|
|||
#ifndef _ASM_M68K_PCI_H
|
||||
#define _ASM_M68K_PCI_H
|
||||
|
||||
/*
|
||||
* asm-m68k/pci_m68k.h - m68k specific PCI declarations.
|
||||
*
|
||||
* Written by Wout Klaren.
|
||||
*/
|
||||
|
||||
#include <asm/scatterlist.h>
|
||||
#include <asm-generic/pci-dma-compat.h>
|
||||
|
||||
struct pci_ops;
|
||||
|
||||
/*
|
||||
* Structure with hardware dependent information and functions of the
|
||||
* PCI bus.
|
||||
*/
|
||||
|
||||
struct pci_bus_info
|
||||
{
|
||||
/*
|
||||
* Resources of the PCI bus.
|
||||
*/
|
||||
|
||||
struct resource mem_space;
|
||||
struct resource io_space;
|
||||
|
||||
/*
|
||||
* System dependent functions.
|
||||
*/
|
||||
|
||||
struct pci_ops *m68k_pci_ops;
|
||||
|
||||
void (*fixup)(int pci_modify);
|
||||
void (*conf_device)(struct pci_dev *dev);
|
||||
};
|
||||
|
||||
#define pcibios_assign_all_busses() 0
|
||||
#define pcibios_scan_all_fns(a, b) 0
|
||||
|
||||
static inline void pcibios_set_master(struct pci_dev *dev)
|
||||
{
|
||||
/* No special bus mastering setup handling */
|
||||
}
|
||||
|
||||
static inline void pcibios_penalize_isa_irq(int irq, int active)
|
||||
{
|
||||
/* We don't do dynamic PCI IRQ allocation */
|
||||
}
|
||||
|
||||
/* The PCI address space does equal the physical memory
|
||||
* address space. The networking and block device layers use
|
||||
* this boolean for bounce buffer decisions.
|
||||
|
|
|
|||
Loading…
Reference in a new issue