[IA64] Multiple outstanding ptc.g instruction support
According to SDM2.2, Itanium supports multiple outstanding ptc.g instructions. But current kernel function ia64_global_tlb_purge() uses a spinlock to serialize ptc.g instructions issued by multiple processors. This serialization might have scalability issue on a big SMP machine where many processors could purge TLB in parallel. The patch fixes this problem by issuing multiple ptc.g instructions in ia64_global_tlb_purge(). It also adds support for the "PALO" table to get a platform view of the max number of outstanding ptc.g instructions (which may be different from the processor view found from PAL_VM_SUMMARY). PALO specification can be found at: http://www.dig64.org/home/DIG64_PALO_R1_0.pdf spinaphore implementation by Matthew Wilcox. Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Fenghua Yu
Tony Luck
parent
e315c121a8
commit
2046b94e7c
5 changed files with 178 additions and 17 deletions
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@ -37,6 +37,7 @@
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#include <asm/pgtable.h>
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#include <asm/processor.h>
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#include <asm/mca.h>
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#include <asm/tlbflush.h>
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#define EFI_DEBUG 0
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@ -403,6 +404,41 @@ efi_get_pal_addr (void)
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return NULL;
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}
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static u8 __init palo_checksum(u8 *buffer, u32 length)
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{
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u8 sum = 0;
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u8 *end = buffer + length;
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while (buffer < end)
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sum = (u8) (sum + *(buffer++));
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return sum;
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}
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/*
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* Parse and handle PALO table which is published at:
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* http://www.dig64.org/home/DIG64_PALO_R1_0.pdf
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*/
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static void __init handle_palo(unsigned long palo_phys)
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{
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struct palo_table *palo = __va(palo_phys);
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u8 checksum;
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if (strncmp(palo->signature, PALO_SIG, sizeof(PALO_SIG) - 1)) {
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printk(KERN_INFO "PALO signature incorrect.\n");
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return;
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}
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checksum = palo_checksum((u8 *)palo, palo->length);
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if (checksum) {
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printk(KERN_INFO "PALO checksum incorrect.\n");
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return;
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}
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setup_ptcg_sem(palo->max_tlb_purges, 1);
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}
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void
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efi_map_pal_code (void)
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{
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@ -432,6 +468,7 @@ efi_init (void)
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u64 efi_desc_size;
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char *cp, vendor[100] = "unknown";
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int i;
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unsigned long palo_phys;
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/*
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* It's too early to be able to use the standard kernel command line
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@ -496,6 +533,8 @@ efi_init (void)
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efi.hcdp = EFI_INVALID_TABLE_ADDR;
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efi.uga = EFI_INVALID_TABLE_ADDR;
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palo_phys = EFI_INVALID_TABLE_ADDR;
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for (i = 0; i < (int) efi.systab->nr_tables; i++) {
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if (efi_guidcmp(config_tables[i].guid, MPS_TABLE_GUID) == 0) {
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efi.mps = config_tables[i].table;
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@ -515,10 +554,17 @@ efi_init (void)
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} else if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) {
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efi.hcdp = config_tables[i].table;
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printk(" HCDP=0x%lx", config_tables[i].table);
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} else if (efi_guidcmp(config_tables[i].guid,
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PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID) == 0) {
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palo_phys = config_tables[i].table;
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printk(" PALO=0x%lx", config_tables[i].table);
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}
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}
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printk("\n");
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if (palo_phys != EFI_INVALID_TABLE_ADDR)
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handle_palo(palo_phys);
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runtime = __va(efi.systab->runtime);
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efi.get_time = phys_get_time;
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efi.set_time = phys_set_time;
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@ -59,6 +59,7 @@
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#include <asm/setup.h>
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#include <asm/smp.h>
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#include <asm/system.h>
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#include <asm/tlbflush.h>
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#include <asm/unistd.h>
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#include <asm/hpsim.h>
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@ -946,9 +947,10 @@ cpu_init (void)
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#endif
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/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
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if (ia64_pal_vm_summary(NULL, &vmi) == 0)
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if (ia64_pal_vm_summary(NULL, &vmi) == 0) {
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max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
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else {
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setup_ptcg_sem(vmi.pal_vm_info_2_s.max_purges, 0);
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} else {
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printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
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max_ctx = (1U << 15) - 1; /* use architected minimum */
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}
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@ -11,6 +11,9 @@
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* Rohit Seth <rohit.seth@intel.com>
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* Ken Chen <kenneth.w.chen@intel.com>
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* Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
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* Copyright (C) 2007 Intel Corp
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* Fenghua Yu <fenghua.yu@intel.com>
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* Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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@ -26,6 +29,7 @@
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#include <asm/pal.h>
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#include <asm/tlbflush.h>
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#include <asm/dma.h>
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#include <asm/sal.h>
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static struct {
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unsigned long mask; /* mask of supported purge page-sizes */
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@ -84,14 +88,104 @@ wrap_mmu_context (struct mm_struct *mm)
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local_flush_tlb_all();
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}
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/*
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* Implement "spinaphores" ... like counting semaphores, but they
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* spin instead of sleeping. If there are ever any other users for
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* this primitive it can be moved up to a spinaphore.h header.
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*/
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struct spinaphore {
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atomic_t cur;
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};
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static inline void spinaphore_init(struct spinaphore *ss, int val)
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{
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atomic_set(&ss->cur, val);
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}
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static inline void down_spin(struct spinaphore *ss)
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{
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while (unlikely(!atomic_add_unless(&ss->cur, -1, 0)))
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while (atomic_read(&ss->cur) == 0)
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cpu_relax();
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}
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static inline void up_spin(struct spinaphore *ss)
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{
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atomic_add(1, &ss->cur);
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}
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static struct spinaphore ptcg_sem;
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static u16 nptcg = 1;
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static int need_ptcg_sem = 1;
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static int toolatetochangeptcgsem = 0;
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/*
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* Maximum number of simultaneous ptc.g purges in the system can
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* be defined by PAL_VM_SUMMARY (in which case we should take
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* the smallest value for any cpu in the system) or by the PAL
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* override table (in which case we should ignore the value from
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* PAL_VM_SUMMARY).
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*
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* Complicating the logic here is the fact that num_possible_cpus()
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* isn't fully setup until we start bringing cpus online.
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*/
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void
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setup_ptcg_sem(int max_purges, int from_palo)
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{
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static int have_palo;
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static int firstcpu = 1;
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if (toolatetochangeptcgsem) {
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BUG_ON(max_purges < nptcg);
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return;
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}
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if (from_palo) {
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have_palo = 1;
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/* In PALO max_purges == 0 really means it! */
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if (max_purges == 0)
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panic("Whoa! Platform does not support global TLB purges.\n");
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nptcg = max_purges;
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if (nptcg == PALO_MAX_TLB_PURGES) {
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need_ptcg_sem = 0;
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return;
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}
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goto resetsema;
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}
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if (have_palo) {
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if (nptcg != PALO_MAX_TLB_PURGES)
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need_ptcg_sem = (num_possible_cpus() > nptcg);
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return;
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}
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/* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
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if (max_purges == 0) max_purges = 1;
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if (firstcpu) {
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nptcg = max_purges;
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firstcpu = 0;
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}
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if (max_purges < nptcg)
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nptcg = max_purges;
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if (nptcg == PAL_MAX_PURGES) {
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need_ptcg_sem = 0;
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return;
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} else
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need_ptcg_sem = (num_possible_cpus() > nptcg);
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resetsema:
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spinaphore_init(&ptcg_sem, max_purges);
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}
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void
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ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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unsigned long end, unsigned long nbits)
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{
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static DEFINE_SPINLOCK(ptcg_lock);
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struct mm_struct *active_mm = current->active_mm;
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toolatetochangeptcgsem = 1;
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if (mm != active_mm) {
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/* Restore region IDs for mm */
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if (mm && active_mm) {
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@ -102,19 +196,20 @@ ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
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}
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}
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/* HW requires global serialization of ptc.ga. */
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spin_lock(&ptcg_lock);
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{
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do {
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/*
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* Flush ALAT entries also.
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*/
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ia64_ptcga(start, (nbits<<2));
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ia64_srlz_i();
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start += (1UL << nbits);
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} while (start < end);
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}
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spin_unlock(&ptcg_lock);
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if (need_ptcg_sem)
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down_spin(&ptcg_sem);
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do {
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/*
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* Flush ALAT entries also.
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*/
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ia64_ptcga(start, (nbits << 2));
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ia64_srlz_i();
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start += (1UL << nbits);
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} while (start < end);
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if (need_ptcg_sem)
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up_spin(&ptcg_sem);
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if (mm != active_mm) {
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activate_context(active_mm);
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@ -296,6 +296,9 @@ enum {
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EFI_GUID(0xe429faf8, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
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#define SAL_PLAT_BUS_ERR_SECT_GUID \
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EFI_GUID(0xe429faf9, 0x3cb7, 0x11d4, 0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81)
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#define PROCESSOR_ABSTRACTION_LAYER_OVERWRITE_GUID \
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EFI_GUID(0x6cb0a200, 0x893a, 0x11da, 0x96, 0xd2, 0x0, 0x10, 0x83, 0xff, \
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0xca, 0x4d)
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#define MAX_CACHE_ERRORS 6
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#define MAX_TLB_ERRORS 6
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@ -879,6 +882,20 @@ extern void ia64_jump_to_sal(struct sal_to_os_boot *);
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extern void ia64_sal_handler_init(void *entry_point, void *gpval);
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#define PALO_MAX_TLB_PURGES 0xFFFF
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#define PALO_SIG "PALO"
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struct palo_table {
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u8 signature[4]; /* Should be "PALO" */
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u32 length;
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u8 minor_revision;
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u8 major_revision;
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u8 checksum;
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u8 reserved1[5];
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u16 max_tlb_purges;
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u8 reserved2[6];
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};
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_IA64_SAL_H */
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@ -17,6 +17,7 @@
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* Now for some TLB flushing routines. This is the kind of stuff that
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* can be very expensive, so try to avoid them whenever possible.
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*/
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extern void setup_ptcg_sem(int max_purges, int from_palo);
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/*
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* Flush everything (kernel mapping may also have changed due to
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