powerpc/mm: Add more bit definitions for Book3E MMU registers
This adds various additional bit definitions for various MMU related SPRs used on Book3E. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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Benjamin Herrenschmidt
parent
29c09e8fba
commit
1fe1a21005
1 changed files with 114 additions and 44 deletions
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@ -38,58 +38,128 @@
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#define BOOK3E_PAGESZ_1TB 30
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#define BOOK3E_PAGESZ_2TB 31
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#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
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#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
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#define MAS0_NV(x) ((x) & 0x00000FFF)
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/* MAS registers bit definitions */
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
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#define MAS1_IND 0x00002000
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#define MAS1_TS 0x00001000
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#define MAS1_TSIZE(x) ((x << 7) & 0x00000F80)
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#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
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#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
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#define MAS0_NV(x) ((x) & 0x00000FFF)
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#define MAS0_HES 0x00004000
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#define MAS0_WQ_ALLWAYS 0x00000000
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#define MAS0_WQ_COND 0x00001000
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#define MAS0_WQ_CLR_RSRV 0x00002000
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#define MAS2_EPN 0xFFFFF000
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
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#define MAS1_IND 0x00002000
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#define MAS1_TS 0x00001000
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#define MAS1_TSIZE_MASK 0x00000f80
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#define MAS1_TSIZE_SHIFT 7
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#define MAS1_TSIZE(x) ((x << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK)
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#define MAS2_EPN 0xFFFFF000
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS2_EPN_MASK(size) (~0 << (size + 10))
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#define MAS2_VAL(addr, size, flags) ((addr) & MAS2_EPN_MASK(size) | (flags))
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#define MAS3_RPN 0xFFFFF000
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS3_RPN 0xFFFFF000
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS3_SPSIZE 0x0000003e
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#define MAS3_SPSIZE_SHIFT 1
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#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
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#define MAS4_INDD 0x00008000
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#define MAS4_TSIZED(x) MAS1_TSIZE(x)
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#define MAS4_X0D 0x00000040
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#define MAS4_X1D 0x00000020
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#define MAS4_WD 0x00000010
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#define MAS4_ID 0x00000008
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#define MAS4_MD 0x00000004
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#define MAS4_GD 0x00000002
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#define MAS4_ED 0x00000001
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#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
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#define MAS4_INDD 0x00008000 /* Default IND */
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#define MAS4_TSIZED(x) MAS1_TSIZE(x)
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#define MAS4_X0D 0x00000040
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#define MAS4_X1D 0x00000020
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#define MAS4_WD 0x00000010
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#define MAS4_ID 0x00000008
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#define MAS4_MD 0x00000004
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#define MAS4_GD 0x00000002
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#define MAS4_ED 0x00000001
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#define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
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#define MAS4_WIMGED_SHIFT 0
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#define MAS4_VLED MAS4_X1D /* Default VLE */
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#define MAS4_ACMD 0x000000c0 /* Default ACM */
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#define MAS4_ACMD_SHIFT 6
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#define MAS4_TSIZED_MASK 0x00000f80 /* Default TSIZE */
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#define MAS4_TSIZED_SHIFT 7
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#define MAS6_SPID0 0x3FFF0000
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#define MAS6_SPID1 0x00007FFE
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#define MAS6_ISIZE(x) MAS1_TSIZE(x)
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#define MAS6_SAS 0x00000001
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#define MAS6_SPID MAS6_SPID0
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#define MAS6_SPID0 0x3FFF0000
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#define MAS6_SPID1 0x00007FFE
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#define MAS6_ISIZE(x) MAS1_TSIZE(x)
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#define MAS6_SAS 0x00000001
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#define MAS6_SPID MAS6_SPID0
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#define MAS6_SIND 0x00000002 /* Indirect page */
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#define MAS6_SIND_SHIFT 1
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#define MAS6_SPID_MASK 0x3fff0000
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#define MAS6_SPID_SHIFT 16
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#define MAS6_ISIZE_MASK 0x00000f80
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#define MAS6_ISIZE_SHIFT 7
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#define MAS7_RPN 0xFFFFFFFF
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#define MAS7_RPN 0xFFFFFFFF
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/* TLBnCFG encoding */
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#define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
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#define TLBnCFG_HES 0x00002000 /* HW select supported */
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#define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
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#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
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#define TLBnCFG_IND 0x00020000 /* IND entries supported */
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#define TLBnCFG_PT 0x00040000 /* Can load from page table */
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#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
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/* TLBnPS encoding */
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#define TLBnPS_4K 0x00000004
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#define TLBnPS_8K 0x00000008
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#define TLBnPS_16K 0x00000010
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#define TLBnPS_32K 0x00000020
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#define TLBnPS_64K 0x00000040
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#define TLBnPS_128K 0x00000080
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#define TLBnPS_256K 0x00000100
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#define TLBnPS_512K 0x00000200
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#define TLBnPS_1M 0x00000400
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#define TLBnPS_2M 0x00000800
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#define TLBnPS_4M 0x00001000
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#define TLBnPS_8M 0x00002000
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#define TLBnPS_16M 0x00004000
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#define TLBnPS_32M 0x00008000
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#define TLBnPS_64M 0x00010000
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#define TLBnPS_128M 0x00020000
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#define TLBnPS_256M 0x00040000
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#define TLBnPS_512M 0x00080000
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#define TLBnPS_1G 0x00100000
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#define TLBnPS_2G 0x00200000
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#define TLBnPS_4G 0x00400000
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#define TLBnPS_8G 0x00800000
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#define TLBnPS_16G 0x01000000
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#define TLBnPS_32G 0x02000000
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#define TLBnPS_64G 0x04000000
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#define TLBnPS_128G 0x08000000
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#define TLBnPS_256G 0x10000000
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/* tlbilx action encoding */
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#define TLBILX_T_ALL 0
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#define TLBILX_T_TID 1
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#define TLBILX_T_FULLMATCH 3
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#define TLBILX_T_CLASS0 4
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#define TLBILX_T_CLASS1 5
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#define TLBILX_T_CLASS2 6
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#define TLBILX_T_CLASS3 7
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#ifndef __ASSEMBLY__
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