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MIPS: JZ4770: Work around config2 misreporting associativity

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According to config2, the associativity would be 5-ways, but the
documentation states 4-ways, which also matches the documented
L2 cache size of 256 kB.

Signed-off-by: Maarten ter Huurne <maarten@treewalker.org>
Reviewed-by: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18488/
Signed-off-by: James Hogan <jhogan@kernel.org>
This commit is contained in:
Maarten ter Huurne 2018-01-16 16:48:02 +01:00 committed by James Hogan
parent 9be5f3e92e
commit 1f7412e0e2
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1 changed files with 9 additions and 0 deletions
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9
arch/mips/mm/sc-mips.c
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@ -16,6 +16,7 @@
#include <asm/mmu_context.h>
#include <asm/r4kcache.h>
#include <asm/mips-cps.h>
#include <asm/bootinfo.h>
/*
* MIPS32/MIPS64 L2 cache handling
@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void)
else
return 0;
/*
* According to config2 it would be 5-ways, but that is contradicted
* by all documentation.
*/
if (current_cpu_type() == CPU_JZRISC &&
mips_machtype == MACH_INGENIC_JZ4770)
c->scache.ways = 4;
c->scache.waysize = c->scache.sets * c->scache.linesz;
c->scache.waybit = __ffs(c->scache.waysize);