OMAP4: hwmod data: Move the smartreflex structures
The merge of the SR series on top of the already modified omap_hwmod_data_44xx.c moved the smartreflex structures at the wrong position in the file. - Re-order the structures properly. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Cc: Thara Gopinath <thara@ti.com> Tested-by: G, Manjunath Kondaiah <manjugk@ti.com> Acked-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Benoit Cousson
Tony Lindgren
parent
4d218826ad
commit
1f6a717f1c
1 changed files with 169 additions and 172 deletions
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@ -556,9 +556,6 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
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* sl2if
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* slimbus1
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* slimbus2
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* smartreflex_core
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* smartreflex_iva
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* smartreflex_mpu
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* spinlock
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* timer1
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* timer10
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@ -1392,6 +1389,170 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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* 'smartreflex' class
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* smartreflex module (monitor silicon performance and outputs a measure of
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* performance error)
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*/
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/* The IP is not compliant to type1 / type2 scheme */
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static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
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.sidle_shift = 24,
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.enwkup_shift = 26,
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};
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static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
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.sysc_offs = 0x0038,
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.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
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};
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static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
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.name = "smartreflex",
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.sysc = &omap44xx_smartreflex_sysc,
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.rev = 2,
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};
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/* smartreflex_core */
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static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
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{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
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{
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.pa_start = 0x4a0dd000,
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.pa_end = 0x4a0dd03f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_core */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_core_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_core_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_core slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_core,
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};
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static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
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.name = "smartreflex_core",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_core_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
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.main_clk = "smartreflex_core_fck",
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.vdd_name = "core",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* smartreflex_iva */
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static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
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{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
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{
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.pa_start = 0x4a0db000,
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.pa_end = 0x4a0db03f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_iva */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_iva_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_iva_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_iva slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_iva,
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};
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static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
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.name = "smartreflex_iva",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_iva_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
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.main_clk = "smartreflex_iva_fck",
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.vdd_name = "iva",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_iva_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* smartreflex_mpu */
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static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
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{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
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{
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.pa_start = 0x4a0d9000,
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.pa_end = 0x4a0d903f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_mpu */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_mpu_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_mpu_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_mpu slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_mpu,
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};
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static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
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.name = "smartreflex_mpu",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
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.main_clk = "smartreflex_mpu_fck",
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.vdd_name = "mpu",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_mpu_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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* 'uart' class
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* universal asynchronous receiver/transmitter (uart)
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@ -1842,170 +2003,6 @@ static struct omap_hwmod omap44xx_dma_system_hwmod = {
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/*
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* 'smartreflex' class
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* smartreflex module (monitor silicon performance and outputs a measure of
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* performance error)
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*/
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/* The IP is not compliant to type1 / type2 scheme */
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static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
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.sidle_shift = 24,
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.enwkup_shift = 26,
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};
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static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
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.sysc_offs = 0x0038,
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.sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.sysc_fields = &omap_hwmod_sysc_type_smartreflex,
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};
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static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
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.name = "smartreflex",
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.sysc = &omap44xx_smartreflex_sysc,
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.rev = 2,
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};
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/* smartreflex_core */
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static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
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{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
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{
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.pa_start = 0x4a0dd000,
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.pa_end = 0x4a0dd03f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_core */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_core_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_core_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_core slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_core,
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};
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static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
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.name = "smartreflex_core",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_core_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
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.main_clk = "smartreflex_core_fck",
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.vdd_name = "core",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_core_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* smartreflex_iva */
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static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
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{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
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{
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.pa_start = 0x4a0db000,
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.pa_end = 0x4a0db03f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_iva */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_iva_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_iva_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_iva slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_iva,
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};
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static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
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.name = "smartreflex_iva",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_iva_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
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.main_clk = "smartreflex_iva_fck",
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.vdd_name = "iva",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_iva_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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/* smartreflex_mpu */
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static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
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static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
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{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
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};
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static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
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{
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.pa_start = 0x4a0d9000,
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.pa_end = 0x4a0d903f,
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.flags = ADDR_TYPE_RT
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},
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};
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/* l4_cfg -> smartreflex_mpu */
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static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
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.master = &omap44xx_l4_cfg_hwmod,
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.slave = &omap44xx_smartreflex_mpu_hwmod,
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.clk = "l4_div_ck",
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.addr = omap44xx_smartreflex_mpu_addrs,
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.addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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/* smartreflex_mpu slave ports */
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static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
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&omap44xx_l4_cfg__smartreflex_mpu,
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};
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static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
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.name = "smartreflex_mpu",
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.class = &omap44xx_smartreflex_hwmod_class,
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.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
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.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
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.main_clk = "smartreflex_mpu_fck",
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.vdd_name = "mpu",
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.prcm = {
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.omap4 = {
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.clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
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},
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},
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.slaves = omap44xx_smartreflex_mpu_slaves,
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.slaves_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_slaves),
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.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
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};
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static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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/* dmm class */
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&omap44xx_dmm_hwmod,
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@ -2057,6 +2054,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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/* mpu class */
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&omap44xx_mpu_hwmod,
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/* smartreflex class */
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&omap44xx_smartreflex_core_hwmod,
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&omap44xx_smartreflex_iva_hwmod,
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&omap44xx_smartreflex_mpu_hwmod,
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/* uart class */
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&omap44xx_uart1_hwmod,
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&omap44xx_uart2_hwmod,
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@ -2067,11 +2069,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
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&omap44xx_wd_timer2_hwmod,
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&omap44xx_wd_timer3_hwmod,
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/* smartreflex class */
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&omap44xx_smartreflex_core_hwmod,
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&omap44xx_smartreflex_iva_hwmod,
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&omap44xx_smartreflex_mpu_hwmod,
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NULL,
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};
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