KVM: ia64: add support for Tukwila processors
In Tukwila processor, VT-i has been enhanced in its implementation, it is often called VT-i2 techonology. With VTi-2 support, virtulization performance should be improved. In this patch, we added the related stuff to support kvm/ia64 for Tukwila processors. Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com> Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Xiantao Zhang
Avi Kivity
parent
81aec5227e
commit
1f095610aa
1 changed files with 91 additions and 21 deletions
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@ -1,9 +1,12 @@
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/*
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* arch/ia64/vmx/optvfault.S
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* arch/ia64/kvm/optvfault.S
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* optimize virtualization fault handler
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*
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* Copyright (C) 2006 Intel Co
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* Xuefei Xu (Anthony Xu) <anthony.xu@intel.com>
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* Copyright (C) 2008 Intel Co
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* Add the support for Tukwila processors.
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* Xiantao Zhang <xiantao.zhang@intel.com>
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*/
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#include <asm/asmmacro.h>
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@ -20,6 +23,29 @@
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#define ACCE_MOV_TO_PSR
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#define ACCE_THASH
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#define VMX_VPS_SYNC_READ \
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add r16=VMM_VPD_BASE_OFFSET,r21; \
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mov r17 = b0; \
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mov r18 = r24; \
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mov r19 = r25; \
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mov r20 = r31; \
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;; \
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{.mii; \
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ld8 r16 = [r16]; \
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nop 0x0; \
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mov r24 = ip; \
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;; \
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}; \
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{.mmb; \
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add r24=0x20, r24; \
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mov r25 =r16; \
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br.sptk.many kvm_vps_sync_read; \
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}; \
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mov b0 = r17; \
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mov r24 = r18; \
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mov r25 = r19; \
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mov r31 = r20
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ENTRY(kvm_vps_entry)
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adds r29 = VMM_VCPU_VSA_BASE_OFFSET,r21
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;;
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@ -226,11 +252,11 @@ GLOBAL_ENTRY(kvm_asm_rsm)
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#ifndef ACCE_RSM
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br.many kvm_virtualization_fault_back
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#endif
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add r16=VMM_VPD_BASE_OFFSET,r21
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VMX_VPS_SYNC_READ
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;;
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extr.u r26=r25,6,21
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extr.u r27=r25,31,2
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;;
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ld8 r16=[r16]
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extr.u r28=r25,36,1
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dep r26=r27,r26,21,2
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;;
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@ -265,7 +291,7 @@ GLOBAL_ENTRY(kvm_asm_rsm)
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tbit.nz p6,p0=r23,0
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;;
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tbit.z.or p6,p0=r26,IA64_PSR_DT_BIT
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(p6) br.dptk kvm_resume_to_guest
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(p6) br.dptk kvm_resume_to_guest_with_sync
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;;
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add r26=VMM_VCPU_META_RR0_OFFSET,r21
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add r27=VMM_VCPU_META_RR0_OFFSET+8,r21
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@ -281,7 +307,7 @@ GLOBAL_ENTRY(kvm_asm_rsm)
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mov rr[r28]=r27
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;;
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srlz.d
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br.many kvm_resume_to_guest
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br.many kvm_resume_to_guest_with_sync
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END(kvm_asm_rsm)
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@ -290,11 +316,11 @@ GLOBAL_ENTRY(kvm_asm_ssm)
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#ifndef ACCE_SSM
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br.many kvm_virtualization_fault_back
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#endif
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add r16=VMM_VPD_BASE_OFFSET,r21
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VMX_VPS_SYNC_READ
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;;
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extr.u r26=r25,6,21
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extr.u r27=r25,31,2
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;;
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ld8 r16=[r16]
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extr.u r28=r25,36,1
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dep r26=r27,r26,21,2
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;; //r26 is imm24
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@ -340,7 +366,7 @@ kvm_asm_ssm_1:
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tbit.nz p6,p0=r29,IA64_PSR_I_BIT
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;;
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tbit.z.or p6,p0=r19,IA64_PSR_I_BIT
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(p6) br.dptk kvm_resume_to_guest
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(p6) br.dptk kvm_resume_to_guest_with_sync
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;;
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add r29=VPD_VTPR_START_OFFSET,r16
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add r30=VPD_VHPI_START_OFFSET,r16
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@ -355,7 +381,7 @@ kvm_asm_ssm_1:
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;;
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cmp.gt p6,p0=r30,r17
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(p6) br.dpnt.few kvm_asm_dispatch_vexirq
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br.many kvm_resume_to_guest
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br.many kvm_resume_to_guest_with_sync
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END(kvm_asm_ssm)
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@ -364,10 +390,9 @@ GLOBAL_ENTRY(kvm_asm_mov_to_psr)
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#ifndef ACCE_MOV_TO_PSR
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br.many kvm_virtualization_fault_back
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#endif
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add r16=VMM_VPD_BASE_OFFSET,r21
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extr.u r26=r25,13,7 //r2
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VMX_VPS_SYNC_READ
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;;
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ld8 r16=[r16]
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extr.u r26=r25,13,7 //r2
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addl r20=@gprel(asm_mov_from_reg),gp
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;;
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adds r30=kvm_asm_mov_to_psr_back-asm_mov_from_reg,r20
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@ -443,7 +468,7 @@ kvm_asm_mov_to_psr_1:
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;;
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tbit.nz.or p6,p0=r17,IA64_PSR_I_BIT
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tbit.z.or p6,p0=r30,IA64_PSR_I_BIT
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(p6) br.dpnt.few kvm_resume_to_guest
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(p6) br.dpnt.few kvm_resume_to_guest_with_sync
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;;
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add r29=VPD_VTPR_START_OFFSET,r16
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add r30=VPD_VHPI_START_OFFSET,r16
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@ -458,13 +483,29 @@ kvm_asm_mov_to_psr_1:
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;;
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cmp.gt p6,p0=r30,r17
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(p6) br.dpnt.few kvm_asm_dispatch_vexirq
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br.many kvm_resume_to_guest
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br.many kvm_resume_to_guest_with_sync
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END(kvm_asm_mov_to_psr)
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ENTRY(kvm_asm_dispatch_vexirq)
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//increment iip
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mov r17 = b0
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mov r18 = r31
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{.mii
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add r25=VMM_VPD_BASE_OFFSET,r21
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nop 0x0
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mov r24 = ip
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;;
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}
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{.mmb
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add r24 = 0x20, r24
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ld8 r25 = [r25]
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br.sptk.many kvm_vps_sync_write
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}
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mov b0 =r17
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mov r16=cr.ipsr
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mov r31 = r18
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mov r19 = 37
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;;
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extr.u r17=r16,IA64_PSR_RI_BIT,2
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tbit.nz p6,p7=r16,IA64_PSR_RI_BIT+1
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@ -504,25 +545,31 @@ GLOBAL_ENTRY(kvm_asm_thash)
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;;
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kvm_asm_thash_back1:
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shr.u r23=r19,61 // get RR number
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adds r25=VMM_VCPU_VRR0_OFFSET,r21 // get vcpu->arch.vrr[0]'s addr
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adds r28=VMM_VCPU_VRR0_OFFSET,r21 // get vcpu->arch.vrr[0]'s addr
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adds r16=VMM_VPD_VPTA_OFFSET,r16 // get vpta
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;;
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shladd r27=r23,3,r25 // get vcpu->arch.vrr[r23]'s addr
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shladd r27=r23,3,r28 // get vcpu->arch.vrr[r23]'s addr
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ld8 r17=[r16] // get PTA
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mov r26=1
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;;
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extr.u r29=r17,2,6 // get pta.size
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ld8 r25=[r27] // get vcpu->arch.vrr[r23]'s value
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extr.u r29=r17,2,6 // get pta.size
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ld8 r28=[r27] // get vcpu->arch.vrr[r23]'s value
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;;
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extr.u r25=r25,2,6 // get rr.ps
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mov b0=r24
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//Fallback to C if pta.vf is set
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tbit.nz p6,p0=r17, 8
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;;
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(p6) mov r24=EVENT_THASH
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(p6) br.cond.dpnt.many kvm_virtualization_fault_back
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extr.u r28=r28,2,6 // get rr.ps
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shl r22=r26,r29 // 1UL << pta.size
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;;
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shr.u r23=r19,r25 // vaddr >> rr.ps
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shr.u r23=r19,r28 // vaddr >> rr.ps
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adds r26=3,r29 // pta.size + 3
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shl r27=r17,3 // pta << 3
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;;
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shl r23=r23,3 // (vaddr >> rr.ps) << 3
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shr.u r27=r27,r26 // (pta << 3) >> (pta.size+3)
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shr.u r27=r27,r26 // (pta << 3) >> (pta.size+3)
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movl r16=7<<61
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;;
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adds r22=-1,r22 // (1UL << pta.size) - 1
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@ -793,6 +840,29 @@ END(asm_mov_from_reg)
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* r31: pr
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* r24: b0
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*/
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ENTRY(kvm_resume_to_guest_with_sync)
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adds r19=VMM_VPD_BASE_OFFSET,r21
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mov r16 = r31
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mov r17 = r24
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;;
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{.mii
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ld8 r25 =[r19]
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nop 0x0
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mov r24 = ip
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;;
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}
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{.mmb
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add r24 =0x20, r24
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nop 0x0
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br.sptk.many kvm_vps_sync_write
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}
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mov r31 = r16
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mov r24 =r17
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;;
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br.sptk.many kvm_resume_to_guest
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END(kvm_resume_to_guest_with_sync)
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ENTRY(kvm_resume_to_guest)
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adds r16 = VMM_VCPU_SAVED_GP_OFFSET,r21
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;;
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