drm/radeon/kms: re-emit full context state for evergreen blits
clear state doesn't seem to work properly in some cases Fixes hangs in heavy 3D on some evergreen cards reported on IRC. May fix: https://bugs.freedesktop.org/show_bug.cgi?id=33381 possibly others. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Cc: stable@kernel.org Signed-off-by: Dave Airlie <airlied@gmail.com>
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1 changed files with 33 additions and 6 deletions
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@ -232,7 +232,7 @@ draw_auto(struct radeon_device *rdev)
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}
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/* emits 30 */
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/* emits 34 */
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static void
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set_default_state(struct radeon_device *rdev)
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{
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@ -245,6 +245,8 @@ set_default_state(struct radeon_device *rdev)
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int num_hs_threads, num_ls_threads;
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int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries;
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int num_hs_stack_entries, num_ls_stack_entries;
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u64 gpu_addr;
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int dwords;
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switch (rdev->family) {
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case CHIP_CEDAR:
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@ -497,6 +499,14 @@ set_default_state(struct radeon_device *rdev)
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radeon_ring_write(rdev, 0x00000000);
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radeon_ring_write(rdev, 0x00000000);
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/* emit an IB pointing at default state */
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dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
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gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
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radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
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radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC);
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radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
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radeon_ring_write(rdev, dwords);
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}
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static inline uint32_t i2f(uint32_t input)
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@ -527,8 +537,10 @@ static inline uint32_t i2f(uint32_t input)
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int evergreen_blit_init(struct radeon_device *rdev)
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{
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u32 obj_size;
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int r;
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int r, dwords;
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void *ptr;
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u32 packet2s[16];
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int num_packet2s = 0;
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/* pin copy shader into vram if already initialized */
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if (rdev->r600_blit.shader_obj)
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@ -536,8 +548,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
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mutex_init(&rdev->r600_blit.mutex);
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rdev->r600_blit.state_offset = 0;
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rdev->r600_blit.state_len = 0;
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obj_size = 0;
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rdev->r600_blit.state_len = evergreen_default_size;
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dwords = rdev->r600_blit.state_len;
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while (dwords & 0xf) {
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packet2s[num_packet2s++] = PACKET2(0);
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dwords++;
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}
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obj_size = dwords * 4;
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obj_size = ALIGN(obj_size, 256);
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rdev->r600_blit.vs_offset = obj_size;
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obj_size += evergreen_vs_size * 4;
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@ -567,6 +588,12 @@ int evergreen_blit_init(struct radeon_device *rdev)
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return r;
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}
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memcpy_toio(ptr + rdev->r600_blit.state_offset,
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evergreen_default_state, rdev->r600_blit.state_len * 4);
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if (num_packet2s)
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memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
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packet2s, num_packet2s * 4);
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memcpy(ptr + rdev->r600_blit.vs_offset, evergreen_vs, evergreen_vs_size * 4);
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memcpy(ptr + rdev->r600_blit.ps_offset, evergreen_ps, evergreen_ps_size * 4);
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radeon_bo_kunmap(rdev->r600_blit.shader_obj);
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@ -652,7 +679,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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/* calculate number of loops correctly */
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 46; /* shaders + def state */
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ring_size += 50; /* shaders + def state */
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ring_size += 10; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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ring_size += 10; /* fence emit for done copy */
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@ -660,7 +687,7 @@ int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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if (r)
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return r;
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set_default_state(rdev); /* 30 */
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set_default_state(rdev); /* 34 */
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set_shaders(rdev); /* 16 */
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return 0;
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}
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