[PATCH] ata_piix: finer-grained port_info
Make port_info finer-grained. This patch doesn't cause any functional change. Later init reimplementation will make use of it. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
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1 changed files with 58 additions and 19 deletions
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@ -119,11 +119,14 @@ enum {
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PIIX_80C_PRI = (1 << 5) | (1 << 4),
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PIIX_80C_SEC = (1 << 7) | (1 << 6),
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ich5_pata = 0,
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ich5_sata = 1,
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piix4_pata = 2,
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ich6_sata = 3,
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ich6_sata_ahci = 4,
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/* controller IDs */
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piix4_pata = 0,
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ich5_pata = 1,
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ich5_sata = 2,
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esb_sata = 3,
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ich6_sata = 4,
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ich6_sata_ahci = 5,
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ich6m_sata_ahci = 6,
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PIIX_AHCI_DEVICE = 6,
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};
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@ -149,19 +152,32 @@ static const struct pci_device_id piix_pci_tbl[] = {
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* list in drivers/pci/quirks.c.
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*/
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/* 82801EB (ICH5) */
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{ 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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/* 82801EB (ICH5) */
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{ 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
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/* 6300ESB (ICH5 variant with broken PCS present bits) */
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{ 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
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/* 6300ESB pretending RAID */
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{ 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
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/* 82801FB/FW (ICH6/ICH6W) */
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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/* 82801FR/FRW (ICH6R/ICH6RW) */
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
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{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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/* Enterprise Southbridge 2 (where's the datasheet?) */
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* SATA Controller 1 IDE (ICH8, no datasheet yet) */
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* SATA Controller 2 IDE (ICH8, ditto) */
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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/* Mobile SATA Controller IDE (ICH8M, ditto) */
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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{ } /* terminate list */
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};
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@ -255,6 +271,20 @@ static const struct ata_port_operations piix_sata_ops = {
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};
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static struct ata_port_info piix_port_info[] = {
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/* piix4_pata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SLAVE_POSS,
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.pio_mask = 0x1f, /* pio0-4 */
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#if 0
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.mwdma_mask = 0x06, /* mwdma1-2 */
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#else
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.mwdma_mask = 0x00, /* mwdma broken */
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#endif
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.udma_mask = ATA_UDMA_MASK_40C,
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.port_ops = &piix_pata_ops,
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},
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/* ich5_pata */
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{
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.sht = &piix_sht,
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@ -280,18 +310,15 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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},
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/* piix4_pata */
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/* i6300esb_sata */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SLAVE_POSS,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
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PIIX_FLAG_CHECKINTR,
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.pio_mask = 0x1f, /* pio0-4 */
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#if 0
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.mwdma_mask = 0x06, /* mwdma1-2 */
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#else
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.mwdma_mask = 0x00, /* mwdma broken */
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#endif
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.udma_mask = ATA_UDMA_MASK_40C,
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.port_ops = &piix_pata_ops,
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* ich6_sata */
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@ -316,6 +343,18 @@ static struct ata_port_info piix_port_info[] = {
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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/* ich6m_sata_ahci */
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{
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.sht = &piix_sht,
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.host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
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PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
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PIIX_FLAG_AHCI,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = 0x7f, /* udma0-6 */
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.port_ops = &piix_sata_ops,
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},
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};
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static struct pci_bits piix_enable_bits[] = {
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