cirrusfb: Laguna chipset 8bpp fix
Fix 8bpp mode by adding handling of the Laguna chipsets to various places and stop trashing a HDR register which probably does not exist on the Laguna. Fix compilation warnings about uninitialized variables also. Finally, all 8bpp, 16bpp and 32bpp modes work on the Laguna chipset. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Krzysztof Helt
Linus Torvalds
parent
48c329e906
commit
1b48cb563d
2 changed files with 21 additions and 14 deletions
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@ -660,7 +660,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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int yres, vdispend, vsyncstart, vsyncend, vtotal;
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long freq;
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int nom, den, div;
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unsigned int control, format, threshold;
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unsigned int control = 0, format = 0, threshold = 0;
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dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
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var->xres, var->yres, var->bits_per_pixel);
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@ -842,8 +842,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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threshold = fb_readw(cinfo->laguna_mmio + 0xea);
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control &= ~0x6800;
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format = 0;
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threshold &= 0xffe0;
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threshold &= 0x3fbf;
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threshold &= 0xffe0 & 0x3fbf;
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}
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if (nom) {
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tmp = den << 1;
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@ -893,6 +892,8 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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tmp |= 0x40;
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if (var->sync & FB_SYNC_VERT_HIGH_ACT)
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tmp |= 0x80;
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if (cinfo->btype == BT_LAGUNA)
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tmp |= 0xc;
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WGen(cinfo, VGA_MIS_W, tmp);
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/* Screen A Preset Row-Scan register */
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@ -1228,9 +1229,7 @@ static int cirrusfb_set_par_foo(struct fb_info *info)
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if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
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vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
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if (cinfo->btype == BT_LAGUNA ||
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cinfo->btype == BT_GD5480) {
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if (cinfo->btype == BT_LAGUNA) {
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tmp = 0;
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if ((htotal + 5) & 256)
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tmp |= 128;
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@ -1360,7 +1359,8 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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xpix = (unsigned char) ((xoffset % 4) * 2);
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}
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cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
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if (cinfo->btype != BT_LAGUNA)
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cirrusfb_WaitBLT(cinfo->regbase);
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/* lower 8 + 8 bits of screen start address */
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vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
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@ -1394,7 +1394,8 @@ static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
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if (info->var.bits_per_pixel == 1)
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vga_wattr(cinfo->regbase, CL_AR33, xpix);
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cirrusfb_WaitBLT(cinfo->regbase);
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if (cinfo->btype != BT_LAGUNA)
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cirrusfb_WaitBLT(cinfo->regbase);
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return 0;
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}
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@ -1513,6 +1514,7 @@ static void init_vgachip(struct fb_info *info)
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vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
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break;
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case BT_LAGUNA:
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case BT_ALPINE:
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/* Nothing to do to reset the board. */
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break;
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@ -1538,7 +1540,7 @@ static void init_vgachip(struct fb_info *info)
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WGen(cinfo, CL_VSSM2, 0x01);
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/* reset sequencer logic */
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vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
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vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
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/* FullBandwidth (video off) and 8/9 dot clock */
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vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
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@ -1560,6 +1562,7 @@ static void init_vgachip(struct fb_info *info)
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vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
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break;
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case BT_ALPINE:
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case BT_LAGUNA:
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break;
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case BT_SD64:
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vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
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@ -1648,7 +1651,8 @@ static void init_vgachip(struct fb_info *info)
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vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
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/* Bit Mask: no mask at all */
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vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
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if (cinfo->btype == BT_ALPINE)
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if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_LAGUNA)
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/* (5434 can't have bit 3 set for bitblt) */
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vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
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else
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@ -1845,7 +1849,8 @@ static void cirrusfb_imageblit(struct fb_info *info,
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{
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struct cirrusfb_info *cinfo = info->par;
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cirrusfb_WaitBLT(cinfo->regbase);
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if (cinfo->btype != BT_LAGUNA)
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cirrusfb_WaitBLT(cinfo->regbase);
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cfb_imageblit(info, image);
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}
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@ -1992,7 +1997,7 @@ static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
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| FBINFO_HWACCEL_YPAN
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| FBINFO_HWACCEL_FILLRECT
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| FBINFO_HWACCEL_COPYAREA;
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if (noaccel)
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if (noaccel || cinfo->btype == BT_LAGUNA)
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info->flags |= FBINFO_HWACCEL_DISABLED;
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info->fbops = &cirrusfb_ops;
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if (cinfo->btype == BT_GD5480) {
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@ -2481,6 +2486,8 @@ static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
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{
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unsigned char dummy;
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if (cinfo->btype == BT_LAGUNA)
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return;
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if (cinfo->btype == BT_PICASSO) {
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/* Klaus' hint for correct access to HDR on some boards */
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/* first write 0 to pixel mask (3c6) */
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@ -2548,7 +2555,8 @@ static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned ch
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vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
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if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
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cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
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cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
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cinfo->btype == BT_LAGUNA) {
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/* but DAC data register IS, at least for Picasso II */
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if (cinfo->btype == BT_PICASSO)
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data += 0xfff;
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@ -32,7 +32,6 @@
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#define CL_VSSM2 0x3c3 /* Motherboard Sleep */
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/*** VGA Sequencer Registers ***/
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#define CL_SEQR0 0x0 /* Reset */
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/* the following are from the "extension registers" group */
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#define CL_SEQR6 0x6 /* Unlock ALL Extensions */
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#define CL_SEQR7 0x7 /* Extended Sequencer Mode */
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