KVM: fix race with level interrupts
When more than 1 source id is in use for the same GSI, we have the following race related to handling irq_states race: CPU 0 clears bit 0. CPU 0 read irq_state as 0. CPU 1 sets level to 1. CPU 1 calls kvm_ioapic_set_irq(1). CPU 0 calls kvm_ioapic_set_irq(0). Now ioapic thinks the level is 0 but irq_state is not 0. Fix by performing all irq_states bitmap handling under pic/ioapic lock. This also removes the need for atomics with irq_states handling. Reported-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
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d63d3e6217
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1a577b7247
5 changed files with 51 additions and 35 deletions
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@ -816,7 +816,20 @@ int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
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void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault);
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bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
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int kvm_pic_set_irq(void *opaque, int irq, int level);
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static inline int __kvm_irq_line_state(unsigned long *irq_state,
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int irq_source_id, int level)
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{
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/* Logical OR for level trig interrupt */
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if (level)
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__set_bit(irq_source_id, irq_state);
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else
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__clear_bit(irq_source_id, irq_state);
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return !!(*irq_state);
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}
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int kvm_pic_set_irq(struct kvm_pic *pic, int irq, int irq_source_id, int level);
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void kvm_pic_clear_all(struct kvm_pic *pic, int irq_source_id);
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void kvm_inject_nmi(struct kvm_vcpu *vcpu);
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@ -188,14 +188,15 @@ void kvm_pic_update_irq(struct kvm_pic *s)
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pic_unlock(s);
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}
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int kvm_pic_set_irq(void *opaque, int irq, int level)
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int kvm_pic_set_irq(struct kvm_pic *s, int irq, int irq_source_id, int level)
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{
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struct kvm_pic *s = opaque;
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int ret = -1;
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pic_lock(s);
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if (irq >= 0 && irq < PIC_NUM_PINS) {
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ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
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int irq_level = __kvm_irq_line_state(&s->irq_states[irq],
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irq_source_id, level);
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ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, irq_level);
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pic_update_irq(s);
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trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
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s->pics[irq >> 3].imr, ret == 0);
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@ -205,6 +206,16 @@ int kvm_pic_set_irq(void *opaque, int irq, int level)
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return ret;
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}
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void kvm_pic_clear_all(struct kvm_pic *s, int irq_source_id)
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{
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int i;
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pic_lock(s);
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for (i = 0; i < PIC_NUM_PINS; i++)
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__clear_bit(irq_source_id, &s->irq_states[i]);
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pic_unlock(s);
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}
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/*
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* acknowledge interrupt 'irq'
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*/
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@ -191,7 +191,8 @@ static int ioapic_deliver(struct kvm_ioapic *ioapic, int irq)
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return kvm_irq_delivery_to_apic(ioapic->kvm, NULL, &irqe);
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}
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
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int level)
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{
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u32 old_irr;
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u32 mask = 1 << irq;
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@ -201,9 +202,11 @@ int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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spin_lock(&ioapic->lock);
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old_irr = ioapic->irr;
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if (irq >= 0 && irq < IOAPIC_NUM_PINS) {
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int irq_level = __kvm_irq_line_state(&ioapic->irq_states[irq],
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irq_source_id, level);
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entry = ioapic->redirtbl[irq];
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level ^= entry.fields.polarity;
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if (!level)
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irq_level ^= entry.fields.polarity;
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if (!irq_level)
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ioapic->irr &= ~mask;
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else {
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int edge = (entry.fields.trig_mode == IOAPIC_EDGE_TRIG);
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@ -221,6 +224,16 @@ int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level)
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return ret;
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}
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void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id)
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{
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int i;
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spin_lock(&ioapic->lock);
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for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++)
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__clear_bit(irq_source_id, &ioapic->irq_states[i]);
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spin_unlock(&ioapic->lock);
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}
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static void __kvm_ioapic_update_eoi(struct kvm_ioapic *ioapic, int vector,
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int trigger_mode)
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{
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@ -74,7 +74,9 @@ void kvm_ioapic_update_eoi(struct kvm *kvm, int vector, int trigger_mode);
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bool kvm_ioapic_handles_vector(struct kvm *kvm, int vector);
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int kvm_ioapic_init(struct kvm *kvm);
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void kvm_ioapic_destroy(struct kvm *kvm);
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
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int kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int irq_source_id,
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int level);
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void kvm_ioapic_clear_all(struct kvm_ioapic *ioapic, int irq_source_id);
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void kvm_ioapic_reset(struct kvm_ioapic *ioapic);
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int kvm_irq_delivery_to_apic(struct kvm *kvm, struct kvm_lapic *src,
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struct kvm_lapic_irq *irq);
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@ -33,26 +33,12 @@
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#include "ioapic.h"
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static inline int kvm_irq_line_state(unsigned long *irq_state,
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int irq_source_id, int level)
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{
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/* Logical OR for level trig interrupt */
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if (level)
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set_bit(irq_source_id, irq_state);
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else
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clear_bit(irq_source_id, irq_state);
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return !!(*irq_state);
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}
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static int kvm_set_pic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level)
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{
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#ifdef CONFIG_X86
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struct kvm_pic *pic = pic_irqchip(kvm);
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level = kvm_irq_line_state(&pic->irq_states[e->irqchip.pin],
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irq_source_id, level);
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return kvm_pic_set_irq(pic, e->irqchip.pin, level);
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return kvm_pic_set_irq(pic, e->irqchip.pin, irq_source_id, level);
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#else
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return -1;
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#endif
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@ -62,10 +48,7 @@ static int kvm_set_ioapic_irq(struct kvm_kernel_irq_routing_entry *e,
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struct kvm *kvm, int irq_source_id, int level)
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{
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struct kvm_ioapic *ioapic = kvm->arch.vioapic;
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level = kvm_irq_line_state(&ioapic->irq_states[e->irqchip.pin],
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irq_source_id, level);
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return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, level);
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return kvm_ioapic_set_irq(ioapic, e->irqchip.pin, irq_source_id, level);
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}
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inline static bool kvm_is_dm_lowest_prio(struct kvm_lapic_irq *irq)
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@ -249,8 +232,6 @@ int kvm_request_irq_source_id(struct kvm *kvm)
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void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
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{
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int i;
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ASSERT(irq_source_id != KVM_USERSPACE_IRQ_SOURCE_ID);
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mutex_lock(&kvm->irq_lock);
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@ -263,14 +244,10 @@ void kvm_free_irq_source_id(struct kvm *kvm, int irq_source_id)
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if (!irqchip_in_kernel(kvm))
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goto unlock;
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for (i = 0; i < KVM_IOAPIC_NUM_PINS; i++) {
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clear_bit(irq_source_id, &kvm->arch.vioapic->irq_states[i]);
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if (i >= 16)
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continue;
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kvm_ioapic_clear_all(kvm->arch.vioapic, irq_source_id);
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#ifdef CONFIG_X86
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clear_bit(irq_source_id, &pic_irqchip(kvm)->irq_states[i]);
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kvm_pic_clear_all(pic_irqchip(kvm), irq_source_id);
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#endif
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}
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unlock:
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mutex_unlock(&kvm->irq_lock);
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}
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