sudmac: add support for SUDMAC
Some Renesas USB modules have SUDMAC. This patch supports it using the shdma-base driver. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Shimoda, Yoshihiro
Vinod Koul
parent
189b4ee8e9
commit
18a1053f7b
4 changed files with 487 additions and 0 deletions
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@ -16,3 +16,9 @@ config SH_DMAE
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depends on SH_DMAE_BASE
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help
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Enable support for the Renesas SuperH DMA controllers.
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config SUDMAC
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tristate "Renesas SUDMAC support"
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depends on SH_DMAE_BASE
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help
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Enable support for the Renesas SUDMAC controllers.
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@ -1,2 +1,3 @@
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obj-$(CONFIG_SH_DMAE_BASE) += shdma-base.o
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obj-$(CONFIG_SH_DMAE) += shdma.o
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obj-$(CONFIG_SUDMAC) += sudmac.o
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428
drivers/dma/sh/sudmac.c
Normal file
428
drivers/dma/sh/sudmac.c
Normal file
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@ -0,0 +1,428 @@
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/*
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* Renesas SUDMAC support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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*
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* based on drivers/dma/sh/shdma.c:
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* Copyright (C) 2011-2012 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
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* Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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* Copyright (C) 2009 Renesas Solutions, Inc. All rights reserved.
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* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
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*
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* This is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/sudmac.h>
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struct sudmac_chan {
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struct shdma_chan shdma_chan;
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void __iomem *base;
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char dev_id[16]; /* unique name per DMAC of channel */
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u32 offset; /* for CFG, BA, BBC, CA, CBC, DEN */
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u32 cfg;
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u32 dint_end_bit;
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};
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struct sudmac_device {
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struct shdma_dev shdma_dev;
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struct sudmac_pdata *pdata;
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void __iomem *chan_reg;
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};
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struct sudmac_regs {
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u32 base_addr;
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u32 base_byte_count;
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};
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struct sudmac_desc {
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struct sudmac_regs hw;
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struct shdma_desc shdma_desc;
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};
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#define to_chan(schan) container_of(schan, struct sudmac_chan, shdma_chan)
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#define to_desc(sdesc) container_of(sdesc, struct sudmac_desc, shdma_desc)
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#define to_sdev(sc) container_of(sc->shdma_chan.dma_chan.device, \
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struct sudmac_device, shdma_dev.dma_dev)
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/* SUDMAC register */
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#define SUDMAC_CH0CFG 0x00
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#define SUDMAC_CH0BA 0x10
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#define SUDMAC_CH0BBC 0x18
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#define SUDMAC_CH0CA 0x20
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#define SUDMAC_CH0CBC 0x28
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#define SUDMAC_CH0DEN 0x30
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#define SUDMAC_DSTSCLR 0x38
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#define SUDMAC_DBUFCTRL 0x3C
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#define SUDMAC_DINTCTRL 0x40
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#define SUDMAC_DINTSTS 0x44
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#define SUDMAC_DINTSTSCLR 0x48
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#define SUDMAC_CH0SHCTRL 0x50
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/* Definitions for the sudmac_channel.config */
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#define SUDMAC_SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
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#define SUDMAC_RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
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#define SUDMAC_LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */
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/* Definitions for the sudmac_channel.dint_end_bit */
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#define SUDMAC_CH1ENDE 0x0002 /* b1: Ch1 DMA Transfer End Int Enable */
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#define SUDMAC_CH0ENDE 0x0001 /* b0: Ch0 DMA Transfer End Int Enable */
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#define SUDMAC_DRV_NAME "sudmac"
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static void sudmac_writel(struct sudmac_chan *sc, u32 data, u32 reg)
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{
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iowrite32(data, sc->base + reg);
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}
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static u32 sudmac_readl(struct sudmac_chan *sc, u32 reg)
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{
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return ioread32(sc->base + reg);
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}
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static bool sudmac_is_busy(struct sudmac_chan *sc)
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{
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u32 den = sudmac_readl(sc, SUDMAC_CH0DEN + sc->offset);
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if (den)
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return true; /* working */
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return false; /* waiting */
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}
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static void sudmac_set_reg(struct sudmac_chan *sc, struct sudmac_regs *hw,
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struct shdma_desc *sdesc)
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{
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sudmac_writel(sc, sc->cfg, SUDMAC_CH0CFG + sc->offset);
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sudmac_writel(sc, hw->base_addr, SUDMAC_CH0BA + sc->offset);
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sudmac_writel(sc, hw->base_byte_count, SUDMAC_CH0BBC + sc->offset);
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}
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static void sudmac_start(struct sudmac_chan *sc)
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{
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u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
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sudmac_writel(sc, dintctrl | sc->dint_end_bit, SUDMAC_DINTCTRL);
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sudmac_writel(sc, 1, SUDMAC_CH0DEN + sc->offset);
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}
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static void sudmac_start_xfer(struct shdma_chan *schan,
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struct shdma_desc *sdesc)
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{
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struct sudmac_chan *sc = to_chan(schan);
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struct sudmac_desc *sd = to_desc(sdesc);
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sudmac_set_reg(sc, &sd->hw, sdesc);
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sudmac_start(sc);
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}
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static bool sudmac_channel_busy(struct shdma_chan *schan)
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{
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struct sudmac_chan *sc = to_chan(schan);
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return sudmac_is_busy(sc);
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}
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static void sudmac_setup_xfer(struct shdma_chan *schan, int slave_id)
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{
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}
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static const struct sudmac_slave_config *sudmac_find_slave(
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struct sudmac_chan *sc, int slave_id)
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{
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struct sudmac_device *sdev = to_sdev(sc);
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struct sudmac_pdata *pdata = sdev->pdata;
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const struct sudmac_slave_config *cfg;
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int i;
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for (i = 0, cfg = pdata->slave; i < pdata->slave_num; i++, cfg++)
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if (cfg->slave_id == slave_id)
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return cfg;
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return NULL;
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}
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static int sudmac_set_slave(struct shdma_chan *schan, int slave_id, bool try)
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{
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struct sudmac_chan *sc = to_chan(schan);
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const struct sudmac_slave_config *cfg = sudmac_find_slave(sc, slave_id);
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if (!cfg)
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return -ENODEV;
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return 0;
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}
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static inline void sudmac_dma_halt(struct sudmac_chan *sc)
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{
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u32 dintctrl = sudmac_readl(sc, SUDMAC_DINTCTRL);
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sudmac_writel(sc, 0, SUDMAC_CH0DEN + sc->offset);
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sudmac_writel(sc, dintctrl & ~sc->dint_end_bit, SUDMAC_DINTCTRL);
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sudmac_writel(sc, sc->dint_end_bit, SUDMAC_DINTSTSCLR);
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}
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static int sudmac_desc_setup(struct shdma_chan *schan,
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struct shdma_desc *sdesc,
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dma_addr_t src, dma_addr_t dst, size_t *len)
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{
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struct sudmac_chan *sc = to_chan(schan);
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struct sudmac_desc *sd = to_desc(sdesc);
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dev_dbg(sc->shdma_chan.dev, "%s: src=%x, dst=%x, len=%d\n",
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__func__, src, dst, *len);
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if (*len > schan->max_xfer_len)
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*len = schan->max_xfer_len;
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if (dst)
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sd->hw.base_addr = dst;
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else if (src)
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sd->hw.base_addr = src;
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sd->hw.base_byte_count = *len;
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return 0;
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}
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static void sudmac_halt(struct shdma_chan *schan)
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{
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struct sudmac_chan *sc = to_chan(schan);
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sudmac_dma_halt(sc);
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}
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static bool sudmac_chan_irq(struct shdma_chan *schan, int irq)
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{
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struct sudmac_chan *sc = to_chan(schan);
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u32 dintsts = sudmac_readl(sc, SUDMAC_DINTSTS);
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if (!(dintsts & sc->dint_end_bit))
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return false;
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/* DMA stop */
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sudmac_dma_halt(sc);
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return true;
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}
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static size_t sudmac_get_partial(struct shdma_chan *schan,
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struct shdma_desc *sdesc)
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{
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struct sudmac_chan *sc = to_chan(schan);
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struct sudmac_desc *sd = to_desc(sdesc);
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u32 current_byte_count = sudmac_readl(sc, SUDMAC_CH0CBC + sc->offset);
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return sd->hw.base_byte_count - current_byte_count;
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}
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static bool sudmac_desc_completed(struct shdma_chan *schan,
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struct shdma_desc *sdesc)
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{
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struct sudmac_chan *sc = to_chan(schan);
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struct sudmac_desc *sd = to_desc(sdesc);
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u32 current_addr = sudmac_readl(sc, SUDMAC_CH0CA + sc->offset);
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return sd->hw.base_addr + sd->hw.base_byte_count == current_addr;
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}
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static int sudmac_chan_probe(struct sudmac_device *su_dev, int id, int irq,
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unsigned long flags)
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{
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struct shdma_dev *sdev = &su_dev->shdma_dev;
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struct platform_device *pdev = to_platform_device(sdev->dma_dev.dev);
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struct sudmac_chan *sc;
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struct shdma_chan *schan;
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int err;
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sc = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_chan), GFP_KERNEL);
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if (!sc) {
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dev_err(sdev->dma_dev.dev,
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"No free memory for allocating dma channels!\n");
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return -ENOMEM;
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}
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schan = &sc->shdma_chan;
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schan->max_xfer_len = 64 * 1024 * 1024 - 1;
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shdma_chan_probe(sdev, schan, id);
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sc->base = su_dev->chan_reg;
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/* get platform_data */
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sc->offset = su_dev->pdata->channel->offset;
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if (su_dev->pdata->channel->config & SUDMAC_TX_BUFFER_MODE)
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sc->cfg |= SUDMAC_SENDBUFM;
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if (su_dev->pdata->channel->config & SUDMAC_RX_END_MODE)
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sc->cfg |= SUDMAC_RCVENDM;
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sc->cfg |= (su_dev->pdata->channel->wait << 4) & SUDMAC_LBA_WAIT;
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if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH0)
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sc->dint_end_bit |= SUDMAC_CH0ENDE;
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if (su_dev->pdata->channel->dint_end_bit & SUDMAC_DMA_BIT_CH1)
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sc->dint_end_bit |= SUDMAC_CH1ENDE;
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/* set up channel irq */
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if (pdev->id >= 0)
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snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d.%d",
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pdev->id, id);
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else
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snprintf(sc->dev_id, sizeof(sc->dev_id), "sudmac%d", id);
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err = shdma_request_irq(schan, irq, flags, sc->dev_id);
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if (err) {
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dev_err(sdev->dma_dev.dev,
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"DMA channel %d request_irq failed %d\n", id, err);
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goto err_no_irq;
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}
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return 0;
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err_no_irq:
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/* remove from dmaengine device node */
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shdma_chan_remove(schan);
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return err;
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}
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static void sudmac_chan_remove(struct sudmac_device *su_dev)
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{
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struct dma_device *dma_dev = &su_dev->shdma_dev.dma_dev;
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struct shdma_chan *schan;
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int i;
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shdma_for_each_chan(schan, &su_dev->shdma_dev, i) {
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struct sudmac_chan *sc = to_chan(schan);
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BUG_ON(!schan);
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shdma_free_irq(&sc->shdma_chan);
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shdma_chan_remove(schan);
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}
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dma_dev->chancnt = 0;
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}
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static dma_addr_t sudmac_slave_addr(struct shdma_chan *schan)
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{
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/* SUDMAC doesn't need the address */
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return 0;
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}
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static struct shdma_desc *sudmac_embedded_desc(void *buf, int i)
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{
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return &((struct sudmac_desc *)buf)[i].shdma_desc;
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}
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static const struct shdma_ops sudmac_shdma_ops = {
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.desc_completed = sudmac_desc_completed,
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.halt_channel = sudmac_halt,
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.channel_busy = sudmac_channel_busy,
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.slave_addr = sudmac_slave_addr,
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.desc_setup = sudmac_desc_setup,
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.set_slave = sudmac_set_slave,
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.setup_xfer = sudmac_setup_xfer,
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.start_xfer = sudmac_start_xfer,
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.embedded_desc = sudmac_embedded_desc,
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.chan_irq = sudmac_chan_irq,
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.get_partial = sudmac_get_partial,
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};
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static int sudmac_probe(struct platform_device *pdev)
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{
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struct sudmac_pdata *pdata = pdev->dev.platform_data;
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int err, i;
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struct sudmac_device *su_dev;
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struct dma_device *dma_dev;
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struct resource *chan, *irq_res;
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/* get platform data */
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if (!pdata)
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return -ENODEV;
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chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
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if (!chan || !irq_res)
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return -ENODEV;
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err = -ENOMEM;
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su_dev = devm_kzalloc(&pdev->dev, sizeof(struct sudmac_device),
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GFP_KERNEL);
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if (!su_dev) {
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dev_err(&pdev->dev, "Not enough memory\n");
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return err;
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}
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dma_dev = &su_dev->shdma_dev.dma_dev;
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su_dev->chan_reg = devm_request_and_ioremap(&pdev->dev, chan);
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if (!su_dev->chan_reg)
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return err;
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dma_cap_set(DMA_SLAVE, dma_dev->cap_mask);
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su_dev->shdma_dev.ops = &sudmac_shdma_ops;
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su_dev->shdma_dev.desc_size = sizeof(struct sudmac_desc);
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err = shdma_init(&pdev->dev, &su_dev->shdma_dev, pdata->channel_num);
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if (err < 0)
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return err;
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/* platform data */
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su_dev->pdata = pdev->dev.platform_data;
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platform_set_drvdata(pdev, su_dev);
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/* Create DMA Channel */
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for (i = 0; i < pdata->channel_num; i++) {
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err = sudmac_chan_probe(su_dev, i, irq_res->start, IRQF_SHARED);
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if (err)
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goto chan_probe_err;
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}
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err = dma_async_device_register(&su_dev->shdma_dev.dma_dev);
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if (err < 0)
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goto chan_probe_err;
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return err;
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chan_probe_err:
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sudmac_chan_remove(su_dev);
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platform_set_drvdata(pdev, NULL);
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shdma_cleanup(&su_dev->shdma_dev);
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return err;
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}
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static int sudmac_remove(struct platform_device *pdev)
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{
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struct sudmac_device *su_dev = platform_get_drvdata(pdev);
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struct dma_device *dma_dev = &su_dev->shdma_dev.dma_dev;
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dma_async_device_unregister(dma_dev);
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sudmac_chan_remove(su_dev);
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shdma_cleanup(&su_dev->shdma_dev);
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platform_set_drvdata(pdev, NULL);
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return 0;
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}
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static struct platform_driver sudmac_driver = {
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.driver = {
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.owner = THIS_MODULE,
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.name = SUDMAC_DRV_NAME,
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},
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.probe = sudmac_probe,
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.remove = sudmac_remove,
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};
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module_platform_driver(sudmac_driver);
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MODULE_AUTHOR("Yoshihiro Shimoda");
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MODULE_DESCRIPTION("Renesas SUDMAC driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:" SUDMAC_DRV_NAME);
|
||||
52
include/linux/sudmac.h
Normal file
52
include/linux/sudmac.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Header for the SUDMAC driver
|
||||
*
|
||||
* Copyright (C) 2013 Renesas Solutions Corp.
|
||||
*
|
||||
* This is free software; you can redistribute it and/or modify
|
||||
* it under the terms of version 2 of the GNU General Public License as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#ifndef SUDMAC_H
|
||||
#define SUDMAC_H
|
||||
|
||||
#include <linux/dmaengine.h>
|
||||
#include <linux/shdma-base.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Used by slave DMA clients to request DMA to/from a specific peripheral */
|
||||
struct sudmac_slave {
|
||||
struct shdma_slave shdma_slave; /* Set by the platform */
|
||||
};
|
||||
|
||||
/*
|
||||
* Supplied by platforms to specify, how a DMA channel has to be configured for
|
||||
* a certain peripheral
|
||||
*/
|
||||
struct sudmac_slave_config {
|
||||
int slave_id;
|
||||
};
|
||||
|
||||
struct sudmac_channel {
|
||||
unsigned long offset;
|
||||
unsigned long config;
|
||||
unsigned long wait; /* The configuable range is 0 to 3 */
|
||||
unsigned long dint_end_bit;
|
||||
};
|
||||
|
||||
struct sudmac_pdata {
|
||||
const struct sudmac_slave_config *slave;
|
||||
int slave_num;
|
||||
const struct sudmac_channel *channel;
|
||||
int channel_num;
|
||||
};
|
||||
|
||||
/* Definitions for the sudmac_channel.config */
|
||||
#define SUDMAC_TX_BUFFER_MODE BIT(0)
|
||||
#define SUDMAC_RX_END_MODE BIT(1)
|
||||
|
||||
/* Definitions for the sudmac_channel.dint_end_bit */
|
||||
#define SUDMAC_DMA_BIT_CH0 BIT(0)
|
||||
#define SUDMAC_DMA_BIT_CH1 BIT(1)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue