clk: axi-clkgen: Add support for v2
This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen
Mike Turquette
parent
62ac983b61
commit
1887c3a64f
2 changed files with 269 additions and 43 deletions
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@ -5,7 +5,7 @@ This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "adi,axi-clkgen".
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- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
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- #clock-cells : from common clock binding; Should always be set to 0.
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- reg : Address and length of the axi-clkgen register set.
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- clocks : Phandle and clock specifier for the parent clock.
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@ -17,23 +17,75 @@
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#include <linux/module.h>
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#include <linux/err.h>
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#define AXI_CLKGEN_REG_UPDATE_ENABLE 0x04
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#define AXI_CLKGEN_REG_CLK_OUT1 0x08
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#define AXI_CLKGEN_REG_CLK_OUT2 0x0c
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#define AXI_CLKGEN_REG_CLK_DIV 0x10
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#define AXI_CLKGEN_REG_CLK_FB1 0x14
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#define AXI_CLKGEN_REG_CLK_FB2 0x18
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#define AXI_CLKGEN_REG_LOCK1 0x1c
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#define AXI_CLKGEN_REG_LOCK2 0x20
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#define AXI_CLKGEN_REG_LOCK3 0x24
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#define AXI_CLKGEN_REG_FILTER1 0x28
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#define AXI_CLKGEN_REG_FILTER2 0x2c
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#define AXI_CLKGEN_V1_REG_UPDATE_ENABLE 0x04
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#define AXI_CLKGEN_V1_REG_CLK_OUT1 0x08
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#define AXI_CLKGEN_V1_REG_CLK_OUT2 0x0c
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#define AXI_CLKGEN_V1_REG_CLK_DIV 0x10
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#define AXI_CLKGEN_V1_REG_CLK_FB1 0x14
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#define AXI_CLKGEN_V1_REG_CLK_FB2 0x18
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#define AXI_CLKGEN_V1_REG_LOCK1 0x1c
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#define AXI_CLKGEN_V1_REG_LOCK2 0x20
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#define AXI_CLKGEN_V1_REG_LOCK3 0x24
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#define AXI_CLKGEN_V1_REG_FILTER1 0x28
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#define AXI_CLKGEN_V1_REG_FILTER2 0x2c
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#define AXI_CLKGEN_V2_REG_RESET 0x40
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#define AXI_CLKGEN_V2_REG_DRP_CNTRL 0x70
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#define AXI_CLKGEN_V2_REG_DRP_STATUS 0x74
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#define AXI_CLKGEN_V2_RESET_MMCM_ENABLE BIT(1)
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#define AXI_CLKGEN_V2_RESET_ENABLE BIT(0)
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#define AXI_CLKGEN_V2_DRP_CNTRL_SEL BIT(29)
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#define AXI_CLKGEN_V2_DRP_CNTRL_READ BIT(28)
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#define AXI_CLKGEN_V2_DRP_STATUS_BUSY BIT(16)
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#define MMCM_REG_CLKOUT0_1 0x08
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#define MMCM_REG_CLKOUT0_2 0x09
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#define MMCM_REG_CLK_FB1 0x14
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#define MMCM_REG_CLK_FB2 0x15
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#define MMCM_REG_CLK_DIV 0x16
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#define MMCM_REG_LOCK1 0x18
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#define MMCM_REG_LOCK2 0x19
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#define MMCM_REG_LOCK3 0x1a
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#define MMCM_REG_FILTER1 0x4e
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#define MMCM_REG_FILTER2 0x4f
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struct axi_clkgen;
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struct axi_clkgen_mmcm_ops {
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void (*enable)(struct axi_clkgen *axi_clkgen, bool enable);
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int (*write)(struct axi_clkgen *axi_clkgen, unsigned int reg,
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unsigned int val, unsigned int mask);
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int (*read)(struct axi_clkgen *axi_clkgen, unsigned int reg,
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unsigned int *val);
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};
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struct axi_clkgen {
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void __iomem *base;
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const struct axi_clkgen_mmcm_ops *mmcm_ops;
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struct clk_hw clk_hw;
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};
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static void axi_clkgen_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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axi_clkgen->mmcm_ops->enable(axi_clkgen, enable);
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}
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static int axi_clkgen_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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return axi_clkgen->mmcm_ops->write(axi_clkgen, reg, val, mask);
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}
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static int axi_clkgen_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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return axi_clkgen->mmcm_ops->read(axi_clkgen, reg, val);
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}
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static uint32_t axi_clkgen_lookup_filter(unsigned int m)
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{
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switch (m) {
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@ -156,6 +208,148 @@ static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
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*val = readl(axi_clkgen->base + reg);
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}
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static unsigned int axi_clkgen_v1_map_mmcm_reg(unsigned int reg)
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{
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switch (reg) {
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case MMCM_REG_CLKOUT0_1:
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return AXI_CLKGEN_V1_REG_CLK_OUT1;
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case MMCM_REG_CLKOUT0_2:
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return AXI_CLKGEN_V1_REG_CLK_OUT2;
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case MMCM_REG_CLK_FB1:
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return AXI_CLKGEN_V1_REG_CLK_FB1;
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case MMCM_REG_CLK_FB2:
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return AXI_CLKGEN_V1_REG_CLK_FB2;
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case MMCM_REG_CLK_DIV:
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return AXI_CLKGEN_V1_REG_CLK_DIV;
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case MMCM_REG_LOCK1:
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return AXI_CLKGEN_V1_REG_LOCK1;
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case MMCM_REG_LOCK2:
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return AXI_CLKGEN_V1_REG_LOCK2;
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case MMCM_REG_LOCK3:
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return AXI_CLKGEN_V1_REG_LOCK3;
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case MMCM_REG_FILTER1:
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return AXI_CLKGEN_V1_REG_FILTER1;
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case MMCM_REG_FILTER2:
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return AXI_CLKGEN_V1_REG_FILTER2;
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default:
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return 0;
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}
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}
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static int axi_clkgen_v1_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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reg = axi_clkgen_v1_map_mmcm_reg(reg);
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if (reg == 0)
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return -EINVAL;
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axi_clkgen_write(axi_clkgen, reg, val);
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return 0;
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}
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static int axi_clkgen_v1_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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reg = axi_clkgen_v1_map_mmcm_reg(reg);
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if (reg == 0)
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return -EINVAL;
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axi_clkgen_read(axi_clkgen, reg, val);
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return 0;
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}
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static void axi_clkgen_v1_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V1_REG_UPDATE_ENABLE, enable);
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}
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static const struct axi_clkgen_mmcm_ops axi_clkgen_v1_mmcm_ops = {
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.write = axi_clkgen_v1_mmcm_write,
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.read = axi_clkgen_v1_mmcm_read,
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.enable = axi_clkgen_v1_mmcm_enable,
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};
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static int axi_clkgen_wait_non_busy(struct axi_clkgen *axi_clkgen)
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{
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unsigned int timeout = 10000;
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unsigned int val;
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do {
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_STATUS, &val);
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} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
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if (val & AXI_CLKGEN_V2_DRP_STATUS_BUSY)
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return -EIO;
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return val & 0xffff;
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}
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static int axi_clkgen_v2_mmcm_read(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int *val)
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{
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unsigned int reg_val;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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reg_val = AXI_CLKGEN_V2_DRP_CNTRL_SEL | AXI_CLKGEN_V2_DRP_CNTRL_READ;
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reg_val |= (reg << 16);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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*val = ret;
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return 0;
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}
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static int axi_clkgen_v2_mmcm_write(struct axi_clkgen *axi_clkgen,
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unsigned int reg, unsigned int val, unsigned int mask)
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{
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unsigned int reg_val = 0;
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int ret;
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ret = axi_clkgen_wait_non_busy(axi_clkgen);
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if (ret < 0)
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return ret;
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if (mask != 0xffff) {
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axi_clkgen_v2_mmcm_read(axi_clkgen, reg, ®_val);
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reg_val &= ~mask;
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}
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reg_val |= AXI_CLKGEN_V2_DRP_CNTRL_SEL | (reg << 16) | (val & mask);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_DRP_CNTRL, reg_val);
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return 0;
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}
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static void axi_clkgen_v2_mmcm_enable(struct axi_clkgen *axi_clkgen,
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bool enable)
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{
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unsigned int val = AXI_CLKGEN_V2_RESET_ENABLE;
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if (enable)
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val |= AXI_CLKGEN_V2_RESET_MMCM_ENABLE;
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_V2_REG_RESET, val);
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}
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static const struct axi_clkgen_mmcm_ops axi_clkgen_v2_mmcm_ops = {
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.write = axi_clkgen_v2_mmcm_write,
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.read = axi_clkgen_v2_mmcm_read,
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.enable = axi_clkgen_v2_mmcm_enable,
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};
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static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
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{
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return container_of(clk_hw, struct axi_clkgen, clk_hw);
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@ -184,33 +378,29 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
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filter = axi_clkgen_lookup_filter(m - 1);
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lock = axi_clkgen_lookup_lock(m - 1);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 0);
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axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1,
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(high << 6) | low);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT2,
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(edge << 7) | (nocount << 6));
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_1,
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(high << 6) | low, 0xefff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLKOUT0_2,
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(edge << 7) | (nocount << 6), 0x03ff);
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axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV,
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(edge << 13) | (nocount << 12) | (high << 6) | low);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_DIV,
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(edge << 13) | (nocount << 12) | (high << 6) | low, 0x3fff);
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axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1,
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(high << 6) | low);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB2,
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(edge << 7) | (nocount << 6));
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB1,
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(high << 6) | low, 0xefff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_CLK_FB2,
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(edge << 7) | (nocount << 6), 0x03ff);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK1, lock & 0x3ff);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK2,
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(((lock >> 16) & 0x1f) << 10) | 0x1);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK3,
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(((lock >> 24) & 0x1f) << 10) | 0x3e9);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER1, filter >> 16);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER2, filter);
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axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 1);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK1, lock & 0x3ff, 0x3ff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK2,
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(((lock >> 16) & 0x1f) << 10) | 0x1, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_LOCK3,
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(((lock >> 24) & 0x1f) << 10) | 0x3e9, 0x7fff);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER1, filter >> 16, 0x9900);
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axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_FILTER2, filter, 0x9900);
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return 0;
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}
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@ -236,11 +426,11 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
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unsigned int reg;
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unsigned long long tmp;
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1, ®);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLKOUT0_1, ®);
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dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV, ®);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_DIV, ®);
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d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1, ®);
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axi_clkgen_mmcm_read(axi_clkgen, MMCM_REG_CLK_FB1, ®);
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m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
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if (d == 0 || dout == 0)
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@ -255,14 +445,45 @@ static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
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return tmp;
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}
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static int axi_clkgen_enable(struct clk_hw *clk_hw)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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axi_clkgen_mmcm_enable(axi_clkgen, true);
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return 0;
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}
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static void axi_clkgen_disable(struct clk_hw *clk_hw)
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{
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struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
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axi_clkgen_mmcm_enable(axi_clkgen, false);
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}
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static const struct clk_ops axi_clkgen_ops = {
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.recalc_rate = axi_clkgen_recalc_rate,
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.round_rate = axi_clkgen_round_rate,
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.set_rate = axi_clkgen_set_rate,
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.enable = axi_clkgen_enable,
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.disable = axi_clkgen_disable,
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};
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static const struct of_device_id axi_clkgen_ids[] = {
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{
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.compatible = "adi,axi-clkgen-1.00.a",
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.data = &axi_clkgen_v1_mmcm_ops
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}, {
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.compatible = "adi,axi-clkgen-2.00.a",
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.data = &axi_clkgen_v2_mmcm_ops,
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},
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{ },
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};
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MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
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static int axi_clkgen_probe(struct platform_device *pdev)
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{
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const struct of_device_id *id;
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struct axi_clkgen *axi_clkgen;
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struct clk_init_data init;
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const char *parent_name;
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@ -270,10 +491,19 @@ static int axi_clkgen_probe(struct platform_device *pdev)
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struct resource *mem;
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struct clk *clk;
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if (!pdev->dev.of_node)
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return -ENODEV;
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id = of_match_node(axi_clkgen_ids, pdev->dev.of_node);
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if (!id)
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return -ENODEV;
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axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
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if (!axi_clkgen)
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return -ENOMEM;
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axi_clkgen->mmcm_ops = id->data;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(axi_clkgen->base))
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@ -289,10 +519,12 @@ static int axi_clkgen_probe(struct platform_device *pdev)
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init.name = clk_name;
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init.ops = &axi_clkgen_ops;
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init.flags = 0;
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init.flags = CLK_SET_RATE_GATE;
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init.parent_names = &parent_name;
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init.num_parents = 1;
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axi_clkgen_mmcm_enable(axi_clkgen, false);
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axi_clkgen->clk_hw.init = &init;
|
||||
clk = devm_clk_register(&pdev->dev, &axi_clkgen->clk_hw);
|
||||
if (IS_ERR(clk))
|
||||
|
|
@ -309,12 +541,6 @@ static int axi_clkgen_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct of_device_id axi_clkgen_ids[] = {
|
||||
{ .compatible = "adi,axi-clkgen-1.00.a" },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
|
||||
|
||||
static struct platform_driver axi_clkgen_driver = {
|
||||
.driver = {
|
||||
.name = "adi-axi-clkgen",
|
||||
|
|
|
|||
Loading…
Reference in a new issue