drm/vc4: add HDMI CEC support
This patch adds support to VC4 for CEC. It is under a separate Kconfig option to keep everyone using VC4 from needing to pull in the CEC core. Thanks to Eric Anholt for providing me with the CEC register information. Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Eric Anholt <eric@anholt.net> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/20170716104804.48308-4-hverkuil@xs4all.nl
This commit is contained in:
Hans Verkuil
Eric Anholt
parent
10ee275cb1
commit
15b4511a4a
3 changed files with 345 additions and 6 deletions
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@ -19,3 +19,11 @@ config DRM_VC4
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This driver requires that "avoid_warnings=2" be present in
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the config.txt for the firmware, to keep it from smashing
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our display setup.
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config DRM_VC4_HDMI_CEC
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bool "Broadcom VC4 HDMI CEC Support"
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depends on DRM_VC4
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select CEC_CORE
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help
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Choose this option if you have a Broadcom VC4 GPU
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and want to use CEC.
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@ -57,9 +57,14 @@
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#include <sound/pcm_drm_eld.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include "media/cec.h"
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#include "vc4_drv.h"
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#include "vc4_regs.h"
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#define HSM_CLOCK_FREQ 163682864
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#define CEC_CLOCK_FREQ 40000
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#define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ)
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/* HDMI audio information */
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struct vc4_hdmi_audio {
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struct snd_soc_card card;
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@ -85,6 +90,11 @@ struct vc4_hdmi {
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int hpd_gpio;
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bool hpd_active_low;
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struct cec_adapter *cec_adap;
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struct cec_msg cec_rx_msg;
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bool cec_tx_ok;
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bool cec_irq_was_rx;
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struct clk *pixel_clock;
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struct clk *hsm_clock;
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};
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@ -149,6 +159,23 @@ static const struct {
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HDMI_REG(VC4_HDMI_VERTB1),
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HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
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HDMI_REG(VC4_HDMI_TX_PHY_CTL0),
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HDMI_REG(VC4_HDMI_CEC_CNTRL_1),
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HDMI_REG(VC4_HDMI_CEC_CNTRL_2),
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HDMI_REG(VC4_HDMI_CEC_CNTRL_3),
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HDMI_REG(VC4_HDMI_CEC_CNTRL_4),
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HDMI_REG(VC4_HDMI_CEC_CNTRL_5),
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HDMI_REG(VC4_HDMI_CPU_STATUS),
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HDMI_REG(VC4_HDMI_CPU_MASK_STATUS),
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HDMI_REG(VC4_HDMI_CEC_RX_DATA_1),
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HDMI_REG(VC4_HDMI_CEC_RX_DATA_2),
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HDMI_REG(VC4_HDMI_CEC_RX_DATA_3),
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HDMI_REG(VC4_HDMI_CEC_RX_DATA_4),
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HDMI_REG(VC4_HDMI_CEC_TX_DATA_1),
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HDMI_REG(VC4_HDMI_CEC_TX_DATA_2),
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HDMI_REG(VC4_HDMI_CEC_TX_DATA_3),
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HDMI_REG(VC4_HDMI_CEC_TX_DATA_4),
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};
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static const struct {
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@ -216,7 +243,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
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if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
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vc4->hdmi->hpd_active_low)
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return connector_status_connected;
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else
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cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
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return connector_status_disconnected;
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}
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@ -225,7 +252,7 @@ vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
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if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
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return connector_status_connected;
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else
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cec_phys_addr_invalidate(vc4->hdmi->cec_adap);
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return connector_status_disconnected;
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}
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@ -247,6 +274,7 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
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struct edid *edid;
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edid = drm_get_edid(connector, vc4->hdmi->ddc);
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cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid);
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if (!edid)
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return -ENODEV;
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@ -1121,6 +1149,159 @@ static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi)
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snd_soc_unregister_codec(dev);
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}
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#ifdef CONFIG_DRM_VC4_HDMI_CEC
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static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
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{
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struct vc4_dev *vc4 = priv;
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struct vc4_hdmi *hdmi = vc4->hdmi;
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if (hdmi->cec_irq_was_rx) {
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if (hdmi->cec_rx_msg.len)
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cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg);
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} else if (hdmi->cec_tx_ok) {
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cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK,
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0, 0, 0, 0);
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} else {
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/*
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* This CEC implementation makes 1 retry, so if we
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* get a NACK, then that means it made 2 attempts.
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*/
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cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK,
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0, 2, 0, 0);
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}
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return IRQ_HANDLED;
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}
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static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1)
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{
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struct cec_msg *msg = &vc4->hdmi->cec_rx_msg;
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unsigned int i;
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msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
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VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
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for (i = 0; i < msg->len; i += 4) {
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u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i);
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msg->msg[i] = val & 0xff;
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msg->msg[i + 1] = (val >> 8) & 0xff;
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msg->msg[i + 2] = (val >> 16) & 0xff;
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msg->msg[i + 3] = (val >> 24) & 0xff;
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}
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}
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static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
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{
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struct vc4_dev *vc4 = priv;
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struct vc4_hdmi *hdmi = vc4->hdmi;
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u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS);
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u32 cntrl1, cntrl5;
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if (!(stat & VC4_HDMI_CPU_CEC))
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return IRQ_NONE;
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hdmi->cec_rx_msg.len = 0;
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cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
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cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
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hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
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if (hdmi->cec_irq_was_rx) {
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vc4_cec_read_msg(vc4, cntrl1);
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cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
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cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
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} else {
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hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
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cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
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}
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1);
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HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC);
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return IRQ_WAKE_THREAD;
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}
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static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
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{
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struct vc4_dev *vc4 = cec_get_drvdata(adap);
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/* clock period in microseconds */
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const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
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u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5);
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val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
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VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
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VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
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val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
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((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
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if (enable) {
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
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VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val);
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2,
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((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
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((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
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((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
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((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
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((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3,
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((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
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((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
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((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
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((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4,
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((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
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((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
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((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
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((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
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HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
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} else {
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HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val |
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VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
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}
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return 0;
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}
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static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
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{
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struct vc4_dev *vc4 = cec_get_drvdata(adap);
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1,
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(HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
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(log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
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return 0;
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}
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static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
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u32 signal_free_time, struct cec_msg *msg)
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{
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struct vc4_dev *vc4 = cec_get_drvdata(adap);
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u32 val;
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unsigned int i;
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for (i = 0; i < msg->len; i += 4)
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HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i,
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(msg->msg[i]) |
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(msg->msg[i + 1] << 8) |
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(msg->msg[i + 2] << 16) |
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(msg->msg[i + 3] << 24));
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val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
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val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
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val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
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val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
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val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val);
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return 0;
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}
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static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
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.adap_enable = vc4_hdmi_cec_adap_enable,
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.adap_log_addr = vc4_hdmi_cec_adap_log_addr,
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.adap_transmit = vc4_hdmi_cec_adap_transmit,
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};
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#endif
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static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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{
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struct platform_device *pdev = to_platform_device(dev);
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@ -1180,7 +1361,7 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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* needs to be a bit higher than the pixel clock rate
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* (generally 148.5Mhz).
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*/
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ret = clk_set_rate(hdmi->hsm_clock, 163682864);
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ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ);
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if (ret) {
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DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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goto err_put_i2c;
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@ -1231,6 +1412,37 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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ret = PTR_ERR(hdmi->connector);
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goto err_destroy_encoder;
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}
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#ifdef CONFIG_DRM_VC4_HDMI_CEC
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hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
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vc4, "vc4",
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CEC_CAP_TRANSMIT |
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CEC_CAP_LOG_ADDRS |
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CEC_CAP_PASSTHROUGH |
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CEC_CAP_RC, 1);
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ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
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if (ret < 0)
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goto err_destroy_conn;
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HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff);
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value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1);
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value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
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/*
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* Set the logical address to Unregistered and set the clock
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* divider: the hsm_clock rate and this divider setting will
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* give a 40 kHz CEC clock.
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*/
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value |= VC4_HDMI_CEC_ADDR_MASK |
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(4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
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HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value);
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ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
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vc4_cec_irq_handler,
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vc4_cec_irq_handler_thread, 0,
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"vc4 hdmi cec", vc4);
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if (ret)
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goto err_delete_cec_adap;
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ret = cec_register_adapter(hdmi->cec_adap, dev);
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if (ret < 0)
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goto err_delete_cec_adap;
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#endif
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ret = vc4_hdmi_audio_init(hdmi);
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if (ret)
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@ -1238,6 +1450,12 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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return 0;
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#ifdef CONFIG_DRM_VC4_HDMI_CEC
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err_delete_cec_adap:
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cec_delete_adapter(hdmi->cec_adap);
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err_destroy_conn:
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vc4_hdmi_connector_destroy(hdmi->connector);
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#endif
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err_destroy_encoder:
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vc4_hdmi_encoder_destroy(hdmi->encoder);
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err_unprepare_hsm:
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@ -1257,7 +1475,7 @@ static void vc4_hdmi_unbind(struct device *dev, struct device *master,
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struct vc4_hdmi *hdmi = vc4->hdmi;
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vc4_hdmi_audio_cleanup(hdmi);
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cec_unregister_adapter(hdmi->cec_adap);
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vc4_hdmi_connector_destroy(hdmi->connector);
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vc4_hdmi_encoder_destroy(hdmi->encoder);
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@ -561,16 +561,129 @@
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# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
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# define VC4_HDMI_VERTB_VBP_SHIFT 0
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#define VC4_HDMI_CEC_CNTRL_1 0x0e8
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/* Set when the transmission has ended. */
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# define VC4_HDMI_CEC_TX_EOM BIT(31)
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/* If set, transmission was acked on the 1st or 2nd attempt (only one
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* retry is attempted). If in continuous mode, this means TX needs to
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* be filled if !TX_EOM.
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*/
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# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
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# define VC4_HDMI_CEC_RX_EOM BIT(29)
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# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
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/* Number of bytes received for the message. */
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# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)
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# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24
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/* Sets continuous receive mode. Generates interrupt after each 8
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* bytes to signal that RX_DATA should be consumed, and at RX_EOM.
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*
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* If disabled, maximum 16 bytes will be received (including header),
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* and interrupt at RX_EOM. Later bytes will be acked but not put
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* into the RX_DATA.
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*/
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# define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
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# define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
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/* Set this after a CEC interrupt. */
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# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
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/* Starts a TX. Will wait for appropriate idel time before CEC
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* activity. Must be cleared in between transmits.
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*/
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# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
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# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)
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# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16
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/* Device's CEC address */
|
||||
# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)
|
||||
# define VC4_HDMI_CEC_ADDR_SHIFT 12
|
||||
/* Divides off of HSM clock to generate CEC bit clock. */
|
||||
/* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
|
||||
# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)
|
||||
# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0
|
||||
|
||||
/* Set these fields to how many bit clock cycles get to that many
|
||||
* microseconds.
|
||||
*/
|
||||
#define VC4_HDMI_CEC_CNTRL_2 0x0ec
|
||||
# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)
|
||||
# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24
|
||||
# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)
|
||||
# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17
|
||||
# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)
|
||||
# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11
|
||||
# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)
|
||||
# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5
|
||||
# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)
|
||||
# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0
|
||||
|
||||
#define VC4_HDMI_CEC_CNTRL_3 0x0f0
|
||||
# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)
|
||||
# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24
|
||||
# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)
|
||||
# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16
|
||||
# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
|
||||
# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
|
||||
# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)
|
||||
# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0
|
||||
|
||||
#define VC4_HDMI_CEC_CNTRL_4 0x0f4
|
||||
# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)
|
||||
# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24
|
||||
# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)
|
||||
# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16
|
||||
# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
|
||||
# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
|
||||
# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)
|
||||
# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0
|
||||
|
||||
#define VC4_HDMI_CEC_CNTRL_5 0x0f8
|
||||
# define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
|
||||
# define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
|
||||
# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
|
||||
# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
|
||||
# define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
|
||||
# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)
|
||||
# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16
|
||||
# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
|
||||
# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
|
||||
# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)
|
||||
# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0
|
||||
|
||||
/* Transmit data, first byte is low byte of the 32-bit reg. MSB of
|
||||
* each byte transmitted first.
|
||||
*/
|
||||
#define VC4_HDMI_CEC_TX_DATA_1 0x0fc
|
||||
#define VC4_HDMI_CEC_TX_DATA_2 0x100
|
||||
#define VC4_HDMI_CEC_TX_DATA_3 0x104
|
||||
#define VC4_HDMI_CEC_TX_DATA_4 0x108
|
||||
#define VC4_HDMI_CEC_RX_DATA_1 0x10c
|
||||
#define VC4_HDMI_CEC_RX_DATA_2 0x110
|
||||
#define VC4_HDMI_CEC_RX_DATA_3 0x114
|
||||
#define VC4_HDMI_CEC_RX_DATA_4 0x118
|
||||
|
||||
#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
|
||||
|
||||
#define VC4_HDMI_TX_PHY_CTL0 0x2c4
|
||||
# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
|
||||
|
||||
/* Interrupt status bits */
|
||||
#define VC4_HDMI_CPU_STATUS 0x340
|
||||
#define VC4_HDMI_CPU_SET 0x344
|
||||
#define VC4_HDMI_CPU_CLEAR 0x348
|
||||
# define VC4_HDMI_CPU_CEC BIT(6)
|
||||
# define VC4_HDMI_CPU_HOTPLUG BIT(0)
|
||||
|
||||
#define VC4_HDMI_CPU_MASK_STATUS 0x34c
|
||||
#define VC4_HDMI_CPU_MASK_SET 0x350
|
||||
#define VC4_HDMI_CPU_MASK_CLEAR 0x354
|
||||
|
||||
#define VC4_HDMI_GCP(x) (0x400 + ((x) * 0x4))
|
||||
#define VC4_HDMI_RAM_PACKET(x) (0x400 + ((x) * 0x24))
|
||||
#define VC4_HDMI_PACKET_STRIDE 0x24
|
||||
|
||||
#define VC4_HD_M_CTL 0x00c
|
||||
/* Debug: Current receive value on the CEC pad. */
|
||||
# define VC4_HD_CECRXD BIT(9)
|
||||
/* Debug: Override CEC output to 0. */
|
||||
# define VC4_HD_CECOVR BIT(8)
|
||||
# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
|
||||
# define VC4_HD_M_RAM_STANDBY (3 << 4)
|
||||
# define VC4_HD_M_SW_RST BIT(2)
|
||||
|
|
|
|||
Loading…
Reference in a new issue