From 14ed9cc7e7b9a95d56c2bf91cab2f010968d6e73 Mon Sep 17 00:00:00 2001 From: Wayne Boyer Date: Mon, 3 Oct 2011 20:54:37 -0700 Subject: [PATCH] [SCSI] ipr: Add support to flash FPGA and flash back DRAM images The write buffer command is used to download and burn new IOA FW images. The same interface can now be used to flash FPGA and flash back DRAM images. To download and flash the new images takes more than 15 minutes, so increase the write buffer command timeout to 30 minutes. The FPGA and flash back DRAM images don't have the same card_type as the IOA FW image. So, remove the sanity checking from the driver. The adapter has sanity checking and will only accept a valid image. Signed-off-by: Wayne Boyer Acked-by: Brian King Signed-off-by: James Bottomley --- drivers/scsi/ipr.c | 10 ++-------- drivers/scsi/ipr.h | 2 +- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index f03963a972fc..e16a9cf442c1 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -3751,14 +3751,6 @@ static ssize_t ipr_store_update_fw(struct device *dev, image_hdr = (struct ipr_ucode_image_header *)fw_entry->data; - if (be32_to_cpu(image_hdr->header_length) > fw_entry->size || - (ioa_cfg->vpd_cbs->page3_data.card_type && - ioa_cfg->vpd_cbs->page3_data.card_type != image_hdr->card_type)) { - dev_err(&ioa_cfg->pdev->dev, "Invalid microcode buffer\n"); - release_firmware(fw_entry); - return -EINVAL; - } - src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length); dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length); sglist = ipr_alloc_ucode_buffer(dnld_size); @@ -3777,6 +3769,8 @@ static ssize_t ipr_store_update_fw(struct device *dev, goto out; } + ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n"); + result = ipr_update_ioa_ucode(ioa_cfg, sglist); if (!result) diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index f9766f84d91c..0cbf58f6ae5d 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -208,7 +208,7 @@ #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) -#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ) +#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) #define IPR_OPERATIONAL_TIMEOUT (5 * 60)