x86, msi, intr-remap: Use the ioapic set affinity routine
IRQ set affinity routine is same for the IO-APIC IRQ's aswell as the MSI IRQ's in the presence of interrupt-remapping. This is because we modify the interrupt-remapping table entry and doesn't touch the IO-APIC RTE or the MSI entry. So remove the ir_msi_set_affinity() and re-use the ir_ioapic_set_affinity() Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: yinghai@kernel.org Cc: youquan.song@intel.com Cc: joerg.roedel@amd.com Cc: tony.luck@intel.com Cc: dwmw2@infradead.org Link: http://lkml.kernel.org/r/20110824001456.452760446@sbsiddha-desk.sc.intel.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
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1 changed files with 12 additions and 42 deletions
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@ -2267,6 +2267,9 @@ ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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* updated vector information), by using a virtual vector (io-apic pin number).
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* Real vector that is used for interrupting cpu will be coming from
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* the interrupt-remapping table entry.
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*
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* As the migration is a simple atomic update of IRTE, the same mechanism
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* is used to migrate MSI irq's in the presence of interrupt-remapping.
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*/
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static int
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ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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@ -2291,10 +2294,16 @@ ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
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irte.dest_id = IRTE_DEST(dest);
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/*
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* Modified the IRTE and flushes the Interrupt entry cache.
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* Atomically updates the IRTE with the new destination, vector
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* and flushes the interrupt entry cache.
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*/
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modify_irte(irq, &irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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@ -3144,45 +3153,6 @@ msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
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return 0;
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}
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#ifdef CONFIG_INTR_REMAP
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/*
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* Migrate the MSI irq to another cpumask. This migration is
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* done in the process context using interrupt-remapping hardware.
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*/
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static int
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ir_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
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bool force)
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{
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struct irq_cfg *cfg = data->chip_data;
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unsigned int dest, irq = data->irq;
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struct irte irte;
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if (get_irte(irq, &irte))
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return -1;
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if (__ioapic_set_affinity(data, mask, &dest))
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return -1;
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irte.vector = cfg->vector;
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irte.dest_id = IRTE_DEST(dest);
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/*
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* atomically update the IRTE with the new destination and vector.
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*/
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modify_irte(irq, &irte);
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/*
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* After this point, all the interrupts will start arriving
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* at the new destination. So, time to cleanup the previous
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* vector allocation.
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*/
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if (cfg->move_in_progress)
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send_cleanup_vector(cfg);
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return 0;
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}
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#endif
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#endif /* CONFIG_SMP */
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/*
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@ -3207,7 +3177,7 @@ static struct irq_chip msi_ir_chip = {
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#ifdef CONFIG_INTR_REMAP
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.irq_ack = ir_ack_apic_edge,
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#ifdef CONFIG_SMP
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.irq_set_affinity = ir_msi_set_affinity,
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.irq_set_affinity = ir_ioapic_set_affinity,
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#endif
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#endif
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.irq_retrigger = ioapic_retrigger_irq,
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@ -3416,7 +3386,7 @@ static struct irq_chip ir_hpet_msi_type = {
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#ifdef CONFIG_INTR_REMAP
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.irq_ack = ir_ack_apic_edge,
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#ifdef CONFIG_SMP
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.irq_set_affinity = ir_msi_set_affinity,
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.irq_set_affinity = ir_ioapic_set_affinity,
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#endif
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#endif
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.irq_retrigger = ioapic_retrigger_irq,
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