[BNX2]: Support larger rx ring sizes (part 1)
Increase maximum receive ring size from 255 to 1020 by supporting up to 4 linked pages of receive descriptors. To accomodate the higher memory usage, each physical descriptor page is allocated separately and the software ring that keeps track of the SKBs and the DMA addresses is allocated using vmalloc. Some of the receive-related fields in the bp structure are re- organized a bit for better locality of reference. The max. was reduced to 1020 from 4080 after discussion with David Miller. This patch contains ring init code changes only. This next patch contains rx data path code changes. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
236b6394bb
commit
13daffa2f2
2 changed files with 106 additions and 45 deletions
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@ -360,6 +360,8 @@ bnx2_netif_start(struct bnx2 *bp)
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static void
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bnx2_free_mem(struct bnx2 *bp)
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{
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int i;
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if (bp->stats_blk) {
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pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
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bp->stats_blk, bp->stats_blk_mapping);
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@ -378,19 +380,23 @@ bnx2_free_mem(struct bnx2 *bp)
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}
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kfree(bp->tx_buf_ring);
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bp->tx_buf_ring = NULL;
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if (bp->rx_desc_ring) {
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pci_free_consistent(bp->pdev,
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sizeof(struct rx_bd) * RX_DESC_CNT,
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bp->rx_desc_ring, bp->rx_desc_mapping);
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bp->rx_desc_ring = NULL;
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for (i = 0; i < bp->rx_max_ring; i++) {
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if (bp->rx_desc_ring[i])
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pci_free_consistent(bp->pdev,
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sizeof(struct rx_bd) * RX_DESC_CNT,
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bp->rx_desc_ring[i],
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bp->rx_desc_mapping[i]);
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bp->rx_desc_ring[i] = NULL;
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}
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kfree(bp->rx_buf_ring);
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vfree(bp->rx_buf_ring);
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bp->rx_buf_ring = NULL;
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}
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static int
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bnx2_alloc_mem(struct bnx2 *bp)
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{
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int i;
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bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
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GFP_KERNEL);
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if (bp->tx_buf_ring == NULL)
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@ -404,18 +410,23 @@ bnx2_alloc_mem(struct bnx2 *bp)
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if (bp->tx_desc_ring == NULL)
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goto alloc_mem_err;
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bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
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GFP_KERNEL);
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bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
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bp->rx_max_ring);
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if (bp->rx_buf_ring == NULL)
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goto alloc_mem_err;
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memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
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bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
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sizeof(struct rx_bd) *
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RX_DESC_CNT,
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&bp->rx_desc_mapping);
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if (bp->rx_desc_ring == NULL)
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goto alloc_mem_err;
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memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
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bp->rx_max_ring);
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for (i = 0; i < bp->rx_max_ring; i++) {
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bp->rx_desc_ring[i] =
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pci_alloc_consistent(bp->pdev,
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sizeof(struct rx_bd) * RX_DESC_CNT,
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&bp->rx_desc_mapping[i]);
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if (bp->rx_desc_ring[i] == NULL)
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goto alloc_mem_err;
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}
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bp->status_blk = pci_alloc_consistent(bp->pdev,
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sizeof(struct status_block),
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@ -1520,7 +1531,7 @@ bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
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struct sk_buff *skb;
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struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
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dma_addr_t mapping;
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struct rx_bd *rxbd = &bp->rx_desc_ring[index];
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struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
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unsigned long align;
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skb = dev_alloc_skb(bp->rx_buf_size);
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@ -3349,24 +3360,32 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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bp->hw_rx_cons = 0;
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bp->rx_prod_bseq = 0;
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rxbd = &bp->rx_desc_ring[0];
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for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
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rxbd->rx_bd_len = bp->rx_buf_use_size;
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rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
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}
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for (i = 0; i < bp->rx_max_ring; i++) {
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int j;
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rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
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rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
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rxbd = &bp->rx_desc_ring[i][0];
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for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
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rxbd->rx_bd_len = bp->rx_buf_use_size;
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rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
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}
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if (i == (bp->rx_max_ring - 1))
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j = 0;
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else
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j = i + 1;
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rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
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rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
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0xffffffff;
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}
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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val |= 0x02 << 8;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
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val = (u64) bp->rx_desc_mapping >> 32;
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val = (u64) bp->rx_desc_mapping[0] >> 32;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
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val = (u64) bp->rx_desc_mapping & 0xffffffff;
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val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
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for (i = 0; i < bp->rx_ring_size; i++) {
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@ -3383,6 +3402,29 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
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}
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static void
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bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
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{
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u32 num_rings, max;
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bp->rx_ring_size = size;
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num_rings = 1;
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while (size > MAX_RX_DESC_CNT) {
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size -= MAX_RX_DESC_CNT;
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num_rings++;
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}
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/* round to next power of 2 */
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max = MAX_RX_RINGS;
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while ((max & num_rings) == 0)
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max >>= 1;
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if (num_rings != max)
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max <<= 1;
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bp->rx_max_ring = max;
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bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
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}
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static void
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bnx2_free_tx_skbs(struct bnx2 *bp)
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{
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@ -3428,7 +3470,7 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
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if (bp->rx_buf_ring == NULL)
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return;
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for (i = 0; i < RX_DESC_CNT; i++) {
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for (i = 0; i < bp->rx_max_ring_idx; i++) {
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struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
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struct sk_buff *skb = rx_buf->skb;
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@ -4792,7 +4834,7 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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{
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struct bnx2 *bp = netdev_priv(dev);
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ering->rx_max_pending = MAX_RX_DESC_CNT;
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ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
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ering->rx_mini_max_pending = 0;
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ering->rx_jumbo_max_pending = 0;
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@ -4809,17 +4851,28 @@ bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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{
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struct bnx2 *bp = netdev_priv(dev);
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if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
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if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
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(ering->tx_pending > MAX_TX_DESC_CNT) ||
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(ering->tx_pending <= MAX_SKB_FRAGS)) {
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return -EINVAL;
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}
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bp->rx_ring_size = ering->rx_pending;
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if (netif_running(bp->dev)) {
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bnx2_netif_stop(bp);
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bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
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bnx2_free_skbs(bp);
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bnx2_free_mem(bp);
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}
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bnx2_set_rx_ring_size(bp, ering->rx_pending);
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bp->tx_ring_size = ering->tx_pending;
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if (netif_running(bp->dev)) {
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bnx2_netif_stop(bp);
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int rc;
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rc = bnx2_alloc_mem(bp);
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if (rc)
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return rc;
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bnx2_init_nic(bp);
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bnx2_netif_start(bp);
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}
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@ -5493,7 +5546,7 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
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bp->mac_addr[5] = (u8) reg;
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bp->tx_ring_size = MAX_TX_DESC_CNT;
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bp->rx_ring_size = 100;
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bnx2_set_rx_ring_size(bp, 100);
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bp->rx_csum = 1;
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@ -3792,8 +3792,10 @@ struct l2_fhdr {
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#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
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#define MAX_RX_RINGS 4
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#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
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#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
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#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
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(MAX_TX_DESC_CNT - 1)) ? \
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@ -3805,8 +3807,10 @@ struct l2_fhdr {
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(MAX_RX_DESC_CNT - 1)) ? \
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(x) + 2 : (x) + 1
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#define RX_RING_IDX(x) ((x) & MAX_RX_DESC_CNT)
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#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
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#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
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#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
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/* Context size. */
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#define CTX_SHIFT 7
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@ -3903,6 +3907,15 @@ struct bnx2 {
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struct status_block *status_blk;
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u32 last_status_idx;
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u32 flags;
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#define PCIX_FLAG 1
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#define PCI_32BIT_FLAG 2
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#define ONE_TDMA_FLAG 4 /* no longer used */
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#define NO_WOL_FLAG 8
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#define USING_DAC_FLAG 0x10
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#define USING_MSI_FLAG 0x20
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#define ASF_ENABLE_FLAG 0x40
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struct tx_bd *tx_desc_ring;
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struct sw_bd *tx_buf_ring;
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u32 tx_prod_bseq;
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@ -3920,19 +3933,22 @@ struct bnx2 {
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u32 rx_offset;
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u32 rx_buf_use_size; /* useable size */
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u32 rx_buf_size; /* with alignment */
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struct rx_bd *rx_desc_ring;
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struct sw_bd *rx_buf_ring;
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u32 rx_max_ring_idx;
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u32 rx_prod_bseq;
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u16 rx_prod;
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u16 rx_cons;
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u32 rx_csum;
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struct sw_bd *rx_buf_ring;
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struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
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/* Only used to synchronize netif_stop_queue/wake_queue when tx */
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/* ring is full */
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spinlock_t tx_lock;
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/* End of fileds used in the performance code paths. */
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/* End of fields used in the performance code paths. */
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char *name;
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@ -3945,15 +3961,6 @@ struct bnx2 {
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/* Used to synchronize phy accesses. */
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spinlock_t phy_lock;
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u32 flags;
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#define PCIX_FLAG 1
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#define PCI_32BIT_FLAG 2
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#define ONE_TDMA_FLAG 4 /* no longer used */
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#define NO_WOL_FLAG 8
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#define USING_DAC_FLAG 0x10
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#define USING_MSI_FLAG 0x20
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#define ASF_ENABLE_FLAG 0x40
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u32 phy_flags;
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#define PHY_SERDES_FLAG 1
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#define PHY_CRC_FIX_FLAG 2
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@ -4004,8 +4011,9 @@ struct bnx2 {
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dma_addr_t tx_desc_mapping;
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int rx_max_ring;
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int rx_ring_size;
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dma_addr_t rx_desc_mapping;
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dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
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u16 tx_quick_cons_trip;
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u16 tx_quick_cons_trip_int;
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