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Merge master.kernel.org:/home/rmk/linux-2.6-arm

Browse source 
* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] AACI: timeout will reach -1
  [ARM] Storage class should be before const qualifier
  [ARM] pxa: stop and disable IRQ for each DMA channels at startup
  [ARM] pxa: make more SSCR0 bit definitions visible on multiple processors
  [ARM] pxa: fix missing of __REG() definition for ac97 registers access
  [ARM] pxa: fix NAND and MMC clock initialization for pxa3xx
This commit is contained in:
Linus Torvalds 2009-02-10 15:54:50 -08:00
commit 1385a7ae65
7 changed files with 23 additions and 16 deletions
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4
arch/arm/kernel/machine_kexec.c
View file

@ -13,8 +13,8 @@
#include <asm/cacheflush.h>
#include <asm/mach-types.h>
const extern unsigned char relocate_new_kernel[];
const extern unsigned int relocate_new_kernel_size;
extern const unsigned char relocate_new_kernel[];
extern const unsigned int relocate_new_kernel_size;
extern void setup_mm_for_reboot(char mode);

18
arch/arm/mach-pxa/dma.c
View file

@ -121,6 +121,16 @@ int __init pxa_init_dma(int num_ch)
if (dma_channels == NULL)
return -ENOMEM;
/* dma channel priorities on pxa2xx processors:
* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
*/
for (i = 0; i < num_ch; i++) {
DCSR(i) = 0;
dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
}
ret = request_irq(IRQ_DMA, dma_irq_handler, IRQF_DISABLED, "DMA", NULL);
if (ret) {
printk (KERN_CRIT "Wow! Can't register IRQ for DMA\n");
@ -128,14 +138,6 @@ int __init pxa_init_dma(int num_ch)
return ret;
}
/* dma channel priorities on pxa2xx processors:
* ch 0 - 3, 16 - 19 <--> (0) DMA_PRIO_HIGH
* ch 4 - 7, 20 - 23 <--> (1) DMA_PRIO_MEDIUM
* ch 8 - 15, 24 - 31 <--> (2) DMA_PRIO_LOW
*/
for (i = 0; i < num_ch; i++)
dma_channels[i].prio = min((i & 0xf) >> 2, DMA_PRIO_LOW);
num_dma_channels = num_ch;
return 0;
}

2
arch/arm/mach-pxa/include/mach/regs-ac97.h
View file

@ -1,6 +1,8 @@
#ifndef __ASM_ARCH_REGS_AC97_H
#define __ASM_ARCH_REGS_AC97_H
#include <mach/hardware.h>
/*
* AC97 Controller registers
*/

3
arch/arm/mach-pxa/include/mach/regs-ssp.h
View file

@ -41,6 +41,9 @@
#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
#endif
#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
#define SSCR0_EDSS (1 << 20) /* Extended data size select */
#define SSCR0_NCS (1 << 21) /* Network clock select */
#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */

4
arch/arm/mach-pxa/pxa300.c
View file

@ -88,13 +88,13 @@ static struct pxa3xx_mfp_addr_map pxa310_mfp_addr_map[] __initdata = {
static DEFINE_PXA3_CKEN(common_nand, NAND, 156000000, 0);
static struct clk_lookup common_clkregs[] = {
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", "NANDCLK"),
INIT_CLKREG(&clk_common_nand, "pxa3xx-nand", NULL),
};
static DEFINE_PXA3_CKEN(pxa310_mmc3, MMC3, 19500000, 0);
static struct clk_lookup pxa310_clkregs[] = {
INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", "MMCCLK"),
INIT_CLKREG(&clk_pxa310_mmc3, "pxa2xx-mci.2", NULL),
};
static int __init pxa300_init(void)

2
arch/arm/mach-pxa/pxa320.c
View file

@ -83,7 +83,7 @@ static struct pxa3xx_mfp_addr_map pxa320_mfp_addr_map[] __initdata = {
static DEFINE_PXA3_CKEN(pxa320_nand, NAND, 104000000, 0);
static struct clk_lookup pxa320_clkregs[] = {
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", "NANDCLK"),
INIT_CLKREG(&clk_pxa320_nand, "pxa3xx-nand", NULL),
};
static int __init pxa320_init(void)

6
sound/arm/aaci.c
View file

@ -90,7 +90,7 @@ static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
*/
do {
v = readl(aaci->base + AACI_SLFR);
} while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--);
} while ((v & (SLFR_1TXB|SLFR_2TXB)) && --timeout);
if (!timeout)
dev_err(&aaci->dev->dev,
@ -126,7 +126,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
*/
do {
v = readl(aaci->base + AACI_SLFR);
} while ((v & SLFR_1TXB) && timeout--);
} while ((v & SLFR_1TXB) && --timeout);
if (!timeout) {
dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
@ -147,7 +147,7 @@ static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
do {
cond_resched();
v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
} while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--);
} while ((v != (SLFR_1RXV|SLFR_2RXV)) && --timeout);
if (!timeout) {
dev_err(&aaci->dev->dev, "timeout on RX valid\n");