powerpc/mpc5121: Add clock driver
Plugs into the generic powerpc clock driver in
arch/powerpc/kernel/clock.c
The following subset of clk_interface is implemented:
clk_get, clk_put: get clock via name, release clock
clk_enable, clk_disable: enable or disable clock
clk_get_rate: get clock rate in Hz
clk_set_rate: stubbed
clk_round_rate: stubbed
clk_set_parent: NULL
clk_get_parent: NULL
Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
This commit is contained in:
John Rigby
Grant Likely
parent
4df64c3e58
commit
137e95906e
4 changed files with 732 additions and 0 deletions
1
Makefile
1
Makefile
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@ -1,3 +1,4 @@
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FRED=42
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VERSION = 2
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PATCHLEVEL = 6
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SUBLEVEL = 26
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@ -2,6 +2,7 @@ config PPC_MPC512x
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bool
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select FSL_SOC
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select IPIC
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select PPC_CLOCK
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default n
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config PPC_MPC5121
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@ -1,4 +1,5 @@
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#
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# Makefile for the Freescale PowerPC 512x linux kernel.
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#
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obj-y += clock.o
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obj-$(CONFIG_MPC5121_ADS) += mpc5121_ads.o
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729
arch/powerpc/platforms/512x/clock.c
Normal file
729
arch/powerpc/platforms/512x/clock.c
Normal file
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@ -0,0 +1,729 @@
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/*
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* Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
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*
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* Author: John Rigby <jrigby@freescale.com>
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*
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* Implements the clk api defined in include/linux/clk.h
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*
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* Original based on linux/arch/arm/mach-integrator/clock.c
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*
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* Copyright (C) 2004 ARM Limited.
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* Written by Deep Blue Solutions Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/mutex.h>
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#include <linux/io.h>
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#include <linux/of_platform.h>
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#include <asm/mpc512x.h>
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#include <asm/clk_interface.h>
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#undef CLK_DEBUG
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static int clocks_initialized;
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#define CLK_HAS_RATE 0x1 /* has rate in MHz */
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#define CLK_HAS_CTRL 0x2 /* has control reg and bit */
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struct clk {
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struct list_head node;
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char name[32];
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int flags;
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struct device *dev;
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unsigned long rate;
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struct module *owner;
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void (*calc) (struct clk *);
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struct clk *parent;
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int reg, bit; /* CLK_HAS_CTRL */
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int div_shift; /* only used by generic_div_clk_calc */
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};
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static LIST_HEAD(clocks);
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static DEFINE_MUTEX(clocks_mutex);
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static struct clk *mpc5121_clk_get(struct device *dev, const char *id)
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{
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struct clk *p, *clk = ERR_PTR(-ENOENT);
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int dev_match = 0;
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int id_match = 0;
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if (dev == NULL && id == NULL)
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return NULL;
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mutex_lock(&clocks_mutex);
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list_for_each_entry(p, &clocks, node) {
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if (dev && dev == p->dev)
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dev_match++;
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if (strcmp(id, p->name) == 0)
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id_match++;
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if ((dev_match || id_match) && try_module_get(p->owner)) {
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clk = p;
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break;
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}
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}
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mutex_unlock(&clocks_mutex);
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return clk;
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}
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#ifdef CLK_DEBUG
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static void dump_clocks(void)
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{
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struct clk *p;
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mutex_lock(&clocks_mutex);
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printk(KERN_INFO "CLOCKS:\n");
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list_for_each_entry(p, &clocks, node) {
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printk(KERN_INFO " %s %ld", p->name, p->rate);
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if (p->parent)
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printk(KERN_INFO " %s %ld", p->parent->name,
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p->parent->rate);
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if (p->flags & CLK_HAS_CTRL)
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printk(KERN_INFO " reg/bit %d/%d", p->reg, p->bit);
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printk("\n");
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}
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mutex_unlock(&clocks_mutex);
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}
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#define DEBUG_CLK_DUMP() dump_clocks()
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#else
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#define DEBUG_CLK_DUMP()
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#endif
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static void mpc5121_clk_put(struct clk *clk)
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{
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module_put(clk->owner);
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}
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#define NRPSC 12
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struct mpc512x_clockctl {
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u32 spmr; /* System PLL Mode Reg */
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u32 sccr[2]; /* System Clk Ctrl Reg 1 & 2 */
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u32 scfr1; /* System Clk Freq Reg 1 */
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u32 scfr2; /* System Clk Freq Reg 2 */
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u32 reserved;
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u32 bcr; /* Bread Crumb Reg */
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u32 pccr[NRPSC]; /* PSC Clk Ctrl Reg 0-11 */
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u32 spccr; /* SPDIF Clk Ctrl Reg */
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u32 cccr; /* CFM Clk Ctrl Reg */
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u32 dccr; /* DIU Clk Cnfg Reg */
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};
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struct mpc512x_clockctl __iomem *clockctl;
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static int mpc5121_clk_enable(struct clk *clk)
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{
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unsigned int mask;
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if (clk->flags & CLK_HAS_CTRL) {
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mask = in_be32(&clockctl->sccr[clk->reg]);
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mask |= 1 << clk->bit;
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out_be32(&clockctl->sccr[clk->reg], mask);
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}
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return 0;
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}
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static void mpc5121_clk_disable(struct clk *clk)
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{
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unsigned int mask;
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if (clk->flags & CLK_HAS_CTRL) {
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mask = in_be32(&clockctl->sccr[clk->reg]);
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mask &= ~(1 << clk->bit);
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out_be32(&clockctl->sccr[clk->reg], mask);
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}
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}
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static unsigned long mpc5121_clk_get_rate(struct clk *clk)
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{
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if (clk->flags & CLK_HAS_RATE)
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return clk->rate;
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else
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return 0;
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}
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static long mpc5121_clk_round_rate(struct clk *clk, unsigned long rate)
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{
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return rate;
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}
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static int mpc5121_clk_set_rate(struct clk *clk, unsigned long rate)
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{
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return 0;
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}
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static int clk_register(struct clk *clk)
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{
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mutex_lock(&clocks_mutex);
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list_add(&clk->node, &clocks);
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mutex_unlock(&clocks_mutex);
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return 0;
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}
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static unsigned long spmf_mult(void)
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{
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/*
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* Convert spmf to multiplier
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*/
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static int spmf_to_mult[] = {
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68, 1, 12, 16,
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20, 24, 28, 32,
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36, 40, 44, 48,
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52, 56, 60, 64
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};
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int spmf = (clockctl->spmr >> 24) & 0xf;
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return spmf_to_mult[spmf];
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}
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static unsigned long sysdiv_div_x_2(void)
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{
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/*
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* Convert sysdiv to divisor x 2
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* Some divisors have fractional parts so
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* multiply by 2 then divide by this value
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*/
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static int sysdiv_to_div_x_2[] = {
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4, 5, 6, 7,
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8, 9, 10, 14,
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12, 16, 18, 22,
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20, 24, 26, 30,
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28, 32, 34, 38,
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36, 40, 42, 46,
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44, 48, 50, 54,
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52, 56, 58, 62,
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60, 64, 66,
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};
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int sysdiv = (clockctl->scfr2 >> 26) & 0x3f;
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return sysdiv_to_div_x_2[sysdiv];
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}
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static unsigned long ref_to_sys(unsigned long rate)
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{
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rate *= spmf_mult();
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rate *= 2;
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rate /= sysdiv_div_x_2();
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return rate;
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}
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static unsigned long sys_to_ref(unsigned long rate)
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{
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rate *= sysdiv_div_x_2();
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rate /= 2;
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rate /= spmf_mult();
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return rate;
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}
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static long ips_to_ref(unsigned long rate)
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{
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int ips_div = (clockctl->scfr1 >> 23) & 0x7;
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rate *= ips_div; /* csb_clk = ips_clk * ips_div */
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rate *= 2; /* sys_clk = csb_clk * 2 */
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return sys_to_ref(rate);
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}
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static unsigned long devtree_getfreq(char *clockname)
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{
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struct device_node *np;
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const unsigned int *prop;
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unsigned int val = 0;
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr");
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if (np) {
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prop = of_get_property(np, clockname, NULL);
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if (prop)
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val = *prop;
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of_node_put(np);
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}
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return val;
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}
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static void ref_clk_calc(struct clk *clk)
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{
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unsigned long rate;
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rate = devtree_getfreq("bus-frequency");
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if (rate == 0) {
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printk(KERN_ERR "No bus-frequency in dev tree\n");
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clk->rate = 0;
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return;
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}
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clk->rate = ips_to_ref(rate);
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}
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static struct clk ref_clk = {
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.name = "ref_clk",
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.calc = ref_clk_calc,
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};
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static void sys_clk_calc(struct clk *clk)
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{
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clk->rate = ref_to_sys(ref_clk.rate);
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}
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static struct clk sys_clk = {
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.name = "sys_clk",
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.calc = sys_clk_calc,
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};
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static void diu_clk_calc(struct clk *clk)
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{
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int diudiv_x_2 = clockctl->scfr1 & 0xff;
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unsigned long rate;
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rate = sys_clk.rate;
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rate *= 2;
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rate /= diudiv_x_2;
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clk->rate = rate;
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}
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static void half_clk_calc(struct clk *clk)
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{
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clk->rate = clk->parent->rate / 2;
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}
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static void generic_div_clk_calc(struct clk *clk)
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{
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int div = (clockctl->scfr1 >> clk->div_shift) & 0x7;
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clk->rate = clk->parent->rate / div;
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}
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static void unity_clk_calc(struct clk *clk)
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{
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clk->rate = clk->parent->rate;
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}
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static struct clk csb_clk = {
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.name = "csb_clk",
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.calc = half_clk_calc,
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.parent = &sys_clk,
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};
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static void e300_clk_calc(struct clk *clk)
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{
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int spmf = (clockctl->spmr >> 16) & 0xf;
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int ratex2 = clk->parent->rate * spmf;
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clk->rate = ratex2 / 2;
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}
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static struct clk e300_clk = {
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.name = "e300_clk",
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.calc = e300_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk ips_clk = {
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.name = "ips_clk",
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.calc = generic_div_clk_calc,
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.parent = &csb_clk,
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.div_shift = 23,
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};
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/*
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* Clocks controlled by SCCR1 (.reg = 0)
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*/
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static struct clk lpc_clk = {
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.name = "lpc_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 30,
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.calc = generic_div_clk_calc,
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.parent = &ips_clk,
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.div_shift = 11,
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};
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static struct clk nfc_clk = {
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.name = "nfc_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 29,
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.calc = generic_div_clk_calc,
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.parent = &ips_clk,
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.div_shift = 8,
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};
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static struct clk pata_clk = {
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.name = "pata_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 28,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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/*
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* PSC clocks (bits 27 - 16)
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* are setup elsewhere
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*/
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static struct clk sata_clk = {
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.name = "sata_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 14,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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static struct clk fec_clk = {
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.name = "fec_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 13,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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static struct clk pci_clk = {
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.name = "pci_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 0,
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.bit = 11,
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.calc = generic_div_clk_calc,
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.parent = &csb_clk,
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.div_shift = 20,
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};
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/*
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* Clocks controlled by SCCR2 (.reg = 1)
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*/
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static struct clk diu_clk = {
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.name = "diu_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 31,
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.calc = diu_clk_calc,
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};
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static struct clk axe_clk = {
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.name = "axe_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 30,
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.calc = unity_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk usb1_clk = {
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.name = "usb1_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 28,
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.calc = unity_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk usb2_clk = {
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.name = "usb2_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 27,
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.calc = unity_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk i2c_clk = {
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.name = "i2c_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 26,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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static struct clk mscan_clk = {
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.name = "mscan_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 25,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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static struct clk sdhc_clk = {
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.name = "sdhc_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 24,
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.calc = unity_clk_calc,
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.parent = &ips_clk,
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};
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static struct clk mbx_bus_clk = {
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.name = "mbx_bus_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 22,
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.calc = half_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk mbx_clk = {
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.name = "mbx_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 21,
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.calc = unity_clk_calc,
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.parent = &csb_clk,
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};
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static struct clk mbx_3d_clk = {
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.name = "mbx_3d_clk",
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.flags = CLK_HAS_CTRL,
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.reg = 1,
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.bit = 20,
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.calc = generic_div_clk_calc,
|
||||
.parent = &mbx_bus_clk,
|
||||
.div_shift = 14,
|
||||
};
|
||||
|
||||
static void psc_mclk_in_calc(struct clk *clk)
|
||||
{
|
||||
clk->rate = devtree_getfreq("psc_mclk_in");
|
||||
if (!clk->rate)
|
||||
clk->rate = 25000000;
|
||||
}
|
||||
|
||||
static struct clk psc_mclk_in = {
|
||||
.name = "psc_mclk_in",
|
||||
.calc = psc_mclk_in_calc,
|
||||
};
|
||||
|
||||
static struct clk spdif_txclk = {
|
||||
.name = "spdif_txclk",
|
||||
.flags = CLK_HAS_CTRL,
|
||||
.reg = 1,
|
||||
.bit = 23,
|
||||
};
|
||||
|
||||
static struct clk spdif_rxclk = {
|
||||
.name = "spdif_rxclk",
|
||||
.flags = CLK_HAS_CTRL,
|
||||
.reg = 1,
|
||||
.bit = 23,
|
||||
};
|
||||
|
||||
static void ac97_clk_calc(struct clk *clk)
|
||||
{
|
||||
/* ac97 bit clock is always 24.567 MHz */
|
||||
clk->rate = 24567000;
|
||||
}
|
||||
|
||||
static struct clk ac97_clk = {
|
||||
.name = "ac97_clk_in",
|
||||
.calc = ac97_clk_calc,
|
||||
};
|
||||
|
||||
struct clk *rate_clks[] = {
|
||||
&ref_clk,
|
||||
&sys_clk,
|
||||
&diu_clk,
|
||||
&csb_clk,
|
||||
&e300_clk,
|
||||
&ips_clk,
|
||||
&fec_clk,
|
||||
&sata_clk,
|
||||
&pata_clk,
|
||||
&nfc_clk,
|
||||
&lpc_clk,
|
||||
&mbx_bus_clk,
|
||||
&mbx_clk,
|
||||
&mbx_3d_clk,
|
||||
&axe_clk,
|
||||
&usb1_clk,
|
||||
&usb2_clk,
|
||||
&i2c_clk,
|
||||
&mscan_clk,
|
||||
&sdhc_clk,
|
||||
&pci_clk,
|
||||
&psc_mclk_in,
|
||||
&spdif_txclk,
|
||||
&spdif_rxclk,
|
||||
&ac97_clk,
|
||||
NULL
|
||||
};
|
||||
|
||||
static void rate_clk_init(struct clk *clk)
|
||||
{
|
||||
if (clk->calc) {
|
||||
clk->calc(clk);
|
||||
clk->flags |= CLK_HAS_RATE;
|
||||
clk_register(clk);
|
||||
} else {
|
||||
printk(KERN_WARNING
|
||||
"Could not initialize clk %s without a calc routine\n",
|
||||
clk->name);
|
||||
}
|
||||
}
|
||||
|
||||
static void rate_clks_init(void)
|
||||
{
|
||||
struct clk **cpp, *clk;
|
||||
|
||||
cpp = rate_clks;
|
||||
while ((clk = *cpp++))
|
||||
rate_clk_init(clk);
|
||||
}
|
||||
|
||||
/*
|
||||
* There are two clk enable registers with 32 enable bits each
|
||||
* psc clocks and device clocks are all stored in dev_clks
|
||||
*/
|
||||
struct clk dev_clks[2][32];
|
||||
|
||||
/*
|
||||
* Given a psc number return the dev_clk
|
||||
* associated with it
|
||||
*/
|
||||
static struct clk *psc_dev_clk(int pscnum)
|
||||
{
|
||||
int reg, bit;
|
||||
struct clk *clk;
|
||||
|
||||
reg = 0;
|
||||
bit = 27 - pscnum;
|
||||
|
||||
clk = &dev_clks[reg][bit];
|
||||
clk->reg = 0;
|
||||
clk->bit = bit;
|
||||
return clk;
|
||||
}
|
||||
|
||||
/*
|
||||
* PSC clock rate calculation
|
||||
*/
|
||||
static void psc_calc_rate(struct clk *clk, int pscnum, struct device_node *np)
|
||||
{
|
||||
unsigned long mclk_src = sys_clk.rate;
|
||||
unsigned long mclk_div;
|
||||
|
||||
/*
|
||||
* Can only change value of mclk divider
|
||||
* when the divider is disabled.
|
||||
*
|
||||
* Zero is not a valid divider so minimum
|
||||
* divider is 1
|
||||
*
|
||||
* disable/set divider/enable
|
||||
*/
|
||||
out_be32(&clockctl->pccr[pscnum], 0);
|
||||
out_be32(&clockctl->pccr[pscnum], 0x00020000);
|
||||
out_be32(&clockctl->pccr[pscnum], 0x00030000);
|
||||
|
||||
if (clockctl->pccr[pscnum] & 0x80) {
|
||||
clk->rate = spdif_rxclk.rate;
|
||||
return;
|
||||
}
|
||||
|
||||
switch ((clockctl->pccr[pscnum] >> 14) & 0x3) {
|
||||
case 0:
|
||||
mclk_src = sys_clk.rate;
|
||||
break;
|
||||
case 1:
|
||||
mclk_src = ref_clk.rate;
|
||||
break;
|
||||
case 2:
|
||||
mclk_src = psc_mclk_in.rate;
|
||||
break;
|
||||
case 3:
|
||||
mclk_src = spdif_txclk.rate;
|
||||
break;
|
||||
}
|
||||
|
||||
mclk_div = ((clockctl->pccr[pscnum] >> 17) & 0x7fff) + 1;
|
||||
clk->rate = mclk_src / mclk_div;
|
||||
}
|
||||
|
||||
/*
|
||||
* Find all psc nodes in device tree and assign a clock
|
||||
* with name "psc%d_mclk" and dev pointing at the device
|
||||
* returned from of_find_device_by_node
|
||||
*/
|
||||
static void psc_clks_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
const u32 *cell_index;
|
||||
struct of_device *ofdev;
|
||||
|
||||
for_each_compatible_node(np, NULL, "fsl,mpc5121-psc") {
|
||||
cell_index = of_get_property(np, "cell-index", NULL);
|
||||
if (cell_index) {
|
||||
int pscnum = *cell_index;
|
||||
struct clk *clk = psc_dev_clk(pscnum);
|
||||
|
||||
clk->flags = CLK_HAS_RATE | CLK_HAS_CTRL;
|
||||
ofdev = of_find_device_by_node(np);
|
||||
clk->dev = &ofdev->dev;
|
||||
/*
|
||||
* AC97 is special rate clock does
|
||||
* not go through normal path
|
||||
*/
|
||||
if (strcmp("ac97", np->name) == 0)
|
||||
clk->rate = ac97_clk.rate;
|
||||
else
|
||||
psc_calc_rate(clk, pscnum, np);
|
||||
sprintf(clk->name, "psc%d_mclk", pscnum);
|
||||
clk_register(clk);
|
||||
clk_enable(clk);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static struct clk_interface mpc5121_clk_functions = {
|
||||
.clk_get = mpc5121_clk_get,
|
||||
.clk_enable = mpc5121_clk_enable,
|
||||
.clk_disable = mpc5121_clk_disable,
|
||||
.clk_get_rate = mpc5121_clk_get_rate,
|
||||
.clk_put = mpc5121_clk_put,
|
||||
.clk_round_rate = mpc5121_clk_round_rate,
|
||||
.clk_set_rate = mpc5121_clk_set_rate,
|
||||
.clk_set_parent = NULL,
|
||||
.clk_get_parent = NULL,
|
||||
};
|
||||
|
||||
static int
|
||||
mpc5121_clk_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock");
|
||||
if (np) {
|
||||
clockctl = of_iomap(np, 0);
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
if (!clockctl) {
|
||||
printk(KERN_ERR "Could not map clock control registers\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
rate_clks_init();
|
||||
psc_clks_init();
|
||||
|
||||
/* leave clockctl mapped forever */
|
||||
/*iounmap(clockctl); */
|
||||
DEBUG_CLK_DUMP();
|
||||
clocks_initialized++;
|
||||
clk_functions = mpc5121_clk_functions;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
arch_initcall(mpc5121_clk_init);
|
||||
Loading…
Reference in a new issue