From dd1d78a11aecd68f5c688c3259c48b8ea4130aaa Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 25 Nov 2014 16:49:49 -0800 Subject: [PATCH 1/4] bus: brcmstb_gisb: Make the driver buildable on MIPS BCM7xxx ARM and MIPS platforms share a similar hardware block for reporting GISB errors, so they both benefit from the use of this driver. Conditionally compile the ARM-specific bus error handler so that the GISB error IRQ handler works on other architectures. Signed-off-by: Kevin Cernekee Signed-off-by: Florian Fainelli --- drivers/bus/Kconfig | 2 +- drivers/bus/brcmstb_gisb.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index 603eb1be4f6a..b99729e36860 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -6,7 +6,7 @@ menu "Bus devices" config BRCMSTB_GISB_ARB bool "Broadcom STB GISB bus arbiter" - depends on ARM + depends on ARM || MIPS help Driver for the Broadcom Set Top Box System-on-a-chip internal bus arbiter. This driver provides timeout and target abort error handling diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index f2cd6a2d40b4..5da935ad8d8b 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -24,8 +24,10 @@ #include #include +#ifdef CONFIG_ARM #include #include +#endif #define ARB_TIMER 0x008 #define ARB_ERR_CAP_CLR 0x7e4 @@ -141,6 +143,7 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev, return 0; } +#ifdef CONFIG_ARM static int brcmstb_bus_error_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) { @@ -165,6 +168,7 @@ void __init brcmstb_hook_fault_code(void) hook_fault_code(22, brcmstb_bus_error_handler, SIGBUS, 0, "imprecise external abort"); } +#endif static irqreturn_t brcmstb_gisb_timeout_handler(int irq, void *dev_id) { From 2b53eadcea05b680278f8d078b166e1e295e2a4f Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 25 Nov 2014 16:49:50 -0800 Subject: [PATCH 2/4] bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses These will be used to abstract out chip-to-chip differences. Signed-off-by: Kevin Cernekee Signed-off-by: Florian Fainelli --- drivers/bus/brcmstb_gisb.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index 5da935ad8d8b..8ff403da5d74 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -54,6 +54,16 @@ struct brcmstb_gisb_arb_device { static LIST_HEAD(brcmstb_gisb_arb_device_list); +static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg) +{ + return ioread32(gdev->base + reg); +} + +static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) +{ + iowrite32(val, gdev->base + reg); +} + static ssize_t gisb_arb_get_timeout(struct device *dev, struct device_attribute *attr, char *buf) @@ -63,7 +73,7 @@ static ssize_t gisb_arb_get_timeout(struct device *dev, u32 timeout; mutex_lock(&gdev->lock); - timeout = ioread32(gdev->base + ARB_TIMER); + timeout = gisb_read(gdev, ARB_TIMER); mutex_unlock(&gdev->lock); return sprintf(buf, "%d", timeout); @@ -85,7 +95,7 @@ static ssize_t gisb_arb_set_timeout(struct device *dev, return -EINVAL; mutex_lock(&gdev->lock); - iowrite32(val, gdev->base + ARB_TIMER); + gisb_write(gdev, val, ARB_TIMER); mutex_unlock(&gdev->lock); return count; @@ -112,18 +122,18 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev, const char *m_name; char m_fmt[11]; - cap_status = ioread32(gdev->base + ARB_ERR_CAP_STATUS); + cap_status = gisb_read(gdev, ARB_ERR_CAP_STATUS); /* Invalid captured address, bail out */ if (!(cap_status & ARB_ERR_CAP_STATUS_VALID)) return 1; /* Read the address and master */ - arb_addr = ioread32(gdev->base + ARB_ERR_CAP_ADDR) & 0xffffffff; + arb_addr = gisb_read(gdev, ARB_ERR_CAP_ADDR) & 0xffffffff; #if (IS_ENABLED(CONFIG_PHYS_ADDR_T_64BIT)) - arb_addr |= (u64)ioread32(gdev->base + ARB_ERR_CAP_HI_ADDR) << 32; + arb_addr |= (u64)gisb_read(gdev, ARB_ERR_CAP_HI_ADDR) << 32; #endif - master = ioread32(gdev->base + ARB_ERR_CAP_MASTER); + master = gisb_read(gdev, ARB_ERR_CAP_MASTER); m_name = brcmstb_gisb_master_to_str(gdev, master); if (!m_name) { @@ -138,7 +148,7 @@ static int brcmstb_gisb_arb_decode_addr(struct brcmstb_gisb_arb_device *gdev, m_name); /* clear the GISB error */ - iowrite32(ARB_ERR_CAP_CLEAR, gdev->base + ARB_ERR_CAP_CLR); + gisb_write(gdev, ARB_ERR_CAP_CLEAR, ARB_ERR_CAP_CLR); return 0; } From f80835875d3d1a4764711a90f6cc2669f037f527 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 25 Nov 2014 16:49:51 -0800 Subject: [PATCH 3/4] bus: brcmstb_gisb: Look up register offsets in a table There are at least 4 incompatible variations of this hardware block, so let's use the ARB_* constants as a table index instead of hardcoding specific register offsets. Also, allow for the possibility of adding old devices that are missing some of the registers. Signed-off-by: Kevin Cernekee Signed-off-by: Florian Fainelli --- drivers/bus/brcmstb_gisb.c | 42 ++++++++++++++++++++++++++++++-------- 1 file changed, 34 insertions(+), 8 deletions(-) diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index 8ff403da5d74..ef1e4238ef5f 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -29,23 +29,37 @@ #include #endif -#define ARB_TIMER 0x008 -#define ARB_ERR_CAP_CLR 0x7e4 #define ARB_ERR_CAP_CLEAR (1 << 0) -#define ARB_ERR_CAP_HI_ADDR 0x7e8 -#define ARB_ERR_CAP_ADDR 0x7ec -#define ARB_ERR_CAP_DATA 0x7f0 -#define ARB_ERR_CAP_STATUS 0x7f4 #define ARB_ERR_CAP_STATUS_TIMEOUT (1 << 12) #define ARB_ERR_CAP_STATUS_TEA (1 << 11) #define ARB_ERR_CAP_STATUS_BS_SHIFT (1 << 2) #define ARB_ERR_CAP_STATUS_BS_MASK 0x3c #define ARB_ERR_CAP_STATUS_WRITE (1 << 1) #define ARB_ERR_CAP_STATUS_VALID (1 << 0) -#define ARB_ERR_CAP_MASTER 0x7f8 + +enum { + ARB_TIMER, + ARB_ERR_CAP_CLR, + ARB_ERR_CAP_HI_ADDR, + ARB_ERR_CAP_ADDR, + ARB_ERR_CAP_DATA, + ARB_ERR_CAP_STATUS, + ARB_ERR_CAP_MASTER, +}; + +static const int gisb_offsets_bcm7445[] = { + [ARB_TIMER] = 0x008, + [ARB_ERR_CAP_CLR] = 0x7e4, + [ARB_ERR_CAP_HI_ADDR] = 0x7e8, + [ARB_ERR_CAP_ADDR] = 0x7ec, + [ARB_ERR_CAP_DATA] = 0x7f0, + [ARB_ERR_CAP_STATUS] = 0x7f4, + [ARB_ERR_CAP_MASTER] = 0x7f8, +}; struct brcmstb_gisb_arb_device { void __iomem *base; + const int *gisb_offsets; struct mutex lock; struct list_head next; u32 valid_mask; @@ -56,11 +70,21 @@ static LIST_HEAD(brcmstb_gisb_arb_device_list); static u32 gisb_read(struct brcmstb_gisb_arb_device *gdev, int reg) { - return ioread32(gdev->base + reg); + int offset = gdev->gisb_offsets[reg]; + + /* return 1 if the hardware doesn't have ARB_ERR_CAP_MASTER */ + if (offset == -1) + return 1; + + return ioread32(gdev->base + offset); } static void gisb_write(struct brcmstb_gisb_arb_device *gdev, u32 val, int reg) { + int offset = gdev->gisb_offsets[reg]; + + if (offset == -1) + return; iowrite32(val, gdev->base + reg); } @@ -230,6 +254,8 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev) if (IS_ERR(gdev->base)) return PTR_ERR(gdev->base); + gdev->gisb_offsets = gisb_offsets_bcm7445; + err = devm_request_irq(&pdev->dev, timeout_irq, brcmstb_gisb_timeout_handler, 0, pdev->name, gdev); From d1d6786846e1c40f780edb83569597a8a7769e95 Mon Sep 17 00:00:00 2001 From: Kevin Cernekee Date: Tue, 25 Nov 2014 16:49:52 -0800 Subject: [PATCH 4/4] bus: brcmstb_gisb: Add register offset tables for older chips This will select the appropriate register layout based on the DT "compatible" string. Signed-off-by: Kevin Cernekee Signed-off-by: Florian Fainelli --- .../devicetree/bindings/bus/brcm,gisb-arb.txt | 6 ++- drivers/bus/brcmstb_gisb.c | 52 ++++++++++++++++--- 2 files changed, 51 insertions(+), 7 deletions(-) diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt index e2d501d20c9a..1eceefb20f01 100644 --- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt +++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt @@ -2,7 +2,11 @@ Broadcom GISB bus Arbiter controller Required properties: -- compatible: should be "brcm,gisb-arb" +- compatible: + "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for 28nm chips + "brcm,bcm7435-gisb-arb" for newer 40nm chips + "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips + "brcm,bcm7038-gisb-arb" for 130nm chips - reg: specifies the base physical address and size of the registers - interrupt-parent: specifies the phandle to the parent interrupt controller this arbiter gets interrupt line from diff --git a/drivers/bus/brcmstb_gisb.c b/drivers/bus/brcmstb_gisb.c index ef1e4238ef5f..172908da5957 100644 --- a/drivers/bus/brcmstb_gisb.c +++ b/drivers/bus/brcmstb_gisb.c @@ -47,6 +47,36 @@ enum { ARB_ERR_CAP_MASTER, }; +static const int gisb_offsets_bcm7038[] = { + [ARB_TIMER] = 0x00c, + [ARB_ERR_CAP_CLR] = 0x0c4, + [ARB_ERR_CAP_HI_ADDR] = -1, + [ARB_ERR_CAP_ADDR] = 0x0c8, + [ARB_ERR_CAP_DATA] = 0x0cc, + [ARB_ERR_CAP_STATUS] = 0x0d0, + [ARB_ERR_CAP_MASTER] = -1, +}; + +static const int gisb_offsets_bcm7400[] = { + [ARB_TIMER] = 0x00c, + [ARB_ERR_CAP_CLR] = 0x0c8, + [ARB_ERR_CAP_HI_ADDR] = -1, + [ARB_ERR_CAP_ADDR] = 0x0cc, + [ARB_ERR_CAP_DATA] = 0x0d0, + [ARB_ERR_CAP_STATUS] = 0x0d4, + [ARB_ERR_CAP_MASTER] = 0x0d8, +}; + +static const int gisb_offsets_bcm7435[] = { + [ARB_TIMER] = 0x00c, + [ARB_ERR_CAP_CLR] = 0x168, + [ARB_ERR_CAP_HI_ADDR] = -1, + [ARB_ERR_CAP_ADDR] = 0x16c, + [ARB_ERR_CAP_DATA] = 0x170, + [ARB_ERR_CAP_STATUS] = 0x174, + [ARB_ERR_CAP_MASTER] = 0x178, +}; + static const int gisb_offsets_bcm7445[] = { [ARB_TIMER] = 0x008, [ARB_ERR_CAP_CLR] = 0x7e4, @@ -230,10 +260,20 @@ static struct attribute_group gisb_arb_sysfs_attr_group = { .attrs = gisb_arb_sysfs_attrs, }; +static const struct of_device_id brcmstb_gisb_arb_of_match[] = { + { .compatible = "brcm,gisb-arb", .data = gisb_offsets_bcm7445 }, + { .compatible = "brcm,bcm7445-gisb-arb", .data = gisb_offsets_bcm7445 }, + { .compatible = "brcm,bcm7435-gisb-arb", .data = gisb_offsets_bcm7435 }, + { .compatible = "brcm,bcm7400-gisb-arb", .data = gisb_offsets_bcm7400 }, + { .compatible = "brcm,bcm7038-gisb-arb", .data = gisb_offsets_bcm7038 }, + { }, +}; + static int brcmstb_gisb_arb_probe(struct platform_device *pdev) { struct device_node *dn = pdev->dev.of_node; struct brcmstb_gisb_arb_device *gdev; + const struct of_device_id *of_id; struct resource *r; int err, timeout_irq, tea_irq; unsigned int num_masters, j = 0; @@ -254,7 +294,12 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev) if (IS_ERR(gdev->base)) return PTR_ERR(gdev->base); - gdev->gisb_offsets = gisb_offsets_bcm7445; + of_id = of_match_node(brcmstb_gisb_arb_of_match, dn); + if (!of_id) { + pr_err("failed to look up compatible string\n"); + return -EINVAL; + } + gdev->gisb_offsets = of_id->data; err = devm_request_irq(&pdev->dev, timeout_irq, brcmstb_gisb_timeout_handler, 0, pdev->name, @@ -307,11 +352,6 @@ static int brcmstb_gisb_arb_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id brcmstb_gisb_arb_of_match[] = { - { .compatible = "brcm,gisb-arb" }, - { }, -}; - static struct platform_driver brcmstb_gisb_arb_driver = { .probe = brcmstb_gisb_arb_probe, .driver = {