drm/i915: Refactor save/restore code
We move the display-specific code into it's own functions, called from the general GPU state save/restore functions. This will be needed later by the GPU reset code. Signed-off-by: Ben Gamari <bgamari.foss@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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ffed1d0920
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2 changed files with 99 additions and 73 deletions
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@ -597,6 +597,8 @@ extern int i915_max_ioctl;
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extern unsigned int i915_fbpercrtc;
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extern unsigned int i915_powersave;
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extern void i915_save_display(struct drm_device *dev);
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extern void i915_restore_display(struct drm_device *dev);
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extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
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extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
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@ -228,6 +228,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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/* Pipe & plane A info */
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dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
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dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
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@ -285,6 +286,7 @@ static void i915_save_modeset_reg(struct drm_device *dev)
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dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
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return;
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}
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static void i915_restore_modeset_reg(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -379,19 +381,10 @@ static void i915_restore_modeset_reg(struct drm_device *dev)
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return;
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}
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int i915_save_state(struct drm_device *dev)
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void i915_save_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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/* Display arbitration control */
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dev_priv->saveDSPARB = I915_READ(DSPARB);
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@ -399,6 +392,7 @@ int i915_save_state(struct drm_device *dev)
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/* This is only meaningful in non-KMS mode */
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/* Don't save them in KMS mode */
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i915_save_modeset_reg(dev);
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/* Cursor state */
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dev_priv->saveCURACNTR = I915_READ(CURACNTR);
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dev_priv->saveCURAPOS = I915_READ(CURAPOS);
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@ -448,81 +442,22 @@ int i915_save_state(struct drm_device *dev)
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dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
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dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
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/* Interrupt state */
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dev_priv->saveIIR = I915_READ(IIR);
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dev_priv->saveIER = I915_READ(IER);
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dev_priv->saveIMR = I915_READ(IMR);
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/* VGA state */
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dev_priv->saveVGA0 = I915_READ(VGA0);
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dev_priv->saveVGA1 = I915_READ(VGA1);
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dev_priv->saveVGA_PD = I915_READ(VGA_PD);
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dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
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/* Clock gating state */
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dev_priv->saveD_STATE = I915_READ(D_STATE);
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dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D);
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/* Cache mode state */
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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for (i = 0; i < 16; i++) {
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dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
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dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
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}
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for (i = 0; i < 3; i++)
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dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
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} else {
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
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}
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i915_save_vga(dev);
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return 0;
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}
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int i915_restore_state(struct drm_device *dev)
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void i915_restore_display(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
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/* Hardware status page */
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I915_WRITE(HWS_PGA, dev_priv->saveHWS);
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/* Display arbitration */
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I915_WRITE(DSPARB, dev_priv->saveDSPARB);
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
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} else {
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
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}
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/* Display port ratios (must be done before clock is set) */
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if (SUPPORTS_INTEGRATED_DP(dev)) {
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I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
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@ -534,9 +469,11 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
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I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
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}
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/* This is only meaningful in non-KMS mode */
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/* Don't restore them in KMS mode */
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i915_restore_modeset_reg(dev);
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/* Cursor state */
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I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
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I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
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@ -586,6 +523,95 @@ int i915_restore_state(struct drm_device *dev)
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I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
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DRM_UDELAY(150);
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i915_restore_vga(dev);
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}
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int i915_save_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
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/* Hardware status page */
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dev_priv->saveHWS = I915_READ(HWS_PGA);
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i915_save_display(dev);
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/* Interrupt state */
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dev_priv->saveIER = I915_READ(IER);
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dev_priv->saveIMR = I915_READ(IMR);
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/* Clock gating state */
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dev_priv->saveD_STATE = I915_READ(D_STATE);
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dev_priv->saveDSPCLK_GATE_D = I915_READ(DSPCLK_GATE_D); /* Not sure about this */
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/* Cache mode state */
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dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
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/* Memory Arbitration state */
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dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
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/* Scratch space */
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for (i = 0; i < 16; i++) {
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dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
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dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
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}
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for (i = 0; i < 3; i++)
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dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
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} else {
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
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}
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return 0;
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}
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int i915_restore_state(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int i;
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pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
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/* Render Standby */
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if (IS_I965G(dev) && IS_MOBILE(dev))
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I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
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/* Hardware status page */
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I915_WRITE(HWS_PGA, dev_priv->saveHWS);
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/* Fences */
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if (IS_I965G(dev)) {
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for (i = 0; i < 16; i++)
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I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
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} else {
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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for (i = 0; i < 8; i++)
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I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
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}
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i915_restore_display(dev);
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/* Interrupt state */
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I915_WRITE (IER, dev_priv->saveIER);
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I915_WRITE (IMR, dev_priv->saveIMR);
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/* Clock gating state */
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I915_WRITE (D_STATE, dev_priv->saveD_STATE);
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I915_WRITE (DSPCLK_GATE_D, dev_priv->saveDSPCLK_GATE_D);
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@ -603,8 +629,6 @@ int i915_restore_state(struct drm_device *dev)
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for (i = 0; i < 3; i++)
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I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
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i915_restore_vga(dev);
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return 0;
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}
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