Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main MIPS pull request for 4.9: MIPS core arch code: - traps: 64bit kernels should read CP0_EBase 64bit - traps: Convert ebase to KSEG0 - c-r4k: Drop bc_wback_inv() from icache flush - c-r4k: Split user/kernel flush_icache_range() - cacheflush: Use __flush_icache_user_range() - uprobes: Flush icache via kernel address - KVM: Use __local_flush_icache_user_range() - c-r4k: Fix flush_icache_range() for EVA - Fix -mabi=64 build of vdso.lds - VDSO: Drop duplicated -I*/-E* aflags - tracing: move insn_has_delay_slot to a shared header - tracing: disable uprobe/kprobe on compact branch instructions - ptrace: Fix regs_return_value for kernel context - Squash lines for simple wrapper functions - Move identification of VP(E) into proc.c from smp-mt.c - Add definitions of SYNC barrierstype values - traps: Ensure full EBase is written - tlb-r4k: If there are wired entries, don't use TLBINVF - Sanitise coherentio semantics - dma-default: Don't check hw_coherentio if device is non-coherent - Support per-device DMA coherence - Adjust MIPS64 CAC_BASE to reflect Config.K0 - Support generating Flattened Image Trees (.itb) - generic: Introduce generic DT-based board support - generic: Convert SEAD-3 to a generic board - Enable hardened usercopy - Don't specify STACKPROTECTOR in defconfigs Octeon: - Delete dead code and files across the platform. - Change to use all memory into use by default. - Rename upper case variables in setup code to lowercase. - Delete legacy hack for broken bootloaders. - Leave maintaining the link state to the actual ethernet/PHY drivers. - Add DTS for D-Link DSR-500N. - Fix PCI interrupt routing on D-Link DSR-500N. Pistachio: - Remove ANDROID_TIMED_OUTPUT from defconfig TX39xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework TX49xx: - Move GPIO setup from .mem_setup() to .arch_init() - Convert to Common Clock Framework txx9wdt: - Add missing clock (un)prepare calls for CCF BMIPS: - Add PW, GPIO SDHCI and NAND device node names - Support APPENDED_DTB - Add missing bcm97435svmb to DT_NONE - Rename bcm96358nb4ser to bcm6358-neufbox4-sercom - Add DT examples for BCM63268, BCM3368 and BCM6362 - Add support for BCM3368 and BCM6362 PCI - Reduce stack frame usage - Use struct list_head lists - Support for CONFIG_PCI_DOMAINS_GENERIC - Make pcibios_set_cache_line_size an initcall - Inline pcibios_assign_all_busses - Split pci.c into pci.c & pci-legacy.c - Introduce CONFIG_PCI_DRIVERS_LEGACY - Support generic drivers CPC - Convert bare 'unsigned' to 'unsigned int' - Avoid lock when MIPS CM >= 3 is present GIC: - Delete unused file smp-gic.c mt7620: - Delete unnecessary assignment for the field "owner" from PCI BCM63xx: - Let clk_disable() return immediately if clk is NULL pm-cps: - Change FSB workaround to CPU blacklist - Update comments on barrier instructions - Use MIPS standard lightweight ordering barrier - Use MIPS standard completion barrier - Remove selection of sync types - Add MIPSr6 CPU support - Support CM3 changes to Coherence Enable Register SMP: - Wrap call to mips_cpc_lock_other in mips_cm_lock_other - Introduce mechanism for freeing and allocating IPIs cpuidle: - cpuidle-cps: Enable use with MIPSr6 CPUs. SEAD3: - Rewrite to use DT and generic kernel feature. USB: - host: ehci-sead3: Remove SEAD-3 EHCI code FBDEV: - cobalt_lcdfb: Drop SEAD3 support dt-bindings: - Document a binding for simple ASCII LCDs auxdisplay: - img-ascii-lcd: driver for simple ASCII LCD displays irqchip i8259: - i8259: Add domain before mapping parent irq - i8259: Allow platforms to override poll function - i8259: Remove unused i8259A_irq_pending Malta: - Rewrite to use DT of/platform: - Probe "isa" busses by default CM: - Print CM error reports upon bus errors Module: - Migrate exception table users off module.h and onto extable.h - Make various drivers explicitly non-modular: - Audit and remove any unnecessary uses of module.h mailmap: - Canonicalize to Qais' current email address. Documentation: - MIPS supports HAVE_REGS_AND_STACK_ACCESS_API Loongson1C: - Add CPU support for Loongson1C - Add board support - Add defconfig - Add RTC support for Loongson1C board All this except one Documentation fix has sat in linux-next and has survived Imagination's automated build test system" * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (127 commits) Documentation: MIPS supports HAVE_REGS_AND_STACK_ACCESS_API MIPS: ptrace: Fix regs_return_value for kernel context MIPS: VDSO: Drop duplicated -I*/-E* aflags MIPS: Fix -mabi=64 build of vdso.lds MIPS: Enable hardened usercopy MIPS: generic: Convert SEAD-3 to a generic board MIPS: generic: Introduce generic DT-based board support MIPS: Support generating Flattened Image Trees (.itb) MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 MIPS: Print CM error reports upon bus errors MIPS: Support per-device DMA coherence MIPS: dma-default: Don't check hw_coherentio if device is non-coherent MIPS: Sanitise coherentio semantics MIPS: PCI: Support generic drivers MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY MIPS: PCI: Split pci.c into pci.c & pci-legacy.c MIPS: PCI: Inline pcibios_assign_all_busses MIPS: PCI: Make pcibios_set_cache_line_size an initcall MIPS: PCI: Support for CONFIG_PCI_DOMAINS_GENERIC MIPS: PCI: Use struct list_head lists ...
This commit is contained in:
Linus Torvalds
commit
133d970e0d
226 changed files with 5242 additions and 3657 deletions
1
.mailmap
1
.mailmap
|
|
@ -127,6 +127,7 @@ Peter Oruba <peter@oruba.de>
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Peter Oruba <peter.oruba@amd.com>
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Pratyush Anand <pratyush.anand@gmail.com> <pratyush.anand@st.com>
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Praveen BP <praveenbp@ti.com>
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Qais Yousef <qsyousef@gmail.com> <qais.yousef@imgtec.com>
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Rajesh Shah <rajesh.shah@intel.com>
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Ralf Baechle <ralf@linux-mips.org>
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Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
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|
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@ -0,0 +1,17 @@
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Binding for ASCII LCD displays on Imagination Technologies boards
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Required properties:
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- compatible : should be one of:
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"img,boston-lcd"
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"mti,malta-lcd"
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"mti,sead3-lcd"
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Required properties for "img,boston-lcd":
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- reg : memory region locating the device registers
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Required properties for "mti,malta-lcd" or "mti,sead3-lcd":
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- regmap: phandle of the system controller containing the LCD registers
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- offset: offset in bytes to the LCD registers within the system controller
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The layout of the registers & properties of the display are determined
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from the compatible string, making this binding somewhat trivial.
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@ -2,9 +2,9 @@
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|||
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Required properties:
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- compatible: "brcm,bcm3384", "brcm,bcm33843"
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- compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
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"brcm,bcm3384-viper", "brcm,bcm33843-viper"
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"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6368",
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"brcm,bcm6328", "brcm,bcm6358", "brcm,bcm6362", "brcm,bcm6368",
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"brcm,bcm63168", "brcm,bcm63268",
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"brcm,bcm7125", "brcm,bcm7346", "brcm,bcm7358", "brcm,bcm7360",
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"brcm,bcm7362", "brcm,bcm7420", "brcm,bcm7425"
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|
|
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@ -22,7 +22,7 @@
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| m68k: | TODO |
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| metag: | TODO |
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| microblaze: | TODO |
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| mips: | TODO |
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| mips: | ok |
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| mn10300: | TODO |
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| nios2: | TODO |
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| openrisc: | TODO |
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|
|
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@ -6131,6 +6131,12 @@ M: Stanislaw Gruszka <stf_xl@wp.pl>
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S: Maintained
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F: drivers/usb/atm/ueagle-atm.c
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IMGTEC ASCII LCD DRIVER
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M: Paul Burton <paul.burton@imgtec.com>
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S: Maintained
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F: Documentation/devicetree/bindings/auxdisplay/img-ascii-lcd.txt
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F: drivers/auxdisplay/img-ascii-lcd.c
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INA209 HARDWARE MONITOR DRIVER
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M: Guenter Roeck <linux@roeck-us.net>
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L: linux-hwmon@vger.kernel.org
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|
|
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@ -11,6 +11,7 @@ platforms += cavium-octeon
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platforms += cobalt
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platforms += dec
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platforms += emma
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platforms += generic
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platforms += jazz
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platforms += jz4740
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platforms += lantiq
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@ -18,7 +19,6 @@ platforms += lasat
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platforms += loongson32
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platforms += loongson64
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platforms += mti-malta
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platforms += mti-sead3
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platforms += netlogic
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platforms += paravirt
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platforms += pic32
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|
|
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@ -65,6 +65,7 @@ config MIPS
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select HANDLE_DOMAIN_IRQ
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select HAVE_EXIT_THREAD
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_ARCH_HARDENED_USERCOPY
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menu "Machine selection"
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@ -72,6 +73,57 @@ choice
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prompt "System type"
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default SGI_IP22
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config MIPS_GENERIC
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bool "Generic board-agnostic MIPS kernel"
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select BOOT_RAW
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select BUILTIN_DTB
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select CEVT_R4K
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select CLKSRC_MIPS_GIC
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select COMMON_CLK
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select CSRC_R4K
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select DMA_PERDEV_COHERENT
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select HW_HAS_PCI
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select IRQ_MIPS_CPU
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select LIBFDT
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select MIPS_CPU_SCACHE
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select MIPS_GIC
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select MIPS_L1_CACHE_SHIFT_7
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select NO_EXCEPT_FILL
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select PCI_DRIVERS_GENERIC
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select PINCTRL
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select SMP_UP if SMP
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
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select SYS_HAS_CPU_MIPS64_R2
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select SYS_HAS_CPU_MIPS64_R6
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_HIGHMEM
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_SUPPORTS_MICROMIPS
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select SYS_SUPPORTS_MIPS_CPS
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select SYS_SUPPORTS_MIPS16
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select SYS_SUPPORTS_MULTITHREADING
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select SYS_SUPPORTS_RELOCATABLE
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select SYS_SUPPORTS_SMARTMIPS
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select USB_EHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
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select USB_EHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
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select USB_OHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
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select USB_OHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
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select USB_UHCI_BIG_ENDIAN_DESC if BIG_ENDIAN
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select USB_UHCI_BIG_ENDIAN_MMIO if BIG_ENDIAN
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select USE_OF
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help
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Select this to build a kernel which aims to support multiple boards,
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generally using a flattened device tree passed from the bootloader
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using the boot protocol defined in the UHI (Unified Hosting
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Interface) specification.
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config MIPS_ALCHEMY
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bool "Alchemy processor based machines"
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select ARCH_PHYS_ADDR_T_64BIT
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@ -478,6 +530,7 @@ config MIPS_MALTA
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select SYS_SUPPORTS_ZBOOT
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select SYS_SUPPORTS_RELOCATABLE
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select USE_OF
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select LIBFDT
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select ZONE_DMA32 if 64BIT
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select BUILTIN_DTB
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select LIBFDT
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|
@ -493,42 +546,6 @@ config MACH_PIC32
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Microchip PIC32 is a family of general-purpose 32 bit MIPS core
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microcontrollers.
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config MIPS_SEAD3
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bool "MIPS SEAD3 board"
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select BOOT_ELF32
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select BOOT_RAW
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select BUILTIN_DTB
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select CEVT_R4K
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select CSRC_R4K
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select CLKSRC_MIPS_GIC
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select COMMON_CLK
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select DMA_NONCOHERENT
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select IRQ_MIPS_CPU
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select MIPS_GIC
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select LIBFDT
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select MIPS_MSC
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_HAS_CPU_MIPS32_R2
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select SYS_HAS_CPU_MIPS32_R6
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select SYS_HAS_CPU_MIPS64_R1
|
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select SYS_HAS_EARLY_PRINTK
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_64BIT_KERNEL
|
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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||||
select SYS_SUPPORTS_SMARTMIPS
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select SYS_SUPPORTS_MICROMIPS
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select SYS_SUPPORTS_MIPS16
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select SYS_SUPPORTS_RELOCATABLE
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select USB_EHCI_BIG_ENDIAN_DESC
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select USB_EHCI_BIG_ENDIAN_MMIO
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select USE_OF
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help
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This enables support for the MIPS Technologies SEAD3 evaluation
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board.
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config NEC_MARKEINS
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bool "NEC EMMA2RH Mark-eins board"
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select SOC_EMMA2RH
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|
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@ -988,6 +1005,7 @@ source "arch/mips/ath79/Kconfig"
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source "arch/mips/bcm47xx/Kconfig"
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source "arch/mips/bcm63xx/Kconfig"
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source "arch/mips/bmips/Kconfig"
|
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source "arch/mips/generic/Kconfig"
|
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source "arch/mips/jazz/Kconfig"
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||||
source "arch/mips/jz4740/Kconfig"
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source "arch/mips/lantiq/Kconfig"
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|
|
@ -1098,6 +1116,10 @@ config DMA_MAYBE_COHERENT
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|||
select DMA_NONCOHERENT
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bool
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config DMA_PERDEV_COHERENT
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bool
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select DMA_MAYBE_COHERENT
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config DMA_COHERENT
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bool
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||||
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||||
|
|
@ -1401,6 +1423,16 @@ config CPU_LOONGSON1B
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|||
The Loongson 1B is a 32-bit SoC, which implements the MIPS32
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release 2 instruction set.
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config CPU_LOONGSON1C
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bool "Loongson 1C"
|
||||
depends on SYS_HAS_CPU_LOONGSON1C
|
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select CPU_LOONGSON1
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||||
select ARCH_WANT_OPTIONAL_GPIOLIB
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||||
select LEDS_GPIO_REGISTER
|
||||
help
|
||||
The Loongson 1C is a 32-bit SoC, which implements the MIPS32
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||||
release 2 instruction set.
|
||||
|
||||
config CPU_MIPS32_R1
|
||||
bool "MIPS32 Release 1"
|
||||
depends on SYS_HAS_CPU_MIPS32_R1
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||||
|
|
@ -1850,6 +1882,9 @@ config SYS_HAS_CPU_LOONGSON2F
|
|||
config SYS_HAS_CPU_LOONGSON1B
|
||||
bool
|
||||
|
||||
config SYS_HAS_CPU_LOONGSON1C
|
||||
bool
|
||||
|
||||
config SYS_HAS_CPU_MIPS32_R1
|
||||
bool
|
||||
|
||||
|
|
@ -2906,7 +2941,7 @@ endchoice
|
|||
choice
|
||||
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
|
||||
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
|
||||
!MIPS_MALTA && !MIPS_SEAD3 && \
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||||
!MIPS_MALTA && \
|
||||
!CAVIUM_OCTEON_SOC
|
||||
default MIPS_CMDLINE_FROM_BOOTLOADER
|
||||
|
||||
|
|
@ -2960,7 +2995,6 @@ config PCI
|
|||
bool "Support for PCI controller"
|
||||
depends on HW_HAS_PCI
|
||||
select PCI_DOMAINS
|
||||
select NO_GENERIC_PCI_IOPORT_MAP
|
||||
help
|
||||
Find out whether you have a PCI motherboard. PCI is the name of a
|
||||
bus system, i.e. the way the CPU talks to the other stuff inside
|
||||
|
|
@ -2981,6 +3015,17 @@ config HT_PCI
|
|||
config PCI_DOMAINS
|
||||
bool
|
||||
|
||||
config PCI_DOMAINS_GENERIC
|
||||
bool
|
||||
|
||||
config PCI_DRIVERS_GENERIC
|
||||
select PCI_DOMAINS_GENERIC if PCI_DOMAINS
|
||||
bool
|
||||
|
||||
config PCI_DRIVERS_LEGACY
|
||||
def_bool !PCI_DRIVERS_GENERIC
|
||||
select NO_GENERIC_PCI_IOPORT_MAP
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
#
|
||||
|
|
|
|||
|
|
@ -262,7 +262,14 @@ KBUILD_CPPFLAGS += -DVMLINUX_LOAD_ADDRESS=$(load-y)
|
|||
KBUILD_CPPFLAGS += -DDATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)
|
||||
|
||||
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y) \
|
||||
VMLINUX_ENTRY_ADDRESS=$(entry-y)
|
||||
VMLINUX_ENTRY_ADDRESS=$(entry-y) \
|
||||
PLATFORM=$(platform-y)
|
||||
ifdef CONFIG_32BIT
|
||||
bootvars-y += ADDR_BITS=32
|
||||
endif
|
||||
ifdef CONFIG_64BIT
|
||||
bootvars-y += ADDR_BITS=64
|
||||
endif
|
||||
|
||||
LDFLAGS += -m $(ld-emul)
|
||||
|
||||
|
|
@ -302,6 +309,11 @@ boot-y += uImage.gz
|
|||
boot-y += uImage.lzma
|
||||
boot-y += uImage.lzo
|
||||
endif
|
||||
boot-y += vmlinux.itb
|
||||
boot-y += vmlinux.gz.itb
|
||||
boot-y += vmlinux.bz2.itb
|
||||
boot-y += vmlinux.lzma.itb
|
||||
boot-y += vmlinux.lzo.itb
|
||||
|
||||
# compressed boot image targets (arch/mips/boot/compressed/)
|
||||
bootz-y := vmlinuz
|
||||
|
|
@ -425,4 +437,67 @@ define archhelp
|
|||
echo ' dtbs_install - Install dtbs to $(INSTALL_DTBS_PATH)'
|
||||
echo
|
||||
echo ' These will be default as appropriate for a configured platform.'
|
||||
echo
|
||||
echo ' If you are targeting a system supported by generic kernels you may'
|
||||
echo ' configure the kernel for a given architecture target like so:'
|
||||
echo
|
||||
echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
|
||||
echo
|
||||
echo ' Otherwise, the following default configurations are available:'
|
||||
endef
|
||||
|
||||
generic_config_dir = $(srctree)/arch/$(ARCH)/configs/generic
|
||||
generic_defconfigs :=
|
||||
|
||||
#
|
||||
# If the user generates a generic kernel configuration without specifying a
|
||||
# list of boards to include the config fragments for, default to including all
|
||||
# available board config fragments.
|
||||
#
|
||||
ifeq ($(BOARDS),)
|
||||
BOARDS = $(patsubst board-%.config,%,$(notdir $(wildcard $(generic_config_dir)/board-*.config)))
|
||||
endif
|
||||
|
||||
#
|
||||
# Generic kernel configurations which merge generic_defconfig with the
|
||||
# appropriate config fragments from arch/mips/configs/generic/, resulting in
|
||||
# the ability to easily configure the kernel for a given architecture,
|
||||
# endianness & set of boards without duplicating the needed configuration in
|
||||
# hundreds of defconfig files.
|
||||
#
|
||||
define gen_generic_defconfigs
|
||||
$(foreach bits,$(1),$(foreach rev,$(2),$(foreach endian,$(3),
|
||||
target := $(bits)$(rev)$(filter el,$(endian))_defconfig
|
||||
generic_defconfigs += $$(target)
|
||||
$$(target): $(generic_config_dir)/$(bits)$(rev).config
|
||||
$$(target): $(generic_config_dir)/$(endian).config
|
||||
)))
|
||||
endef
|
||||
|
||||
$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el))
|
||||
$(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
|
||||
|
||||
.PHONY: $(generic_defconfigs)
|
||||
$(generic_defconfigs):
|
||||
$(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
|
||||
-m -O $(objtree) $(srctree)/arch/$(ARCH)/configs/generic_defconfig $^ \
|
||||
$(foreach board,$(BOARDS),$(generic_config_dir)/board-$(board).config)
|
||||
$(Q)$(MAKE) olddefconfig
|
||||
|
||||
#
|
||||
# Prevent generic merge_config rules attempting to merge single fragments
|
||||
#
|
||||
$(generic_config_dir)/%.config: ;
|
||||
|
||||
#
|
||||
# Legacy defconfig compatibility - these targets used to be real defconfigs but
|
||||
# now that the boards have been converted to use the generic kernel they are
|
||||
# wrappers around the generic rules above.
|
||||
#
|
||||
.PHONY: sead3_defconfig
|
||||
sead3_defconfig:
|
||||
$(Q)$(MAKE) 32r2el_defconfig BOARDS=sead-3
|
||||
|
||||
.PHONY: sead3micro_defconfig
|
||||
sead3micro_defconfig:
|
||||
$(Q)$(MAKE) micro32r2el_defconfig BOARDS=sead-3
|
||||
|
|
|
|||
|
|
@ -48,17 +48,17 @@ void __init plat_mem_setup(void)
|
|||
clear_c0_config(1 << 19); /* Clear Config[OD] */
|
||||
|
||||
hw_coherentio = 0;
|
||||
coherentio = 1;
|
||||
coherentio = IO_COHERENCE_ENABLED;
|
||||
switch (alchemy_get_cputype()) {
|
||||
case ALCHEMY_CPU_AU1000:
|
||||
case ALCHEMY_CPU_AU1500:
|
||||
case ALCHEMY_CPU_AU1100:
|
||||
coherentio = 0;
|
||||
coherentio = IO_COHERENCE_DISABLED;
|
||||
break;
|
||||
case ALCHEMY_CPU_AU1200:
|
||||
/* Au1200 AB USB does not support coherent memory */
|
||||
if (0 == (read_c0_prid() & PRID_REV_MASK))
|
||||
coherentio = 0;
|
||||
coherentio = IO_COHERENCE_DISABLED;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,7 @@
|
|||
/*
|
||||
* 8250 UART probe driver for the BCM47XX platforms
|
||||
* Author: Aurelien Jarno
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
|
|
@ -6,7 +9,6 @@
|
|||
* Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <linux/serial_8250.h>
|
||||
|
|
@ -88,9 +90,4 @@ static int __init uart8250_init(void)
|
|||
}
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
module_init(uart8250_init);
|
||||
|
||||
MODULE_AUTHOR("Aurelien Jarno <aurelien@aurel32.net>");
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_DESCRIPTION("8250 UART probe driver for the BCM47XX platforms");
|
||||
device_initcall(uart8250_init);
|
||||
|
|
|
|||
|
|
@ -326,6 +326,9 @@ EXPORT_SYMBOL(clk_enable);
|
|||
|
||||
void clk_disable(struct clk *clk)
|
||||
{
|
||||
if (!clk)
|
||||
return;
|
||||
|
||||
mutex_lock(&clocks_mutex);
|
||||
clk_disable_unlocked(clk);
|
||||
mutex_unlock(&clocks_mutex);
|
||||
|
|
|
|||
|
|
@ -21,10 +21,6 @@ config DT_BCM93384WVG_VIPER
|
|||
bool "BCM93384WVG Viper CPU (EXPERIMENTAL)"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM96358NB4SER
|
||||
bool "BCM96358NB4SER"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_BCM96368MVWG
|
||||
bool "BCM96368MVWG"
|
||||
select BUILTIN_DTB
|
||||
|
|
@ -65,6 +61,22 @@ config DT_BCM97435SVMB
|
|||
bool "BCM97435SVMB"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_COMTREND_VR3032U
|
||||
bool "Comtrend VR-3032u"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_NETGEAR_CVG834G
|
||||
bool "NETGEAR CVG834G"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_SFR_NEUFBOX4_SERCOMM
|
||||
bool "SFR Neufbox 4 (Sercomm)"
|
||||
select BUILTIN_DTB
|
||||
|
||||
config DT_SFR_NEUFBOX6_SERCOMM
|
||||
bool "SFR Neufbox 6 (Sercomm)"
|
||||
select BUILTIN_DTB
|
||||
|
||||
endchoice
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/addrspace.h>
|
||||
#include <asm/bmips.h>
|
||||
|
|
@ -98,7 +99,7 @@ static void bcm6328_quirks(void)
|
|||
static void bcm6358_quirks(void)
|
||||
{
|
||||
/*
|
||||
* BCM6358 needs special handling for its shared TLB, so
|
||||
* BCM3368/BCM6358 need special handling for their shared TLB, so
|
||||
* disable SMP for now
|
||||
*/
|
||||
bmips_smp_enabled = 0;
|
||||
|
|
@ -110,10 +111,12 @@ static void bcm6368_quirks(void)
|
|||
}
|
||||
|
||||
static const struct bmips_quirk bmips_quirk_list[] = {
|
||||
{ "brcm,bcm3368", &bcm6358_quirks },
|
||||
{ "brcm,bcm3384-viper", &bcm3384_viper_quirks },
|
||||
{ "brcm,bcm33843-viper", &bcm3384_viper_quirks },
|
||||
{ "brcm,bcm6328", &bcm6328_quirks },
|
||||
{ "brcm,bcm6358", &bcm6358_quirks },
|
||||
{ "brcm,bcm6362", &bcm6368_quirks },
|
||||
{ "brcm,bcm6368", &bcm6368_quirks },
|
||||
{ "brcm,bcm63168", &bcm6368_quirks },
|
||||
{ "brcm,bcm63268", &bcm6368_quirks },
|
||||
|
|
@ -150,6 +153,8 @@ void __init plat_time_init(void)
|
|||
mips_hpt_frequency = freq;
|
||||
}
|
||||
|
||||
extern const char __appended_dtb;
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
void *dtb;
|
||||
|
|
@ -159,6 +164,11 @@ void __init plat_mem_setup(void)
|
|||
ioport_resource.start = 0;
|
||||
ioport_resource.end = ~0;
|
||||
|
||||
#ifdef CONFIG_MIPS_ELF_APPENDED_DTB
|
||||
if (!fdt_check_header(&__appended_dtb))
|
||||
dtb = (void *)&__appended_dtb;
|
||||
else
|
||||
#endif
|
||||
/* intended to somewhat resemble ARM; see Documentation/arm/Booting */
|
||||
if (fw_arg0 == 0 && fw_arg1 == 0xffffffff)
|
||||
dtb = phys_to_virt(fw_arg2);
|
||||
|
|
|
|||
|
|
@ -100,3 +100,69 @@ $(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo FORCE
|
|||
$(obj)/uImage: $(obj)/uImage.$(suffix-y)
|
||||
@ln -sf $(notdir $<) $@
|
||||
@echo ' Image $@ is ready'
|
||||
|
||||
#
|
||||
# Flattened Image Tree (.itb) images
|
||||
#
|
||||
|
||||
targets += vmlinux.itb
|
||||
targets += vmlinux.gz.itb
|
||||
targets += vmlinux.bz2.itb
|
||||
targets += vmlinux.lzma.itb
|
||||
targets += vmlinux.lzo.itb
|
||||
|
||||
ifeq ($(ADDR_BITS),32)
|
||||
itb_addr_cells = 1
|
||||
endif
|
||||
ifeq ($(ADDR_BITS),64)
|
||||
itb_addr_cells = 2
|
||||
endif
|
||||
|
||||
quiet_cmd_cpp_its_S = ITS $@
|
||||
cmd_cpp_its_S = $(CPP) $(cpp_flags) -P -C -o $@ $< \
|
||||
-DKERNEL_NAME="\"Linux $(KERNELRELEASE)\"" \
|
||||
-DVMLINUX_BINARY="\"$(3)\"" \
|
||||
-DVMLINUX_COMPRESSION="\"$(2)\"" \
|
||||
-DVMLINUX_LOAD_ADDRESS=$(VMLINUX_LOAD_ADDRESS) \
|
||||
-DVMLINUX_ENTRY_ADDRESS=$(VMLINUX_ENTRY_ADDRESS) \
|
||||
-DADDR_BITS=$(ADDR_BITS) \
|
||||
-DADDR_CELLS=$(itb_addr_cells)
|
||||
|
||||
$(obj)/vmlinux.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
|
||||
$(call if_changed_dep,cpp_its_S,none,vmlinux.bin)
|
||||
|
||||
$(obj)/vmlinux.gz.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
|
||||
$(call if_changed_dep,cpp_its_S,gzip,vmlinux.bin.gz)
|
||||
|
||||
$(obj)/vmlinux.bz2.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
|
||||
$(call if_changed_dep,cpp_its_S,bzip2,vmlinux.bin.bz2)
|
||||
|
||||
$(obj)/vmlinux.lzma.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
|
||||
$(call if_changed_dep,cpp_its_S,lzma,vmlinux.bin.lzma)
|
||||
|
||||
$(obj)/vmlinux.lzo.its: $(srctree)/arch/mips/$(PLATFORM)/vmlinux.its.S FORCE
|
||||
$(call if_changed_dep,cpp_its_S,lzo,vmlinux.bin.lzo)
|
||||
|
||||
quiet_cmd_itb-image = ITB $@
|
||||
cmd_itb-image = \
|
||||
env PATH="$(objtree)/scripts/dtc:$(PATH)" \
|
||||
$(CONFIG_SHELL) $(MKIMAGE) \
|
||||
-D "-I dts -O dtb -p 500 \
|
||||
--include $(objtree)/arch/mips \
|
||||
--warning no-unit_address_vs_reg" \
|
||||
-f $(2) $@
|
||||
|
||||
$(obj)/vmlinux.itb: $(obj)/vmlinux.its $(obj)/vmlinux.bin FORCE
|
||||
$(call if_changed,itb-image,$<)
|
||||
|
||||
$(obj)/vmlinux.gz.itb: $(obj)/vmlinux.gz.its $(obj)/vmlinux.bin.gz FORCE
|
||||
$(call if_changed,itb-image,$<)
|
||||
|
||||
$(obj)/vmlinux.bz2.itb: $(obj)/vmlinux.bz2.its $(obj)/vmlinux.bin.bz2 FORCE
|
||||
$(call if_changed,itb-image,$<)
|
||||
|
||||
$(obj)/vmlinux.lzma.itb: $(obj)/vmlinux.lzma.its $(obj)/vmlinux.bin.lzma FORCE
|
||||
$(call if_changed,itb-image,$<)
|
||||
|
||||
$(obj)/vmlinux.lzo.itb: $(obj)/vmlinux.lzo.its $(obj)/vmlinux.bin.lzo FORCE
|
||||
$(call if_changed,itb-image,$<)
|
||||
|
|
|
|||
|
|
@ -1,6 +1,5 @@
|
|||
dtb-$(CONFIG_DT_BCM93384WVG) += bcm93384wvg.dtb
|
||||
dtb-$(CONFIG_DT_BCM93384WVG_VIPER) += bcm93384wvg_viper.dtb
|
||||
dtb-$(CONFIG_DT_BCM96358NB4SER) += bcm96358nb4ser.dtb
|
||||
dtb-$(CONFIG_DT_BCM96368MVWG) += bcm96368mvwg.dtb
|
||||
dtb-$(CONFIG_DT_BCM9EJTAGPRB) += bcm9ejtagprb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97125CBMB) += bcm97125cbmb.dtb
|
||||
|
|
@ -11,20 +10,29 @@ dtb-$(CONFIG_DT_BCM97362SVMB) += bcm97362svmb.dtb
|
|||
dtb-$(CONFIG_DT_BCM97420C) += bcm97420c.dtb
|
||||
dtb-$(CONFIG_DT_BCM97425SVMB) += bcm97425svmb.dtb
|
||||
dtb-$(CONFIG_DT_BCM97435SVMB) += bcm97435svmb.dtb
|
||||
dtb-$(CONFIG_DT_COMTREND_VR3032U) += bcm63268-comtrend-vr-3032u.dtb
|
||||
dtb-$(CONFIG_DT_NETGEAR_CVG834G) += bcm3368-netgear-cvg834g.dtb
|
||||
dtb-$(CONFIG_DT_SFR_NEUFBOX4_SERCOMM) += bcm6358-neufbox4-sercomm.dtb
|
||||
dtb-$(CONFIG_DT_SFR_NEUFBOX6_SERCOMM) += bcm6362-neufbox6-sercomm.dtb
|
||||
|
||||
dtb-$(CONFIG_DT_NONE) += \
|
||||
bcm93384wvg.dtb \
|
||||
bcm93384wvg_viper.dtb \
|
||||
bcm96358nb4ser.dtb \
|
||||
bcm96368mvwg.dtb \
|
||||
bcm9ejtagprb.dtb \
|
||||
bcm97125cbmb.dtb \
|
||||
bcm97346dbsmb.dtb \
|
||||
bcm97358svmb.dtb \
|
||||
bcm97360svmb.dtb \
|
||||
bcm97362svmb.dtb \
|
||||
bcm97420c.dtb \
|
||||
bcm97425svmb.dtb
|
||||
dtb-$(CONFIG_DT_NONE) += \
|
||||
bcm3368-netgear-cvg834g.dtb \
|
||||
bcm6358-neufbox4-sercomm.dtb \
|
||||
bcm6362-neufbox6-sercomm.dtb \
|
||||
bcm63268-comtrend-vr-3032u.dtb \
|
||||
bcm93384wvg.dtb \
|
||||
bcm93384wvg_viper.dtb \
|
||||
bcm96358nb4ser.dtb \
|
||||
bcm96368mvwg.dtb \
|
||||
bcm9ejtagprb.dtb \
|
||||
bcm97125cbmb.dtb \
|
||||
bcm97346dbsmb.dtb \
|
||||
bcm97358svmb.dtb \
|
||||
bcm97360svmb.dtb \
|
||||
bcm97362svmb.dtb \
|
||||
bcm97420c.dtb \
|
||||
bcm97425svmb.dtb \
|
||||
bcm97435svmb.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
|
|
|
|||
22
arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts
Normal file
22
arch/mips/boot/dts/brcm/bcm3368-netgear-cvg834g.dts
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm3368.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "netgear,cvg834g", "brcm,bcm3368";
|
||||
model = "NETGEAR CVG834G";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x02000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
101
arch/mips/boot/dts/brcm/bcm3368.dtsi
Normal file
101
arch/mips/boot/dts/brcm/bcm3368.dtsi
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm3368";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <150000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
periph_cntl: syscon@fff8c000 {
|
||||
compatible = "syscon";
|
||||
reg = <0xfff8c000 0xc>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
reboot: syscon-reboot@fff8c008 {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&periph_cntl>;
|
||||
offset = <0x8>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_intc: interrupt-controller@fff8c00c {
|
||||
compatible = "brcm,bcm6345-l1-intc";
|
||||
reg = <0xfff8c00c 0x8>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>;
|
||||
};
|
||||
|
||||
uart0: serial@fff8c100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfff8c100 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <2>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@fff8c120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0xfff8c120 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
108
arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts
Normal file
108
arch/mips/boot/dts/brcm/bcm63268-comtrend-vr-3032u.dts
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm63268.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "comtrend,vr-3032u", "brcm,bcm63268";
|
||||
model = "Comtrend VR-3032u";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x04000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&leds0 {
|
||||
status = "ok";
|
||||
brcm,serial-leds;
|
||||
brcm,serial-dat-low;
|
||||
brcm,serial-shift-inv;
|
||||
|
||||
led@0 {
|
||||
reg = <0>;
|
||||
brcm,hardware-controlled;
|
||||
brcm,link-signal-sources = <0>;
|
||||
/* GPHY0 Speed 0 */
|
||||
};
|
||||
led@1 {
|
||||
reg = <1>;
|
||||
brcm,hardware-controlled;
|
||||
brcm,link-signal-sources = <1>;
|
||||
/* GPHY0 Speed 1 */
|
||||
};
|
||||
led@2 {
|
||||
reg = <2>;
|
||||
active-low;
|
||||
label = "vr-3032u:red:inet";
|
||||
};
|
||||
led@3 {
|
||||
reg = <3>;
|
||||
active-low;
|
||||
label = "vr-3032u:green:dsl";
|
||||
};
|
||||
led@4 {
|
||||
reg = <4>;
|
||||
active-low;
|
||||
label = "vr-3032u:green:usb";
|
||||
};
|
||||
led@7 {
|
||||
reg = <7>;
|
||||
active-low;
|
||||
label = "vr-3032u:green:wps";
|
||||
};
|
||||
led@8 {
|
||||
reg = <8>;
|
||||
active-low;
|
||||
label = "vr-3032u:green:inet";
|
||||
};
|
||||
led@9 {
|
||||
reg = <9>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY0 Activity */
|
||||
};
|
||||
led@10 {
|
||||
reg = <10>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY1 Activity */
|
||||
};
|
||||
led@11 {
|
||||
reg = <11>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY2 Activity */
|
||||
};
|
||||
led@12 {
|
||||
reg = <12>;
|
||||
brcm,hardware-controlled;
|
||||
/* GPHY0 Activity */
|
||||
};
|
||||
led@13 {
|
||||
reg = <13>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY0 Speed */
|
||||
};
|
||||
led@14 {
|
||||
reg = <14>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY1 Speed */
|
||||
};
|
||||
led@15 {
|
||||
reg = <15>;
|
||||
brcm,hardware-controlled;
|
||||
/* EPHY2 Speed */
|
||||
};
|
||||
led@20 {
|
||||
reg = <20>;
|
||||
active-low;
|
||||
label = "vr-3032u:green:power";
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
134
arch/mips/boot/dts/brcm/bcm63268.dtsi
Normal file
134
arch/mips/boot/dts/brcm/bcm63268.dtsi
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm63268";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <200000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
periph_cntl: syscon@10000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0x14>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
reboot: syscon-reboot@10000008 {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&periph_cntl>;
|
||||
offset = <0x8>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_intc: interrupt-controller@10000020 {
|
||||
compatible = "brcm,bcm6345-l1-intc";
|
||||
reg = <0x10000020 0x20>,
|
||||
<0x10000040 0x20>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
uart0: serial@10000180 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000180 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <5>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@100001a0 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x100001a0 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <34>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds0: led-controller@10001900 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10001900 0x24>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci: usb@10002500 {
|
||||
compatible = "brcm,bcm63268-ehci", "generic-ehci";
|
||||
reg = <0x10002500 0x100>;
|
||||
big-endian;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb@10002600 {
|
||||
compatible = "brcm,bcm63268-ohci", "generic-ohci";
|
||||
reg = <0x10002600 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <9>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -12,6 +12,7 @@
|
|||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
22
arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts
Normal file
22
arch/mips/boot/dts/brcm/bcm6362-neufbox6-sercomm.dts
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm6362.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "sfr,nb6-ser", "brcm,bcm6362";
|
||||
model = "SFR NeufBox 6 (Sercomm)";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
134
arch/mips/boot/dts/brcm/bcm6362.dtsi
Normal file
134
arch/mips/boot/dts/brcm/bcm6362.dtsi
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "brcm,bcm6362";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mips-hpt-frequency = <200000000>;
|
||||
|
||||
cpu@0 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
compatible = "brcm,bmips4350";
|
||||
device_type = "cpu";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
periph_clk: periph-clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
ubus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
periph_cntl: syscon@10000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x10000000 0x14>;
|
||||
native-endian;
|
||||
};
|
||||
|
||||
reboot: syscon-reboot@10000008 {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&periph_cntl>;
|
||||
offset = <0x8>;
|
||||
mask = <0x1>;
|
||||
};
|
||||
|
||||
periph_intc: interrupt-controller@10000020 {
|
||||
compatible = "brcm,bcm6345-l1-intc";
|
||||
reg = <0x10000020 0x10>,
|
||||
<0x10000030 0x10>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
uart0: serial@10000100 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000100 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <3>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@10000120 {
|
||||
compatible = "brcm,bcm6345-uart";
|
||||
reg = <0x10000120 0x18>;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <4>;
|
||||
|
||||
clocks = <&periph_clk>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
leds0: led-controller@10001900 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "brcm,bcm6328-leds";
|
||||
reg = <0x10001900 0x24>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehci: usb@10002500 {
|
||||
compatible = "brcm,bcm6362-ehci", "generic-ehci";
|
||||
reg = <0x10002500 0x100>;
|
||||
big-endian;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ohci: usb@10002600 {
|
||||
compatible = "brcm,bcm6362-ohci", "generic-ohci";
|
||||
reg = <0x10002600 0x100>;
|
||||
big-endian;
|
||||
no-big-frame-no;
|
||||
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <9>;
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -26,7 +26,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -40,6 +40,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -49,7 +55,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@441400 {
|
||||
periph_intc: interrupt-controller@441400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x441400 0x30>, <0x441600 0x30>;
|
||||
|
||||
|
|
@ -60,7 +66,7 @@
|
|||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@401800 {
|
||||
sun_l2_intc: interrupt-controller@401800 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x401800 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -81,7 +87,7 @@
|
|||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
upg_irq0_intc: interrupt-controller@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
|
|
@ -183,6 +189,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406580 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406580 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 18>;
|
||||
};
|
||||
|
||||
ehci0: usb@488300 {
|
||||
compatible = "brcm,bcm7125-ehci", "generic-ehci";
|
||||
reg = <0x488300 0x100>;
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -40,6 +40,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -49,7 +55,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
periph_intc: interrupt-controller@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>, <0x411600 0x30>;
|
||||
|
||||
|
|
@ -60,7 +66,7 @@
|
|||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -81,7 +87,7 @@
|
|||
"jtag_0", "svd_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
upg_irq0_intc: interrupt-controller@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
|
|
@ -96,7 +102,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
|
||||
upg_aon_irq0_intc: interrupt-controller@408b80 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x408b80 0x8>;
|
||||
|
||||
|
|
@ -210,6 +216,59 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406580 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406580 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwmb: pwm@406800 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406800 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <53>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x60>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 16>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@408c00 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x408c00 0x60>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <27 32 2>;
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -313,6 +372,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@411000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x411000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
nand: nand@412800 {
|
||||
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand";
|
||||
reg = <0x412800 0x400>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@181000 {
|
||||
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
|
|
@ -352,5 +431,13 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0: sdhci@413500 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x413500 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <85>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -34,6 +34,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -43,7 +49,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
periph_intc: interrupt-controller@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>;
|
||||
|
||||
|
|
@ -54,7 +60,7 @@
|
|||
interrupts = <2>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -75,7 +81,7 @@
|
|||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
upg_irq0_intc: interrupt-controller@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
|
|
@ -90,7 +96,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
|
||||
upg_aon_irq0_intc: interrupt-controller@408b80 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x408b80 0x8>;
|
||||
|
||||
|
|
@ -194,6 +200,59 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406400 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406400 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwmb: pwm@406700 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406700 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408240 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408240 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <50>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406500 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406500 0xa0>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 29 4>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@408c00 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x408c00 0x60>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <21 32 2>;
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -239,5 +298,25 @@
|
|||
interrupts = <66>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@411000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x411000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
nand: nand@412800 {
|
||||
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand";
|
||||
reg = <0x412800 0x400>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -34,6 +34,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -43,7 +49,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
periph_intc: interrupt-controller@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>;
|
||||
|
||||
|
|
@ -54,7 +60,7 @@
|
|||
interrupts = <2>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -75,7 +81,7 @@
|
|||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
upg_irq0_intc: interrupt-controller@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
|
|
@ -90,7 +96,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
|
||||
upg_aon_irq0_intc: interrupt-controller@408b80 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x408b80 0x8>;
|
||||
|
||||
|
|
@ -194,6 +200,51 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406400 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406400 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <50>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406500 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406500 0xa0>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 29 4>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@408c00 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x408c00 0x60>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <21 32 2>;
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -240,6 +291,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@411000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x411000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
nand: nand@412800 {
|
||||
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand";
|
||||
reg = <0x412800 0x400>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@181000 {
|
||||
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
|
|
@ -279,5 +350,13 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0: sdhci@410000 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x410000 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <82>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -40,6 +40,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -49,7 +55,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@411400 {
|
||||
periph_intc: interrupt-controller@411400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x411400 0x30>, <0x411600 0x30>;
|
||||
|
||||
|
|
@ -60,7 +66,7 @@
|
|||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -81,7 +87,7 @@
|
|||
"avd_0", "jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406600 {
|
||||
upg_irq0_intc: interrupt-controller@406600 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406600 0x8>;
|
||||
|
||||
|
|
@ -96,7 +102,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
|
||||
upg_aon_irq0_intc: interrupt-controller@408b80 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x408b80 0x8>;
|
||||
|
||||
|
|
@ -190,6 +196,51 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406400 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406400 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <50>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406500 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406500 0xa0>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 29 4>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@408c00 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x408c00 0x60>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <21 32 2>;
|
||||
};
|
||||
|
||||
enet0: ethernet@430000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -236,6 +287,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@411000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x411000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <30>;
|
||||
};
|
||||
|
||||
nand: nand@412800 {
|
||||
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand";
|
||||
reg = <0x412800 0x400>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@181000 {
|
||||
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
|
|
@ -275,5 +346,13 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0: sdhci@410000 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x410000 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <82>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -40,6 +40,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -49,7 +55,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@441400 {
|
||||
periph_intc: interrupt-controller@441400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x441400 0x30>, <0x441600 0x30>;
|
||||
|
||||
|
|
@ -60,7 +66,7 @@
|
|||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@401800 {
|
||||
sun_l2_intc: interrupt-controller@401800 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x401800 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -82,7 +88,7 @@
|
|||
"jtag_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
upg_irq0_intc: interrupt-controller@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
|
|
@ -191,6 +197,34 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406580 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406580 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwmb: pwm@406880 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406880 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 27>;
|
||||
};
|
||||
|
||||
enet0: ethernet@468000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -40,6 +40,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -49,7 +55,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@41a400 {
|
||||
periph_intc: interrupt-controller@41a400 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x41a400 0x30>, <0x41a600 0x30>;
|
||||
|
||||
|
|
@ -60,7 +66,7 @@
|
|||
interrupts = <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -83,7 +89,7 @@
|
|||
"vice_0";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
upg_irq0_intc: interrupt-controller@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
|
|
@ -98,7 +104,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
|
||||
upg_aon_irq0_intc: interrupt-controller@409480 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x409480 0x8>;
|
||||
|
||||
|
|
@ -209,6 +215,59 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406580 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406580 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwmb: pwm@406800 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406800 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <49>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 21>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@4094c0 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x4094c0 0x40>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <18 4>;
|
||||
};
|
||||
|
||||
enet0: ethernet@b80000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -312,6 +371,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@41a000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x41a000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
|
||||
nand: nand@41b800 {
|
||||
compatible = "brcm,brcmnand-v5.0", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand";
|
||||
reg = <0x41b800 0x400>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@181000 {
|
||||
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
|
|
@ -351,5 +430,25 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0: sdhci@419000 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x419000 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <43>;
|
||||
sd-uhs-sdr50;
|
||||
mmc-hs200-1_8v;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci1: sdhci@419200 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x419200 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <44>;
|
||||
sd-uhs-sdr50;
|
||||
mmc-hs200-1_8v;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
uart0 = &uart0;
|
||||
};
|
||||
|
||||
cpu_intc: cpu_intc {
|
||||
cpu_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
|
|
@ -52,6 +52,12 @@
|
|||
#clock-cells = <0>;
|
||||
clock-frequency = <81000000>;
|
||||
};
|
||||
|
||||
upg_clk: upg_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
};
|
||||
|
||||
rdb {
|
||||
|
|
@ -61,7 +67,7 @@
|
|||
compatible = "simple-bus";
|
||||
ranges = <0 0x10000000 0x01000000>;
|
||||
|
||||
periph_intc: periph_intc@41b500 {
|
||||
periph_intc: interrupt-controller@41b500 {
|
||||
compatible = "brcm,bcm7038-l1-intc";
|
||||
reg = <0x41b500 0x40>, <0x41b600 0x40>,
|
||||
<0x41b700 0x40>, <0x41b800 0x40>;
|
||||
|
|
@ -73,7 +79,7 @@
|
|||
interrupts = <2>, <3>, <2>, <3>;
|
||||
};
|
||||
|
||||
sun_l2_intc: sun_l2_intc@403000 {
|
||||
sun_l2_intc: interrupt-controller@403000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x403000 0x30>;
|
||||
interrupt-controller;
|
||||
|
|
@ -98,7 +104,7 @@
|
|||
"scpu";
|
||||
};
|
||||
|
||||
upg_irq0_intc: upg_irq0_intc@406780 {
|
||||
upg_irq0_intc: interrupt-controller@406780 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x406780 0x8>;
|
||||
|
||||
|
|
@ -113,7 +119,7 @@
|
|||
interrupt-names = "upg_main", "upg_bsc";
|
||||
};
|
||||
|
||||
upg_aon_irq0_intc: upg_aon_irq0_intc@409480 {
|
||||
upg_aon_irq0_intc: interrupt-controller@409480 {
|
||||
compatible = "brcm,bcm7120-l2-intc";
|
||||
reg = <0x409480 0x8>;
|
||||
|
||||
|
|
@ -224,6 +230,59 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pwma: pwm@406580 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406580 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwmb: pwm@406800 {
|
||||
compatible = "brcm,bcm7038-pwm";
|
||||
reg = <0x406800 0x28>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&upg_clk>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aon_pm_l2_intc: interrupt-controller@408440 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x408440 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <54>;
|
||||
brcm,irq-can-wake;
|
||||
};
|
||||
|
||||
upg_gio: gpio@406700 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x406700 0x80>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
brcm,gpio-bank-widths = <32 32 32 21>;
|
||||
};
|
||||
|
||||
upg_gio_aon: gpio@4094c0 {
|
||||
compatible = "brcm,brcmstb-gpio";
|
||||
reg = <0x4094c0 0x40>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
interrupt-parent = <&upg_aon_irq0_intc>;
|
||||
interrupts = <6>;
|
||||
interrupts-extended = <&upg_aon_irq0_intc 6>,
|
||||
<&aon_pm_l2_intc 5>;
|
||||
wakeup-source;
|
||||
brcm,gpio-bank-widths = <18 4>;
|
||||
};
|
||||
|
||||
enet0: ethernet@b80000 {
|
||||
phy-mode = "internal";
|
||||
phy-handle = <&phy1>;
|
||||
|
|
@ -327,6 +386,26 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
hif_l2_intc: interrupt-controller@41b000 {
|
||||
compatible = "brcm,l2-intc";
|
||||
reg = <0x41b000 0x30>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <24>;
|
||||
};
|
||||
|
||||
nand: nand@41c800 {
|
||||
compatible = "brcm,brcmnand-v6.2", "brcm,brcmnand";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "nand", "flash-dma";
|
||||
reg = <0x41c800 0x600>, <0x41d000 0x100>;
|
||||
interrupt-parent = <&hif_l2_intc>;
|
||||
interrupts = <24>, <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata: sata@181000 {
|
||||
compatible = "brcm,bcm7425-ahci", "brcm,sata3-ahci";
|
||||
reg-names = "ahci", "top-ctrl";
|
||||
|
|
@ -366,5 +445,25 @@
|
|||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci0: sdhci@41a000 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x41a000 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <47>;
|
||||
sd-uhs-sdr50;
|
||||
mmc-hs200-1_8v;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci1: sdhci@41a200 {
|
||||
compatible = "brcm,bcm7425-sdhci";
|
||||
reg = <0x41a200 0x100>;
|
||||
interrupt-parent = <&periph_intc>;
|
||||
interrupts = <48>;
|
||||
sd-uhs-sdr50;
|
||||
mmc-hs200-1_8v;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: USB is wonky; disable it for now */
|
||||
&ehci0 {
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7346.dtsi"
|
||||
/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97346dbsmb", "brcm,bcm7346";
|
||||
|
|
@ -49,6 +50,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwmb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -85,6 +94,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -92,3 +105,7 @@
|
|||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7358.dtsi"
|
||||
/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97358svmb", "brcm,bcm7358";
|
||||
|
|
@ -45,6 +46,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwmb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -56,3 +65,7 @@
|
|||
&ohci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -45,6 +45,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -64,3 +68,7 @@
|
|||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7362.dtsi"
|
||||
/include/ "bcm97xxx-nand-cs1-bch4.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97362svmb", "brcm,bcm7362";
|
||||
|
|
@ -41,6 +42,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -53,6 +58,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -60,3 +69,7 @@
|
|||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -51,6 +51,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwmb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* FIXME: MAC driver comes up but cannot attach to PHY */
|
||||
&enet0 {
|
||||
status = "disabled";
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7425.dtsi"
|
||||
/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97425svmb", "brcm,bcm7425";
|
||||
|
|
@ -51,6 +52,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwmb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -86,3 +95,15 @@
|
|||
&ohci3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
/dts-v1/;
|
||||
|
||||
/include/ "bcm7435.dtsi"
|
||||
/include/ "bcm97xxx-nand-cs1-bch24.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm97435svmb", "brcm,bcm7435";
|
||||
|
|
@ -51,6 +52,14 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&pwma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pwmb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enet0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -87,6 +96,10 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&nand {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -94,3 +107,11 @@
|
|||
&sata_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
25
arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
Normal file
25
arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch24.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
&nand {
|
||||
nandcs@1 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <1>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
nand-ecc-strength = <24>;
|
||||
nand-ecc-step-size = <1024>;
|
||||
brcm,nand-oob-sector-size = <27>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash1.rootfs@0 {
|
||||
reg = <0x0 0x10000000>;
|
||||
};
|
||||
|
||||
flash1.kernel@10000000 {
|
||||
reg = <0x10000000 0x400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
25
arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
Normal file
25
arch/mips/boot/dts/brcm/bcm97xxx-nand-cs1-bch4.dtsi
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
&nand {
|
||||
nandcs@1 {
|
||||
compatible = "brcm,nandcs";
|
||||
reg = <1>;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
brcm,nand-oob-sector-size = <16>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash1.rootfs@0 {
|
||||
reg = <0x0 0x10000000>;
|
||||
};
|
||||
|
||||
flash1.kernel@10000000 {
|
||||
reg = <0x10000000 0x400000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -8,55 +8,16 @@
|
|||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "octeon_3xxx.dtsi"
|
||||
/include/ "dlink_dsr-500n-1000n.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "dlink,dsr-1000n";
|
||||
|
||||
soc@0 {
|
||||
smi0: mdio@1180000001800 {
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
|
||||
pip: pip@11800a0000000 {
|
||||
interface@0 {
|
||||
ethernet@0 {
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
ethernet@1 {
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
ethernet@2 {
|
||||
phy-handle = <&phy8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
twsi0: i2c@1180000001000 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0: serial@1180000000800 {
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
usbn: usbn@1180068000000 {
|
||||
refclk-frequency = <12000000>;
|
||||
refclk-type = "crystal";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
@ -87,8 +48,4 @@
|
|||
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
pip = &pip;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
58
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi
Normal file
58
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n-1000n.dtsi
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/*
|
||||
* Device tree source for D-Link DSR-500N/1000N (common parts).
|
||||
*
|
||||
* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "octeon_3xxx.dtsi"
|
||||
|
||||
/ {
|
||||
soc@0 {
|
||||
smi0: mdio@1180000001800 {
|
||||
phy8: ethernet-phy@8 {
|
||||
reg = <8>;
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
};
|
||||
};
|
||||
|
||||
pip: pip@11800a0000000 {
|
||||
interface@0 {
|
||||
ethernet@0 {
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
ethernet@1 {
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
ethernet@2 {
|
||||
phy-handle = <&phy8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
twsi0: i2c@1180000001000 {
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1337";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
usbn: usbn@1180068000000 {
|
||||
refclk-frequency = <12000000>;
|
||||
refclk-type = "crystal";
|
||||
};
|
||||
};
|
||||
|
||||
aliases {
|
||||
pip = &pip;
|
||||
};
|
||||
};
|
||||
40
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
Normal file
40
arch/mips/boot/dts/cavium-octeon/dlink_dsr-500n.dts
Normal file
|
|
@ -0,0 +1,40 @@
|
|||
/*
|
||||
* Device tree source for D-Link DSR-500N.
|
||||
*
|
||||
* Written by: Aaro Koskinen <aaro.koskinen@iki.fi>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/include/ "dlink_dsr-500n-1000n.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "dlink,dsr-500n";
|
||||
compatible = "dlink,dsr-500n", "cavium,octeon-3860";
|
||||
|
||||
soc@0 {
|
||||
uart0: serial@1180000000800 {
|
||||
clock-frequency = <300000000>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
usb {
|
||||
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wps {
|
||||
gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wireless {
|
||||
label = "2.4g";
|
||||
gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -1,5 +1,5 @@
|
|||
dtb-$(CONFIG_MIPS_MALTA) += malta.dtb
|
||||
dtb-$(CONFIG_MIPS_SEAD3) += sead3.dtb
|
||||
dtb-$(CONFIG_LEGACY_BOARD_SEAD3) += sead3.dtb
|
||||
|
||||
obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,8 @@
|
|||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
/memreserve/ 0x00000000 0x00001000; /* YAMON exception vectors */
|
||||
/memreserve/ 0x00001000 0x000ef000; /* YAMON */
|
||||
/memreserve/ 0x000f0000 0x00010000; /* PIIX4 ISA memory */
|
||||
|
|
@ -8,4 +11,100 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mti,malta";
|
||||
|
||||
cpu_intc: interrupt-controller {
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1bdc0000 {
|
||||
compatible = "mti,gic";
|
||||
reg = <0x1bdc0000 0x20000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
/*
|
||||
* Declare the interrupt-parent even though the mti,gic
|
||||
* binding doesn't require it, such that the kernel can
|
||||
* figure out that cpu_intc is the root interrupt
|
||||
* controller & should be probed first.
|
||||
*/
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
i8259: interrupt-controller@20 {
|
||||
compatible = "intel,i8259";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
flash@1e000000 {
|
||||
compatible = "intel,dt28f160", "cfi-flash";
|
||||
reg = <0x1e000000 0x400000>;
|
||||
bank-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
yamon@0 {
|
||||
label = "YAMON";
|
||||
reg = <0x0 0x100000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
user-fs@100000 {
|
||||
label = "User FS";
|
||||
reg = <0x100000 0x2e0000>;
|
||||
};
|
||||
|
||||
board-config@3e0000 {
|
||||
label = "Board Config";
|
||||
reg = <0x3e0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fpga_regs: system-controller@1f000000 {
|
||||
compatible = "mti,malta-fpga", "syscon", "simple-mfd";
|
||||
reg = <0x1f000000 0x1000>;
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&fpga_regs>;
|
||||
offset = <0x500>;
|
||||
mask = <0x4d>;
|
||||
};
|
||||
};
|
||||
|
||||
isa {
|
||||
compatible = "isa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <1 0 0 0x1000>;
|
||||
|
||||
rtc@70 {
|
||||
compatible = "motorola,mc146818";
|
||||
reg = <1 0x70 0x8>;
|
||||
|
||||
interrupt-parent = <&i8259>;
|
||||
interrupts = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,10 +4,23 @@
|
|||
/memreserve/ 0x00001000 0x000ef000; // ROM data
|
||||
/memreserve/ 0x000f0000 0x004cc000; // reserved
|
||||
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mti,sead-3";
|
||||
model = "MIPS SEAD-3";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
stdout-path = "uart1:115200";
|
||||
};
|
||||
|
||||
aliases {
|
||||
uart0 = &uart0;
|
||||
uart1 = &uart1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
|
|
@ -19,4 +32,229 @@
|
|||
device_type = "memory";
|
||||
reg = <0x0 0x08000000>;
|
||||
};
|
||||
|
||||
cpu_intc: interrupt-controller {
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@1b1c0000 {
|
||||
compatible = "mti,gic";
|
||||
reg = <0x1b1c0000 0x20000>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
|
||||
/*
|
||||
* Declare the interrupt-parent even though the mti,gic
|
||||
* binding doesn't require it, such that the kernel can
|
||||
* figure out that cpu_intc is the root interrupt
|
||||
* controller & should be probed first.
|
||||
*/
|
||||
interrupt-parent = <&cpu_intc>;
|
||||
|
||||
timer {
|
||||
compatible = "mti,gic-timer";
|
||||
interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
|
||||
};
|
||||
};
|
||||
|
||||
ehci@1b200000 {
|
||||
compatible = "generic-ehci";
|
||||
reg = <0x1b200000 0x1000>;
|
||||
|
||||
interrupts = <0>; /* GIC 0 or CPU 6 */
|
||||
|
||||
has-transaction-translator;
|
||||
};
|
||||
|
||||
flash@1c000000 {
|
||||
compatible = "intel,28f128j3", "cfi-flash";
|
||||
reg = <0x1c000000 0x2000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
bank-width = <4>;
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
user-fs@0 {
|
||||
label = "User FS";
|
||||
reg = <0x0 0x1fc0000>;
|
||||
};
|
||||
|
||||
board-config@3e0000 {
|
||||
label = "Board Config";
|
||||
reg = <0x1fc0000 0x40000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
fpga_regs: system-controller@1f000000 {
|
||||
compatible = "mti,sead3-fpga", "syscon", "simple-mfd";
|
||||
reg = <0x1f000000 0x200>;
|
||||
|
||||
reboot {
|
||||
compatible = "syscon-reboot";
|
||||
regmap = <&fpga_regs>;
|
||||
offset = <0x50>;
|
||||
mask = <0x4d>;
|
||||
};
|
||||
|
||||
poweroff {
|
||||
compatible = "restart-poweroff";
|
||||
};
|
||||
};
|
||||
|
||||
system-controller@1f000200 {
|
||||
compatible = "mti,sead3-cpld", "syscon", "simple-mfd";
|
||||
reg = <0x1f000200 0x300>;
|
||||
|
||||
led@10.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x1>;
|
||||
label = "pled0";
|
||||
};
|
||||
led@10.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x2>;
|
||||
label = "pled1";
|
||||
};
|
||||
led@10.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x4>;
|
||||
label = "pled2";
|
||||
};
|
||||
led@10.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x8>;
|
||||
label = "pled3";
|
||||
};
|
||||
led@10.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x10>;
|
||||
label = "pled4";
|
||||
};
|
||||
led@10.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x20>;
|
||||
label = "pled5";
|
||||
};
|
||||
led@10.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x40>;
|
||||
label = "pled6";
|
||||
};
|
||||
led@10.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x10>;
|
||||
mask = <0x80>;
|
||||
label = "pled7";
|
||||
};
|
||||
|
||||
led@18.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x1>;
|
||||
label = "fled0";
|
||||
};
|
||||
led@18.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x2>;
|
||||
label = "fled1";
|
||||
};
|
||||
led@18.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x4>;
|
||||
label = "fled2";
|
||||
};
|
||||
led@18.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x8>;
|
||||
label = "fled3";
|
||||
};
|
||||
led@18.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x10>;
|
||||
label = "fled4";
|
||||
};
|
||||
led@18.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x20>;
|
||||
label = "fled5";
|
||||
};
|
||||
led@18.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x40>;
|
||||
label = "fled6";
|
||||
};
|
||||
led@18.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x18>;
|
||||
mask = <0x80>;
|
||||
label = "fled7";
|
||||
};
|
||||
|
||||
lcd@200 {
|
||||
compatible = "mti,sead3-lcd";
|
||||
offset = <0x200>;
|
||||
};
|
||||
};
|
||||
|
||||
/* UART connected to FTDI & miniUSB socket */
|
||||
uart0: uart@1f000900 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1f000900 0x20>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
clock-frequency = <14745600>;
|
||||
|
||||
interrupts = <3>; /* GIC 3 or CPU 4 */
|
||||
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
/* UART connected to RS232 socket */
|
||||
uart1: uart@1f000800 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0x1f000800 0x20>;
|
||||
reg-io-width = <4>;
|
||||
reg-shift = <2>;
|
||||
|
||||
clock-frequency = <14745600>;
|
||||
|
||||
interrupts = <2>; /* GIC 2 or CPU 4 */
|
||||
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
eth@1f010000 {
|
||||
compatible = "smsc,lan9115";
|
||||
reg = <0x1f010000 0x10000>;
|
||||
reg-io-width = <4>;
|
||||
|
||||
interrupts = <0>; /* GIC 0 or CPU 6 */
|
||||
|
||||
phy-mode = "mii";
|
||||
smsc,irq-push-pull;
|
||||
smsc,save-mac-address;
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -36,8 +36,6 @@
|
|||
|
||||
#include <asm/octeon/cvmx-config.h>
|
||||
|
||||
#include <asm/octeon/cvmx-mdio.h>
|
||||
|
||||
#include <asm/octeon/cvmx-helper.h>
|
||||
#include <asm/octeon/cvmx-helper-util.h>
|
||||
#include <asm/octeon/cvmx-helper-board.h>
|
||||
|
|
@ -45,17 +43,6 @@
|
|||
#include <asm/octeon/cvmx-gmxx-defs.h>
|
||||
#include <asm/octeon/cvmx-asxx-defs.h>
|
||||
|
||||
/**
|
||||
* cvmx_override_board_link_get(int ipd_port) is a function
|
||||
* pointer. It is meant to allow customization of the process of
|
||||
* talking to a PHY to determine link speed. It is called every
|
||||
* time a PHY must be polled for link status. Users should set
|
||||
* this pointer to a function before calling any cvmx-helper
|
||||
* operations.
|
||||
*/
|
||||
cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) =
|
||||
NULL;
|
||||
|
||||
/**
|
||||
* Return the MII PHY address associated with the given IPD
|
||||
* port. A result of -1 means there isn't a MII capable PHY
|
||||
|
|
@ -222,12 +209,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
|
|||
cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
|
||||
{
|
||||
cvmx_helper_link_info_t result;
|
||||
int phy_addr;
|
||||
int is_broadcom_phy = 0;
|
||||
|
||||
/* Give the user a chance to override the processing of this function */
|
||||
if (cvmx_override_board_link_get)
|
||||
return cvmx_override_board_link_get(ipd_port);
|
||||
|
||||
/* Unless we fix it later, all links are defaulted to down */
|
||||
result.u64 = 0;
|
||||
|
|
@ -263,8 +244,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
|
|||
result.s.full_duplex = 1;
|
||||
result.s.speed = 1000;
|
||||
return result;
|
||||
} else /* The other port uses a broadcom PHY */
|
||||
is_broadcom_phy = 1;
|
||||
}
|
||||
break;
|
||||
case CVMX_BOARD_TYPE_BBGW_REF:
|
||||
/* Port 1 on these boards is always Gigabit */
|
||||
|
|
@ -282,108 +262,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
|
|||
break;
|
||||
}
|
||||
|
||||
phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
|
||||
if (phy_addr != -1) {
|
||||
if (is_broadcom_phy) {
|
||||
/*
|
||||
* Below we are going to read SMI/MDIO
|
||||
* register 0x19 which works on Broadcom
|
||||
* parts
|
||||
*/
|
||||
int phy_status =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
0x19);
|
||||
switch ((phy_status >> 8) & 0x7) {
|
||||
case 0:
|
||||
result.u64 = 0;
|
||||
break;
|
||||
case 1:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 0;
|
||||
result.s.speed = 10;
|
||||
break;
|
||||
case 2:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 1;
|
||||
result.s.speed = 10;
|
||||
break;
|
||||
case 3:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 0;
|
||||
result.s.speed = 100;
|
||||
break;
|
||||
case 4:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 1;
|
||||
result.s.speed = 100;
|
||||
break;
|
||||
case 5:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 1;
|
||||
result.s.speed = 100;
|
||||
break;
|
||||
case 6:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 0;
|
||||
result.s.speed = 1000;
|
||||
break;
|
||||
case 7:
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = 1;
|
||||
result.s.speed = 1000;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* This code assumes we are using a Marvell
|
||||
* Gigabit PHY. All the speed information can
|
||||
* be read from register 17 in one
|
||||
* go. Somebody using a different PHY will
|
||||
* need to handle it above in the board
|
||||
* specific area.
|
||||
*/
|
||||
int phy_status =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
|
||||
|
||||
/*
|
||||
* If the resolve bit 11 isn't set, see if
|
||||
* autoneg is turned off (bit 12, reg 0). The
|
||||
* resolve bit doesn't get set properly when
|
||||
* autoneg is off, so force it.
|
||||
*/
|
||||
if ((phy_status & (1 << 11)) == 0) {
|
||||
int auto_status =
|
||||
cvmx_mdio_read(phy_addr >> 8,
|
||||
phy_addr & 0xff, 0);
|
||||
if ((auto_status & (1 << 12)) == 0)
|
||||
phy_status |= 1 << 11;
|
||||
}
|
||||
|
||||
/*
|
||||
* Only return a link if the PHY has finished
|
||||
* auto negotiation and set the resolved bit
|
||||
* (bit 11)
|
||||
*/
|
||||
if (phy_status & (1 << 11)) {
|
||||
result.s.link_up = 1;
|
||||
result.s.full_duplex = ((phy_status >> 13) & 1);
|
||||
switch ((phy_status >> 14) & 3) {
|
||||
case 0: /* 10 Mbps */
|
||||
result.s.speed = 10;
|
||||
break;
|
||||
case 1: /* 100 Mbps */
|
||||
result.s.speed = 100;
|
||||
break;
|
||||
case 2: /* 1 Gbps */
|
||||
result.s.speed = 1000;
|
||||
break;
|
||||
case 3: /* Illegal */
|
||||
result.u64 = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
|
||||
if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
|
||||
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|
||||
|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
|
||||
/*
|
||||
|
|
@ -432,176 +311,6 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
|
|||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function as a board specific method of changing the PHY
|
||||
* speed, duplex, and auto-negotiation. This programs the PHY and
|
||||
* not Octeon. This can be used to force Octeon's links to
|
||||
* specific settings.
|
||||
*
|
||||
* @phy_addr: The address of the PHY to program
|
||||
* @enable_autoneg:
|
||||
* Non zero if you want to enable auto-negotiation.
|
||||
* @link_info: Link speed to program. If the speed is zero and auto-negotiation
|
||||
* is enabled, all possible negotiation speeds are advertised.
|
||||
*
|
||||
* Returns Zero on success, negative on failure
|
||||
*/
|
||||
int cvmx_helper_board_link_set_phy(int phy_addr,
|
||||
cvmx_helper_board_set_phy_link_flags_types_t
|
||||
link_flags,
|
||||
cvmx_helper_link_info_t link_info)
|
||||
{
|
||||
|
||||
/* Set the flow control settings based on link_flags */
|
||||
if ((link_flags & set_phy_link_flags_flow_control_mask) !=
|
||||
set_phy_link_flags_flow_control_dont_touch) {
|
||||
cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
|
||||
reg_autoneg_adver.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
|
||||
reg_autoneg_adver.s.asymmetric_pause =
|
||||
(link_flags & set_phy_link_flags_flow_control_mask) ==
|
||||
set_phy_link_flags_flow_control_enable;
|
||||
reg_autoneg_adver.s.pause =
|
||||
(link_flags & set_phy_link_flags_flow_control_mask) ==
|
||||
set_phy_link_flags_flow_control_enable;
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
|
||||
reg_autoneg_adver.u16);
|
||||
}
|
||||
|
||||
/* If speed isn't set and autoneg is on advertise all supported modes */
|
||||
if ((link_flags & set_phy_link_flags_autoneg)
|
||||
&& (link_info.s.speed == 0)) {
|
||||
cvmx_mdio_phy_reg_control_t reg_control;
|
||||
cvmx_mdio_phy_reg_status_t reg_status;
|
||||
cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
|
||||
cvmx_mdio_phy_reg_extended_status_t reg_extended_status;
|
||||
cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
|
||||
|
||||
reg_status.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_STATUS);
|
||||
reg_autoneg_adver.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
|
||||
reg_autoneg_adver.s.advert_100base_t4 =
|
||||
reg_status.s.capable_100base_t4;
|
||||
reg_autoneg_adver.s.advert_10base_tx_full =
|
||||
reg_status.s.capable_10_full;
|
||||
reg_autoneg_adver.s.advert_10base_tx_half =
|
||||
reg_status.s.capable_10_half;
|
||||
reg_autoneg_adver.s.advert_100base_tx_full =
|
||||
reg_status.s.capable_100base_x_full;
|
||||
reg_autoneg_adver.s.advert_100base_tx_half =
|
||||
reg_status.s.capable_100base_x_half;
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
|
||||
reg_autoneg_adver.u16);
|
||||
if (reg_status.s.capable_extended_status) {
|
||||
reg_extended_status.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_EXTENDED_STATUS);
|
||||
reg_control_1000.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL_1000);
|
||||
reg_control_1000.s.advert_1000base_t_full =
|
||||
reg_extended_status.s.capable_1000base_t_full;
|
||||
reg_control_1000.s.advert_1000base_t_half =
|
||||
reg_extended_status.s.capable_1000base_t_half;
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL_1000,
|
||||
reg_control_1000.u16);
|
||||
}
|
||||
reg_control.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL);
|
||||
reg_control.s.autoneg_enable = 1;
|
||||
reg_control.s.restart_autoneg = 1;
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
||||
} else if ((link_flags & set_phy_link_flags_autoneg)) {
|
||||
cvmx_mdio_phy_reg_control_t reg_control;
|
||||
cvmx_mdio_phy_reg_status_t reg_status;
|
||||
cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver;
|
||||
cvmx_mdio_phy_reg_control_1000_t reg_control_1000;
|
||||
|
||||
reg_status.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_STATUS);
|
||||
reg_autoneg_adver.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER);
|
||||
reg_autoneg_adver.s.advert_100base_t4 = 0;
|
||||
reg_autoneg_adver.s.advert_10base_tx_full = 0;
|
||||
reg_autoneg_adver.s.advert_10base_tx_half = 0;
|
||||
reg_autoneg_adver.s.advert_100base_tx_full = 0;
|
||||
reg_autoneg_adver.s.advert_100base_tx_half = 0;
|
||||
if (reg_status.s.capable_extended_status) {
|
||||
reg_control_1000.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL_1000);
|
||||
reg_control_1000.s.advert_1000base_t_full = 0;
|
||||
reg_control_1000.s.advert_1000base_t_half = 0;
|
||||
}
|
||||
switch (link_info.s.speed) {
|
||||
case 10:
|
||||
reg_autoneg_adver.s.advert_10base_tx_full =
|
||||
link_info.s.full_duplex;
|
||||
reg_autoneg_adver.s.advert_10base_tx_half =
|
||||
!link_info.s.full_duplex;
|
||||
break;
|
||||
case 100:
|
||||
reg_autoneg_adver.s.advert_100base_tx_full =
|
||||
link_info.s.full_duplex;
|
||||
reg_autoneg_adver.s.advert_100base_tx_half =
|
||||
!link_info.s.full_duplex;
|
||||
break;
|
||||
case 1000:
|
||||
reg_control_1000.s.advert_1000base_t_full =
|
||||
link_info.s.full_duplex;
|
||||
reg_control_1000.s.advert_1000base_t_half =
|
||||
!link_info.s.full_duplex;
|
||||
break;
|
||||
}
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_AUTONEG_ADVER,
|
||||
reg_autoneg_adver.u16);
|
||||
if (reg_status.s.capable_extended_status)
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL_1000,
|
||||
reg_control_1000.u16);
|
||||
reg_control.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL);
|
||||
reg_control.s.autoneg_enable = 1;
|
||||
reg_control.s.restart_autoneg = 1;
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
||||
} else {
|
||||
cvmx_mdio_phy_reg_control_t reg_control;
|
||||
reg_control.u16 =
|
||||
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL);
|
||||
reg_control.s.autoneg_enable = 0;
|
||||
reg_control.s.restart_autoneg = 1;
|
||||
reg_control.s.duplex = link_info.s.full_duplex;
|
||||
if (link_info.s.speed == 1000) {
|
||||
reg_control.s.speed_msb = 1;
|
||||
reg_control.s.speed_lsb = 0;
|
||||
} else if (link_info.s.speed == 100) {
|
||||
reg_control.s.speed_msb = 0;
|
||||
reg_control.s.speed_lsb = 1;
|
||||
} else if (link_info.s.speed == 10) {
|
||||
reg_control.s.speed_msb = 0;
|
||||
reg_control.s.speed_lsb = 0;
|
||||
}
|
||||
cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff,
|
||||
CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* This function is called by cvmx_helper_interface_probe() after it
|
||||
* determines the number of ports Octeon can support on a specific
|
||||
|
|
@ -675,48 +384,6 @@ int __cvmx_helper_board_hardware_enable(int interface)
|
|||
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface),
|
||||
0xc);
|
||||
}
|
||||
} else if (cvmx_sysinfo_get()->board_type ==
|
||||
CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
|
||||
/*
|
||||
* Broadcom PHYs require differnet ASX
|
||||
* clocks. Unfortunately many boards don't define a
|
||||
* new board Id and simply mangle the
|
||||
* CN3010_EVB_HS5
|
||||
*/
|
||||
if (interface == 0) {
|
||||
/*
|
||||
* Some boards use a hacked up bootloader that
|
||||
* identifies them as CN3010_EVB_HS5
|
||||
* evaluation boards. This leads to all kinds
|
||||
* of configuration problems. Detect one
|
||||
* case, and print warning, while trying to do
|
||||
* the right thing.
|
||||
*/
|
||||
int phy_addr = cvmx_helper_board_get_mii_address(0);
|
||||
if (phy_addr != -1) {
|
||||
int phy_identifier =
|
||||
cvmx_mdio_read(phy_addr >> 8,
|
||||
phy_addr & 0xff, 0x2);
|
||||
/* Is it a Broadcom PHY? */
|
||||
if (phy_identifier == 0x0143) {
|
||||
cvmx_dprintf("\n");
|
||||
cvmx_dprintf("ERROR:\n");
|
||||
cvmx_dprintf
|
||||
("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n");
|
||||
cvmx_dprintf
|
||||
("ERROR: The board type is mis-configured, and software malfunctions are likely.\n");
|
||||
cvmx_dprintf
|
||||
("ERROR: All boards require a unique board type to identify them.\n");
|
||||
cvmx_dprintf("ERROR:\n");
|
||||
cvmx_dprintf("\n");
|
||||
cvmx_wait(1000000000);
|
||||
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX
|
||||
(0, interface), 5);
|
||||
cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX
|
||||
(0, interface), 5);
|
||||
}
|
||||
}
|
||||
}
|
||||
} else if (cvmx_sysinfo_get()->board_type ==
|
||||
CVMX_BOARD_TYPE_UBNT_E100) {
|
||||
cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), 0);
|
||||
|
|
|
|||
|
|
@ -33,8 +33,6 @@
|
|||
|
||||
#include <asm/octeon/cvmx-config.h>
|
||||
|
||||
|
||||
#include <asm/octeon/cvmx-mdio.h>
|
||||
#include <asm/octeon/cvmx-pko.h>
|
||||
#include <asm/octeon/cvmx-helper.h>
|
||||
#include <asm/octeon/cvmx-helper-board.h>
|
||||
|
|
@ -243,8 +241,7 @@ int __cvmx_helper_rgmii_enable(int interface)
|
|||
/* enable the ports now */
|
||||
for (port = 0; port < num_ports; port++) {
|
||||
union cvmx_gmxx_prtx_cfg gmx_cfg;
|
||||
cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port
|
||||
(interface, port));
|
||||
|
||||
gmx_cfg.u64 =
|
||||
cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
|
||||
gmx_cfg.s.en = 1;
|
||||
|
|
|
|||
|
|
@ -34,7 +34,6 @@
|
|||
|
||||
#include <asm/octeon/cvmx-config.h>
|
||||
|
||||
#include <asm/octeon/cvmx-mdio.h>
|
||||
#include <asm/octeon/cvmx-helper.h>
|
||||
#include <asm/octeon/cvmx-helper-board.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -234,8 +234,6 @@ int __cvmx_helper_xaui_enable(int interface)
|
|||
cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64);
|
||||
cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64);
|
||||
|
||||
cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0));
|
||||
|
||||
/* (8) Enable packet reception */
|
||||
xauiMiscCtl.s.gmxeno = 0;
|
||||
cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64);
|
||||
|
|
|
|||
|
|
@ -841,7 +841,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
|
|||
int retry_cnt;
|
||||
int retry_loop_cnt;
|
||||
int i;
|
||||
cvmx_helper_link_info_t link_info;
|
||||
|
||||
/* Save values for restore at end */
|
||||
uint64_t prtx_cfg =
|
||||
|
|
@ -1002,15 +1001,6 @@ int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
|
|||
(INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
|
||||
frame_max);
|
||||
cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
|
||||
/* Set link to down so autonegotiation will set it up again */
|
||||
link_info.u64 = 0;
|
||||
cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
|
||||
|
||||
/*
|
||||
* Bring the link back up as autonegotiation is not done in
|
||||
* user applications.
|
||||
*/
|
||||
cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
|
||||
|
||||
CVMX_SYNC;
|
||||
if (num_segs)
|
||||
|
|
|
|||
|
|
@ -65,7 +65,8 @@ EXPORT_SYMBOL(octeon_should_swizzle_table);
|
|||
extern void pci_console_init(const char *arg);
|
||||
#endif
|
||||
|
||||
static unsigned long long MAX_MEMORY = 512ull << 20;
|
||||
static unsigned long long max_memory = ULLONG_MAX;
|
||||
static unsigned long long reserve_low_mem;
|
||||
|
||||
DEFINE_SEMAPHORE(octeon_bootbus_sem);
|
||||
EXPORT_SYMBOL(octeon_bootbus_sem);
|
||||
|
|
@ -75,7 +76,6 @@ struct octeon_boot_descriptor *octeon_boot_desc_ptr;
|
|||
struct cvmx_bootinfo *octeon_bootinfo;
|
||||
EXPORT_SYMBOL(octeon_bootinfo);
|
||||
|
||||
static unsigned long long RESERVE_LOW_MEM = 0ull;
|
||||
#ifdef CONFIG_KEXEC
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
|
|
@ -125,18 +125,18 @@ static void kexec_bootmem_init(uint64_t mem_size, uint32_t low_reserved_bytes)
|
|||
bootmem_desc->major_version = CVMX_BOOTMEM_DESC_MAJ_VER;
|
||||
bootmem_desc->minor_version = CVMX_BOOTMEM_DESC_MIN_VER;
|
||||
|
||||
addr = (OCTEON_DDR0_BASE + RESERVE_LOW_MEM + low_reserved_bytes);
|
||||
addr = (OCTEON_DDR0_BASE + reserve_low_mem + low_reserved_bytes);
|
||||
bootmem_desc->head_addr = 0;
|
||||
|
||||
if (mem_size <= OCTEON_DDR0_SIZE) {
|
||||
__cvmx_bootmem_phy_free(addr,
|
||||
mem_size - RESERVE_LOW_MEM -
|
||||
mem_size - reserve_low_mem -
|
||||
low_reserved_bytes, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
__cvmx_bootmem_phy_free(addr,
|
||||
OCTEON_DDR0_SIZE - RESERVE_LOW_MEM -
|
||||
OCTEON_DDR0_SIZE - reserve_low_mem -
|
||||
low_reserved_bytes, 0);
|
||||
|
||||
mem_size -= OCTEON_DDR0_SIZE;
|
||||
|
|
@ -857,15 +857,15 @@ void __init prom_init(void)
|
|||
|
||||
/* Default to 64MB in the simulator to speed things up */
|
||||
if (octeon_is_simulation())
|
||||
MAX_MEMORY = 64ull << 20;
|
||||
max_memory = 64ull << 20;
|
||||
|
||||
arg = strstr(arcs_cmdline, "mem=");
|
||||
if (arg) {
|
||||
MAX_MEMORY = memparse(arg + 4, &p);
|
||||
if (MAX_MEMORY == 0)
|
||||
MAX_MEMORY = 32ull << 30;
|
||||
max_memory = memparse(arg + 4, &p);
|
||||
if (max_memory == 0)
|
||||
max_memory = 32ull << 30;
|
||||
if (*p == '@')
|
||||
RESERVE_LOW_MEM = memparse(p + 1, &p);
|
||||
reserve_low_mem = memparse(p + 1, &p);
|
||||
}
|
||||
|
||||
arcs_cmdline[0] = 0;
|
||||
|
|
@ -875,11 +875,11 @@ void __init prom_init(void)
|
|||
cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
|
||||
if ((strncmp(arg, "MEM=", 4) == 0) ||
|
||||
(strncmp(arg, "mem=", 4) == 0)) {
|
||||
MAX_MEMORY = memparse(arg + 4, &p);
|
||||
if (MAX_MEMORY == 0)
|
||||
MAX_MEMORY = 32ull << 30;
|
||||
max_memory = memparse(arg + 4, &p);
|
||||
if (max_memory == 0)
|
||||
max_memory = 32ull << 30;
|
||||
if (*p == '@')
|
||||
RESERVE_LOW_MEM = memparse(p + 1, &p);
|
||||
reserve_low_mem = memparse(p + 1, &p);
|
||||
#ifdef CONFIG_KEXEC
|
||||
} else if (strncmp(arg, "crashkernel=", 12) == 0) {
|
||||
crashk_size = memparse(arg+12, &p);
|
||||
|
|
@ -971,13 +971,13 @@ void __init plat_mem_setup(void)
|
|||
* to consistently work.
|
||||
*/
|
||||
mem_alloc_size = 4 << 20;
|
||||
if (mem_alloc_size > MAX_MEMORY)
|
||||
mem_alloc_size = MAX_MEMORY;
|
||||
if (mem_alloc_size > max_memory)
|
||||
mem_alloc_size = max_memory;
|
||||
|
||||
/* Crashkernel ignores bootmem list. It relies on mem=X@Y option */
|
||||
#ifdef CONFIG_CRASH_DUMP
|
||||
add_memory_region(RESERVE_LOW_MEM, MAX_MEMORY, BOOT_MEM_RAM);
|
||||
total += MAX_MEMORY;
|
||||
add_memory_region(reserve_low_mem, max_memory, BOOT_MEM_RAM);
|
||||
total += max_memory;
|
||||
#else
|
||||
#ifdef CONFIG_KEXEC
|
||||
if (crashk_size > 0) {
|
||||
|
|
@ -992,7 +992,7 @@ void __init plat_mem_setup(void)
|
|||
*/
|
||||
cvmx_bootmem_lock();
|
||||
while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
|
||||
&& (total < MAX_MEMORY)) {
|
||||
&& (total < max_memory)) {
|
||||
memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
|
||||
__pa_symbol(&_end), -1,
|
||||
0x100000,
|
||||
|
|
|
|||
2
arch/mips/configs/generic/32r1.config
Normal file
2
arch/mips/configs/generic/32r1.config
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
CONFIG_CPU_MIPS32_R1=y
|
||||
CONFIG_HIGHMEM=y
|
||||
3
arch/mips/configs/generic/32r2.config
Normal file
3
arch/mips/configs/generic/32r2.config
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
CONFIG_HIGHMEM=y
|
||||
2
arch/mips/configs/generic/32r6.config
Normal file
2
arch/mips/configs/generic/32r6.config
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
CONFIG_CPU_MIPS32_R6=y
|
||||
CONFIG_HIGHMEM=y
|
||||
4
arch/mips/configs/generic/64r1.config
Normal file
4
arch/mips/configs/generic/64r1.config
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_CPU_MIPS64_R1=y
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
5
arch/mips/configs/generic/64r2.config
Normal file
5
arch/mips/configs/generic/64r2.config
Normal file
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_CPU_MIPS64_R2=y
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
4
arch/mips/configs/generic/64r6.config
Normal file
4
arch/mips/configs/generic/64r6.config
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_CPU_MIPS64_R6=y
|
||||
CONFIG_64BIT=y
|
||||
CONFIG_MIPS32_O32=y
|
||||
CONFIG_MIPS32_N32=y
|
||||
32
arch/mips/configs/generic/board-sead-3.config
Normal file
32
arch/mips/configs/generic/board-sead-3.config
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
CONFIG_LEGACY_BOARD_SEAD3=y
|
||||
|
||||
CONFIG_AUXDISPLAY=y
|
||||
CONFIG_IMG_ASCII_LCD=y
|
||||
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_SPI=y
|
||||
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMSC911X=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
1
arch/mips/configs/generic/eb.config
Normal file
1
arch/mips/configs/generic/eb.config
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_CPU_BIG_ENDIAN=y
|
||||
1
arch/mips/configs/generic/el.config
Normal file
1
arch/mips/configs/generic/el.config
Normal file
|
|
@ -0,0 +1 @@
|
|||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
4
arch/mips/configs/generic/micro32r2.config
Normal file
4
arch/mips/configs/generic/micro32r2.config
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MICROMIPS=y
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
CONFIG_HIGHMEM=y
|
||||
96
arch/mips/configs/generic_defconfig
Normal file
96
arch/mips/configs/generic_defconfig
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
CONFIG_MIPS_GENERIC=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_MIPS_CPS=y
|
||||
CONFIG_CPU_HAS_MSA=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_MIPS_O32_FP64_SUPPORT=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ_IDLE=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_MEMCG=y
|
||||
CONFIG_MEMCG_SWAP=y
|
||||
CONFIG_BLK_CGROUP=y
|
||||
CONFIG_CFS_BANDWIDTH=y
|
||||
CONFIG_RT_GROUP_SCHED=y
|
||||
CONFIG_CGROUP_PIDS=y
|
||||
CONFIG_CGROUP_FREEZER=y
|
||||
CONFIG_CPUSETS=y
|
||||
CONFIG_CGROUP_DEVICE=y
|
||||
CONFIG_CGROUP_CPUACCT=y
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_USER_NS=y
|
||||
CONFIG_SCHED_AUTOGROUP=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_BPF_SYSCALL=y
|
||||
CONFIG_USERFAULTFD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_SLUB_DEBUG is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_CC_STACKPROTECTOR_REGULAR=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_TRIM_UNUSED_KSYMS=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_NETFILTER=y
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_HW_RANDOM=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_MFD_SYSCON=y
|
||||
CONFIG_HID_A4TECH=y
|
||||
CONFIG_HID_APPLE=y
|
||||
CONFIG_HID_BELKIN=y
|
||||
CONFIG_HID_CHERRY=y
|
||||
CONFIG_HID_CHICONY=y
|
||||
CONFIG_HID_CYPRESS=y
|
||||
CONFIG_HID_EZKEY=y
|
||||
CONFIG_HID_KENSINGTON=y
|
||||
CONFIG_HID_LOGITECH=y
|
||||
CONFIG_HID_MICROSOFT=y
|
||||
CONFIG_HID_MONTEREY=y
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
# CONFIG_MIPS_PLATFORM_DEVICES is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT4_FS=y
|
||||
CONFIG_EXT4_FS_POSIX_ACL=y
|
||||
CONFIG_EXT4_FS_SECURITY=y
|
||||
CONFIG_EXT4_ENCRYPTION=y
|
||||
CONFIG_FANOTIFY=y
|
||||
CONFIG_FUSE_FS=y
|
||||
CONFIG_CUSE=y
|
||||
CONFIG_OVERLAY_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3_ACL=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_NFS_V4_1=y
|
||||
CONFIG_NFS_V4_2=y
|
||||
CONFIG_PRINTK_TIME=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_DEBUG_INFO_REDUCED=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE="earlycon"
|
||||
# CONFIG_XZ_DEC_X86 is not set
|
||||
# CONFIG_XZ_DEC_POWERPC is not set
|
||||
# CONFIG_XZ_DEC_IA64 is not set
|
||||
# CONFIG_XZ_DEC_ARM is not set
|
||||
# CONFIG_XZ_DEC_ARMTHUMB is not set
|
||||
# CONFIG_XZ_DEC_SPARC is not set
|
||||
126
arch/mips/configs/loongson1c_defconfig
Normal file
126
arch/mips/configs/loongson1c_defconfig
Normal file
|
|
@ -0,0 +1,126 @@
|
|||
CONFIG_MACH_LOONGSON32=y
|
||||
CONFIG_LOONGSON1_LS1C=y
|
||||
CONFIG_PREEMPT=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_LOCALVERSION_AUTO is not set
|
||||
CONFIG_KERNEL_XZ=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_BSD_PROCESS_ACCT_V3=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_NAMESPACES=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_PERF_EVENTS=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_LBDAF is not set
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_SYN_COOKIES=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_LOONGSON1=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_SCSI=m
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=m
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
# CONFIG_NET_VENDOR_BROADCOM is not set
|
||||
# CONFIG_NET_VENDOR_INTEL is not set
|
||||
# CONFIG_NET_VENDOR_MARVELL is not set
|
||||
# CONFIG_NET_VENDOR_MICREL is not set
|
||||
# CONFIG_NET_VENDOR_NATSEMI is not set
|
||||
# CONFIG_NET_VENDOR_SEEQ is not set
|
||||
# CONFIG_NET_VENDOR_SMSC is not set
|
||||
CONFIG_STMMAC_ETH=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=8
|
||||
# CONFIG_DEVKMEM is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_GPIOLIB=y
|
||||
CONFIG_GPIO_LOONGSON1=y
|
||||
# CONFIG_HWMON is not set
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_HID_GENERIC=m
|
||||
CONFIG_USB_HID=m
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
# CONFIG_USB_EHCI_TT_NEWSCHED is not set
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=m
|
||||
CONFIG_USB_SERIAL=m
|
||||
CONFIG_USB_SERIAL_PL2303=m
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_LOONGSON1=y
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT2_FS_XATTR=y
|
||||
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||
CONFIG_EXT2_FS_SECURITY=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_EXT3_FS_POSIX_ACL=y
|
||||
CONFIG_EXT3_FS_SECURITY=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_TMPFS_POSIX_ACL=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
|
||||
CONFIG_UBIFS_ATIME_SUPPORT=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=m
|
||||
CONFIG_NLS_ISO8859_1=m
|
||||
CONFIG_DYNAMIC_DEBUG=y
|
||||
# CONFIG_ENABLE_WARN_DEPRECATED is not set
|
||||
# CONFIG_ENABLE_MUST_CHECK is not set
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
# CONFIG_FTRACE is not set
|
||||
# CONFIG_EARLY_PRINTK is not set
|
||||
# CONFIG_CRYPTO_ECHAINIV is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -230,7 +230,7 @@ CONFIG_MTD_CFI=y
|
|||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UBI=m
|
||||
CONFIG_MTD_UBI_GLUEBI=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
|
|
@ -318,6 +318,8 @@ CONFIG_LIBERTAS=m
|
|||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CIRRUS=y
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ CONFIG_MTD_CFI=y
|
|||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UBI=m
|
||||
CONFIG_MTD_UBI_GLUEBI=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
|
|
@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
|
|||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CIRRUS=y
|
||||
|
|
|
|||
|
|
@ -234,7 +234,7 @@ CONFIG_MTD_CFI=y
|
|||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UBI=m
|
||||
CONFIG_MTD_UBI_GLUEBI=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
|
|
@ -331,6 +331,8 @@ CONFIG_LIBERTAS=m
|
|||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CIRRUS=y
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=4
|
|||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
|
|
|
|||
|
|
@ -132,6 +132,8 @@ CONFIG_LEGACY_PTY_COUNT=16
|
|||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=m
|
||||
CONFIG_FB=y
|
||||
|
|
|
|||
|
|
@ -134,6 +134,8 @@ CONFIG_LEGACY_PTY_COUNT=4
|
|||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FIRMWARE_EDID=y
|
||||
|
|
|
|||
|
|
@ -137,6 +137,8 @@ CONFIG_LEGACY_PTY_COUNT=4
|
|||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=m
|
||||
CONFIG_FB=y
|
||||
|
|
|
|||
|
|
@ -131,6 +131,8 @@ CONFIG_LEGACY_PTY_COUNT=16
|
|||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_HW_RANDOM=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=m
|
||||
CONFIG_FB=y
|
||||
|
|
|
|||
|
|
@ -231,7 +231,7 @@ CONFIG_MTD_CFI=y
|
|||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_CFI_STAA=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_UBI=m
|
||||
CONFIG_MTD_UBI_GLUEBI=m
|
||||
CONFIG_BLK_DEV_FD=m
|
||||
|
|
@ -326,6 +326,8 @@ CONFIG_LIBERTAS=m
|
|||
# CONFIG_SERIO_I8042 is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_POWER_RESET=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_CIRRUS=y
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
|||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_CC_STACKPROTECTOR_STRONG=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
|
|
@ -264,7 +263,6 @@ CONFIG_DMADEVICES=y
|
|||
CONFIG_IMG_MDC_DMA=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_ASHMEM=y
|
||||
# CONFIG_ANDROID_TIMED_OUTPUT is not set
|
||||
# CONFIG_IOMMU_SUPPORT is not set
|
||||
CONFIG_MEMORY=y
|
||||
CONFIG_IIO=y
|
||||
|
|
|
|||
|
|
@ -1,121 +0,0 @@
|
|||
CONFIG_MIPS_SEAD3=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_QSEMI_PHY=y
|
||||
CONFIG_LXT_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_CONSOLE_TRANSLATIONS is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=32
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_I2C_COMPAT is not set
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_HELPER_AUTO is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SENSORS_ADT7475=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_DEBUG=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_M41T80=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_XFS_FS=y
|
||||
CONFIG_XFS_QUOTA=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_QUOTA=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_15=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
|
|
@ -1,122 +0,0 @@
|
|||
CONFIG_MIPS_SEAD3=y
|
||||
CONFIG_CPU_LITTLE_ENDIAN=y
|
||||
CONFIG_CPU_MIPS32_R2=y
|
||||
CONFIG_CPU_MICROMIPS=y
|
||||
CONFIG_HZ_100=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=15
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_PROFILING=y
|
||||
CONFIG_OPROFILE=y
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
|
||||
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
|
||||
# CONFIG_INET_XFRM_MODE_BEET is not set
|
||||
# CONFIG_INET_LRO is not set
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_PHYSMAP=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_GLUEBI=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=m
|
||||
CONFIG_SCSI=y
|
||||
# CONFIG_SCSI_PROC_FS is not set
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
CONFIG_CHR_DEV_SG=y
|
||||
# CONFIG_SCSI_LOWLEVEL is not set
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_SMSC911X=y
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_QSEMI_PHY=y
|
||||
CONFIG_LXT_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
CONFIG_VITESSE_PHY=y
|
||||
CONFIG_SMSC_PHY=y
|
||||
CONFIG_BROADCOM_PHY=y
|
||||
CONFIG_ICPLUS_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
# CONFIG_SERIO is not set
|
||||
# CONFIG_CONSOLE_TRANSLATIONS is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=32
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_I2C_COMPAT is not set
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
# CONFIG_I2C_HELPER_AUTO is not set
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SENSORS_ADT7475=y
|
||||
CONFIG_BACKLIGHT_LCD_SUPPORT=y
|
||||
CONFIG_LCD_CLASS_DEVICE=y
|
||||
CONFIG_BACKLIGHT_CLASS_DEVICE=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_ROOT_HUB_TT=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_DEBUG=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_M41T80=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_XFS_FS=y
|
||||
CONFIG_XFS_QUOTA=y
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_QUOTA=y
|
||||
# CONFIG_PRINT_QUOTA_WARNING is not set
|
||||
CONFIG_MSDOS_FS=m
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_ISO8859_15=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_ARC4=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
19
arch/mips/generic/Kconfig
Normal file
19
arch/mips/generic/Kconfig
Normal file
|
|
@ -0,0 +1,19 @@
|
|||
if MIPS_GENERIC
|
||||
|
||||
config LEGACY_BOARDS
|
||||
bool
|
||||
help
|
||||
Select this from your board if the board must use a legacy, non-UHI,
|
||||
boot protocol. This will cause the kernel to scan through the list of
|
||||
supported machines calling their detect functions in turn if the
|
||||
kernel is booted without being provided with an FDT via the UHI
|
||||
boot protocol.
|
||||
|
||||
config LEGACY_BOARD_SEAD3
|
||||
bool "Support MIPS SEAD-3 boards"
|
||||
select LEGACY_BOARDS
|
||||
help
|
||||
Enable this to include support for booting on MIPS SEAD-3 FPGA-based
|
||||
development boards, which boot using a legacy boot protocol.
|
||||
|
||||
endif
|
||||
15
arch/mips/generic/Makefile
Normal file
15
arch/mips/generic/Makefile
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
#
|
||||
# Copyright (C) 2016 Imagination Technologies
|
||||
# Author: Paul Burton <paul.burton@imgtec.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; either version 2 of the License, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
|
||||
obj-y += init.o
|
||||
obj-y += irq.o
|
||||
obj-y += proc.o
|
||||
|
||||
obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
|
||||
14
arch/mips/generic/Platform
Normal file
14
arch/mips/generic/Platform
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
#
|
||||
# Copyright (C) 2016 Imagination Technologies
|
||||
# Author: Paul Burton <paul.burton@imgtec.com>
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; either version 2 of the License, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
|
||||
platform-$(CONFIG_MIPS_GENERIC) += generic/
|
||||
cflags-$(CONFIG_MIPS_GENERIC) += -I$(srctree)/arch/mips/include/asm/mach-generic
|
||||
load-$(CONFIG_MIPS_GENERIC) += 0xffffffff80100000
|
||||
all-$(CONFIG_MIPS_GENERIC) := vmlinux.gz.itb
|
||||
376
arch/mips/generic/board-sead3.c
Normal file
376
arch/mips/generic/board-sead3.c
Normal file
|
|
@ -0,0 +1,376 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "sead3: " fmt
|
||||
|
||||
#include <linux/errno.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <linux/printk.h>
|
||||
|
||||
#include <asm/fw/fw.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/machine.h>
|
||||
|
||||
#define SEAD_CONFIG CKSEG1ADDR(0x1b100110)
|
||||
#define SEAD_CONFIG_GIC_PRESENT BIT(1)
|
||||
|
||||
#define MIPS_REVISION CKSEG1ADDR(0x1fc00010)
|
||||
#define MIPS_REVISION_MACHINE (0xf << 4)
|
||||
#define MIPS_REVISION_MACHINE_SEAD3 (0x4 << 4)
|
||||
|
||||
static __init bool sead3_detect(void)
|
||||
{
|
||||
uint32_t rev;
|
||||
|
||||
rev = __raw_readl((void *)MIPS_REVISION);
|
||||
return (rev & MIPS_REVISION_MACHINE) == MIPS_REVISION_MACHINE_SEAD3;
|
||||
}
|
||||
|
||||
static __init int append_cmdline(void *fdt)
|
||||
{
|
||||
int err, chosen_off;
|
||||
|
||||
/* find or add chosen node */
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen@0");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
|
||||
if (chosen_off < 0) {
|
||||
pr_err("Unable to find or add DT chosen node: %d\n",
|
||||
chosen_off);
|
||||
return chosen_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_string(fdt, chosen_off, "bootargs", fw_getcmdline());
|
||||
if (err) {
|
||||
pr_err("Unable to set bootargs property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int append_memory(void *fdt)
|
||||
{
|
||||
unsigned long phys_memsize, memsize;
|
||||
__be32 mem_array[2];
|
||||
int err, mem_off;
|
||||
char *var;
|
||||
|
||||
/* find memory size from the bootloader environment */
|
||||
var = fw_getenv("memsize");
|
||||
if (var) {
|
||||
err = kstrtoul(var, 0, &phys_memsize);
|
||||
if (err) {
|
||||
pr_err("Failed to read memsize env variable '%s'\n",
|
||||
var);
|
||||
return -EINVAL;
|
||||
}
|
||||
} else {
|
||||
pr_warn("The bootloader didn't provide memsize: defaulting to 32MB\n");
|
||||
phys_memsize = 32 << 20;
|
||||
}
|
||||
|
||||
/* default to using all available RAM */
|
||||
memsize = phys_memsize;
|
||||
|
||||
/* allow the user to override the usable memory */
|
||||
var = strstr(arcs_cmdline, "memsize=");
|
||||
if (var)
|
||||
memsize = memparse(var + strlen("memsize="), NULL);
|
||||
|
||||
/* if the user says there's more RAM than we thought, believe them */
|
||||
phys_memsize = max_t(unsigned long, phys_memsize, memsize);
|
||||
|
||||
/* find or add a memory node */
|
||||
mem_off = fdt_path_offset(fdt, "/memory");
|
||||
if (mem_off == -FDT_ERR_NOTFOUND)
|
||||
mem_off = fdt_add_subnode(fdt, 0, "memory");
|
||||
if (mem_off < 0) {
|
||||
pr_err("Unable to find or add memory DT node: %d\n", mem_off);
|
||||
return mem_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_string(fdt, mem_off, "device_type", "memory");
|
||||
if (err) {
|
||||
pr_err("Unable to set memory node device_type: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
mem_array[0] = 0;
|
||||
mem_array[1] = cpu_to_be32(phys_memsize);
|
||||
err = fdt_setprop(fdt, mem_off, "reg", mem_array, sizeof(mem_array));
|
||||
if (err) {
|
||||
pr_err("Unable to set memory regs property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
mem_array[0] = 0;
|
||||
mem_array[1] = cpu_to_be32(memsize);
|
||||
err = fdt_setprop(fdt, mem_off, "linux,usable-memory",
|
||||
mem_array, sizeof(mem_array));
|
||||
if (err) {
|
||||
pr_err("Unable to set linux,usable-memory property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int remove_gic(void *fdt)
|
||||
{
|
||||
const unsigned int cpu_ehci_int = 2;
|
||||
const unsigned int cpu_uart_int = 4;
|
||||
const unsigned int cpu_eth_int = 6;
|
||||
int gic_off, cpu_off, uart_off, eth_off, ehci_off, err;
|
||||
uint32_t cfg, cpu_phandle;
|
||||
|
||||
/* leave the GIC node intact if a GIC is present */
|
||||
cfg = __raw_readl((uint32_t *)SEAD_CONFIG);
|
||||
if (cfg & SEAD_CONFIG_GIC_PRESENT)
|
||||
return 0;
|
||||
|
||||
gic_off = fdt_node_offset_by_compatible(fdt, -1, "mti,gic");
|
||||
if (gic_off < 0) {
|
||||
pr_err("unable to find DT GIC node: %d\n", gic_off);
|
||||
return gic_off;
|
||||
}
|
||||
|
||||
err = fdt_nop_node(fdt, gic_off);
|
||||
if (err) {
|
||||
pr_err("unable to nop GIC node\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
cpu_off = fdt_node_offset_by_compatible(fdt, -1,
|
||||
"mti,cpu-interrupt-controller");
|
||||
if (cpu_off < 0) {
|
||||
pr_err("unable to find CPU intc node: %d\n", cpu_off);
|
||||
return cpu_off;
|
||||
}
|
||||
|
||||
cpu_phandle = fdt_get_phandle(fdt, cpu_off);
|
||||
if (!cpu_phandle) {
|
||||
pr_err("unable to get CPU intc phandle\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = fdt_setprop_u32(fdt, 0, "interrupt-parent", cpu_phandle);
|
||||
if (err) {
|
||||
pr_err("unable to set root interrupt-parent: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
uart_off = fdt_node_offset_by_compatible(fdt, -1, "ns16550a");
|
||||
while (uart_off >= 0) {
|
||||
err = fdt_setprop_u32(fdt, uart_off, "interrupts",
|
||||
cpu_uart_int);
|
||||
if (err) {
|
||||
pr_err("unable to set UART interrupts property: %d\n",
|
||||
err);
|
||||
return err;
|
||||
}
|
||||
|
||||
uart_off = fdt_node_offset_by_compatible(fdt, uart_off,
|
||||
"ns16550a");
|
||||
}
|
||||
if (uart_off != -FDT_ERR_NOTFOUND) {
|
||||
pr_err("error searching for UART DT node: %d\n", uart_off);
|
||||
return uart_off;
|
||||
}
|
||||
|
||||
eth_off = fdt_node_offset_by_compatible(fdt, -1, "smsc,lan9115");
|
||||
if (eth_off < 0) {
|
||||
pr_err("unable to find ethernet DT node: %d\n", eth_off);
|
||||
return eth_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_u32(fdt, eth_off, "interrupts", cpu_eth_int);
|
||||
if (err) {
|
||||
pr_err("unable to set ethernet interrupts property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
ehci_off = fdt_node_offset_by_compatible(fdt, -1, "generic-ehci");
|
||||
if (ehci_off < 0) {
|
||||
pr_err("unable to find EHCI DT node: %d\n", ehci_off);
|
||||
return ehci_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_u32(fdt, ehci_off, "interrupts", cpu_ehci_int);
|
||||
if (err) {
|
||||
pr_err("unable to set EHCI interrupts property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init int serial_config(void *fdt)
|
||||
{
|
||||
const char *yamontty, *mode_var;
|
||||
char mode_var_name[9], path[18], parity;
|
||||
unsigned int uart, baud, stop_bits;
|
||||
bool hw_flow;
|
||||
int chosen_off, err;
|
||||
|
||||
yamontty = fw_getenv("yamontty");
|
||||
if (!yamontty || !strcmp(yamontty, "tty0")) {
|
||||
uart = 0;
|
||||
} else if (!strcmp(yamontty, "tty1")) {
|
||||
uart = 1;
|
||||
} else {
|
||||
pr_warn("yamontty environment variable '%s' invalid\n",
|
||||
yamontty);
|
||||
uart = 0;
|
||||
}
|
||||
|
||||
baud = stop_bits = 0;
|
||||
parity = 0;
|
||||
hw_flow = false;
|
||||
|
||||
snprintf(mode_var_name, sizeof(mode_var_name), "modetty%u", uart);
|
||||
mode_var = fw_getenv(mode_var_name);
|
||||
if (mode_var) {
|
||||
while (mode_var[0] >= '0' && mode_var[0] <= '9') {
|
||||
baud *= 10;
|
||||
baud += mode_var[0] - '0';
|
||||
mode_var++;
|
||||
}
|
||||
if (mode_var[0] == ',')
|
||||
mode_var++;
|
||||
if (mode_var[0])
|
||||
parity = mode_var[0];
|
||||
if (mode_var[0] == ',')
|
||||
mode_var++;
|
||||
if (mode_var[0])
|
||||
stop_bits = mode_var[0] - '0';
|
||||
if (mode_var[0] == ',')
|
||||
mode_var++;
|
||||
if (!strcmp(mode_var, "hw"))
|
||||
hw_flow = true;
|
||||
}
|
||||
|
||||
if (!baud)
|
||||
baud = 38400;
|
||||
|
||||
if (parity != 'e' && parity != 'n' && parity != 'o')
|
||||
parity = 'n';
|
||||
|
||||
if (stop_bits != 7 && stop_bits != 8)
|
||||
stop_bits = 8;
|
||||
|
||||
WARN_ON(snprintf(path, sizeof(path), "uart%u:%u%c%u%s",
|
||||
uart, baud, parity, stop_bits,
|
||||
hw_flow ? "r" : "") >= sizeof(path));
|
||||
|
||||
/* find or add chosen node */
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_path_offset(fdt, "/chosen@0");
|
||||
if (chosen_off == -FDT_ERR_NOTFOUND)
|
||||
chosen_off = fdt_add_subnode(fdt, 0, "chosen");
|
||||
if (chosen_off < 0) {
|
||||
pr_err("Unable to find or add DT chosen node: %d\n",
|
||||
chosen_off);
|
||||
return chosen_off;
|
||||
}
|
||||
|
||||
err = fdt_setprop_string(fdt, chosen_off, "stdout-path", path);
|
||||
if (err) {
|
||||
pr_err("Unable to set stdout-path property: %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static __init const void *sead3_fixup_fdt(const void *fdt,
|
||||
const void *match_data)
|
||||
{
|
||||
static unsigned char fdt_buf[16 << 10] __initdata;
|
||||
int err;
|
||||
|
||||
if (fdt_check_header(fdt))
|
||||
panic("Corrupt DT");
|
||||
|
||||
/* if this isn't SEAD3, something went wrong */
|
||||
BUG_ON(fdt_node_check_compatible(fdt, 0, "mti,sead-3"));
|
||||
|
||||
fw_init_cmdline();
|
||||
|
||||
err = fdt_open_into(fdt, fdt_buf, sizeof(fdt_buf));
|
||||
if (err)
|
||||
panic("Unable to open FDT: %d", err);
|
||||
|
||||
err = append_cmdline(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
|
||||
err = append_memory(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
|
||||
err = remove_gic(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
|
||||
err = serial_config(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to patch FDT: %d", err);
|
||||
|
||||
err = fdt_pack(fdt_buf);
|
||||
if (err)
|
||||
panic("Unable to pack FDT: %d\n", err);
|
||||
|
||||
return fdt_buf;
|
||||
}
|
||||
|
||||
static __init unsigned int sead3_measure_hpt_freq(void)
|
||||
{
|
||||
void __iomem *status_reg = (void __iomem *)0xbf000410;
|
||||
unsigned int freq, orig, tick = 0;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
orig = readl(status_reg) & 0x2; /* get original sample */
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
|
||||
write_c0_count(0);
|
||||
|
||||
/* wait 1 second (the sampling clock transitions every 10ms) */
|
||||
while (tick < 100) {
|
||||
/* wait for transition */
|
||||
while ((readl(status_reg) & 0x2) == orig)
|
||||
;
|
||||
orig = orig ^ 0x2; /* flip the bit */
|
||||
tick++;
|
||||
}
|
||||
|
||||
freq = read_c0_count();
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return freq;
|
||||
}
|
||||
|
||||
extern char __dtb_sead3_begin[];
|
||||
|
||||
MIPS_MACHINE(sead3) = {
|
||||
.fdt = __dtb_sead3_begin,
|
||||
.detect = sead3_detect,
|
||||
.fixup_fdt = sead3_fixup_fdt,
|
||||
.measure_hpt_freq = sead3_measure_hpt_freq,
|
||||
};
|
||||
176
arch/mips/generic/init.c
Normal file
176
arch/mips/generic/init.c
Normal file
|
|
@ -0,0 +1,176 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/fw/fw.h>
|
||||
#include <asm/irq_cpu.h>
|
||||
#include <asm/machine.h>
|
||||
#include <asm/mips-cpc.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/smp-ops.h>
|
||||
#include <asm/time.h>
|
||||
|
||||
static __initdata const void *fdt;
|
||||
static __initdata const struct mips_machine *mach;
|
||||
static __initdata const void *mach_match_data;
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
const struct mips_machine *check_mach;
|
||||
const struct of_device_id *match;
|
||||
|
||||
if ((fw_arg0 == -2) && !fdt_check_header((void *)fw_arg1)) {
|
||||
/*
|
||||
* We booted using the UHI boot protocol, so we have been
|
||||
* provided with the appropriate device tree for the board.
|
||||
* Make use of it & search for any machine struct based upon
|
||||
* the root compatible string.
|
||||
*/
|
||||
fdt = (void *)fw_arg1;
|
||||
|
||||
for_each_mips_machine(check_mach) {
|
||||
match = mips_machine_is_compatible(check_mach, fdt);
|
||||
if (match) {
|
||||
mach = check_mach;
|
||||
mach_match_data = match->data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
} else if (IS_ENABLED(CONFIG_LEGACY_BOARDS)) {
|
||||
/*
|
||||
* We weren't booted using the UHI boot protocol, but do
|
||||
* support some number of boards with legacy boot protocols.
|
||||
* Attempt to find the right one.
|
||||
*/
|
||||
for_each_mips_machine(check_mach) {
|
||||
if (!check_mach->detect)
|
||||
continue;
|
||||
|
||||
if (!check_mach->detect())
|
||||
continue;
|
||||
|
||||
mach = check_mach;
|
||||
}
|
||||
|
||||
/*
|
||||
* If we don't recognise the machine then we can't continue, so
|
||||
* die here.
|
||||
*/
|
||||
BUG_ON(!mach);
|
||||
|
||||
/* Retrieve the machine's FDT */
|
||||
fdt = mach->fdt;
|
||||
}
|
||||
|
||||
BUG_ON(!fdt);
|
||||
}
|
||||
|
||||
void __init *plat_get_fdt(void)
|
||||
{
|
||||
return (void *)fdt;
|
||||
}
|
||||
|
||||
void __init plat_mem_setup(void)
|
||||
{
|
||||
if (mach && mach->fixup_fdt)
|
||||
fdt = mach->fixup_fdt(fdt, mach_match_data);
|
||||
|
||||
strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
|
||||
__dt_setup_arch((void *)fdt);
|
||||
}
|
||||
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
int err;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
mips_cpc_probe();
|
||||
|
||||
err = register_cps_smp_ops();
|
||||
if (err)
|
||||
err = register_up_smp_ops();
|
||||
}
|
||||
|
||||
void __init plat_time_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
struct clk *clk;
|
||||
|
||||
of_clk_init(NULL);
|
||||
|
||||
if (!cpu_has_counter) {
|
||||
mips_hpt_frequency = 0;
|
||||
} else if (mach && mach->measure_hpt_freq) {
|
||||
mips_hpt_frequency = mach->measure_hpt_freq();
|
||||
} else {
|
||||
np = of_get_cpu_node(0, NULL);
|
||||
if (!np) {
|
||||
pr_err("Failed to get CPU node\n");
|
||||
return;
|
||||
}
|
||||
|
||||
clk = of_clk_get(np, 0);
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
|
||||
return;
|
||||
}
|
||||
|
||||
mips_hpt_frequency = clk_get_rate(clk);
|
||||
clk_put(clk);
|
||||
|
||||
switch (boot_cpu_type()) {
|
||||
case CPU_20KC:
|
||||
case CPU_25KF:
|
||||
/* The counter runs at the CPU clock rate */
|
||||
break;
|
||||
default:
|
||||
/* The counter runs at half the CPU clock rate */
|
||||
mips_hpt_frequency /= 2;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
clocksource_probe();
|
||||
}
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
struct device_node *intc_node;
|
||||
|
||||
intc_node = of_find_compatible_node(NULL, NULL,
|
||||
"mti,cpu-interrupt-controller");
|
||||
if (!cpu_has_veic && !intc_node)
|
||||
mips_cpu_irq_init();
|
||||
|
||||
irqchip_init();
|
||||
}
|
||||
|
||||
static int __init publish_devices(void)
|
||||
{
|
||||
if (!of_have_populated_dt())
|
||||
panic("Device-tree not present");
|
||||
|
||||
if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
|
||||
panic("Failed to populate DT");
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(publish_devices);
|
||||
|
||||
void __init prom_free_prom_memory(void)
|
||||
{
|
||||
}
|
||||
64
arch/mips/generic/irq.c
Normal file
64
arch/mips/generic/irq.c
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clocksource.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/irqchip/mips-gic.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
||||
int get_c0_fdc_int(void)
|
||||
{
|
||||
int mips_cpu_fdc_irq;
|
||||
|
||||
if (cpu_has_veic)
|
||||
panic("Unimplemented!");
|
||||
else if (gic_present)
|
||||
mips_cpu_fdc_irq = gic_get_c0_fdc_int();
|
||||
else if (cp0_fdc_irq >= 0)
|
||||
mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
|
||||
else
|
||||
mips_cpu_fdc_irq = -1;
|
||||
|
||||
return mips_cpu_fdc_irq;
|
||||
}
|
||||
|
||||
int get_c0_perfcount_int(void)
|
||||
{
|
||||
int mips_cpu_perf_irq;
|
||||
|
||||
if (cpu_has_veic)
|
||||
panic("Unimplemented!");
|
||||
else if (gic_present)
|
||||
mips_cpu_perf_irq = gic_get_c0_perfcount_int();
|
||||
else if (cp0_perfcount_irq >= 0)
|
||||
mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
|
||||
else
|
||||
mips_cpu_perf_irq = -1;
|
||||
|
||||
return mips_cpu_perf_irq;
|
||||
}
|
||||
|
||||
unsigned int get_c0_compare_int(void)
|
||||
{
|
||||
int mips_cpu_timer_irq;
|
||||
|
||||
if (cpu_has_veic)
|
||||
panic("Unimplemented!");
|
||||
else if (gic_present)
|
||||
mips_cpu_timer_irq = gic_get_c0_compare_int();
|
||||
else
|
||||
mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
|
||||
|
||||
return mips_cpu_timer_irq;
|
||||
}
|
||||
29
arch/mips/generic/proc.c
Normal file
29
arch/mips/generic/proc.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Imagination Technologies
|
||||
* Author: Paul Burton <paul.burton@imgtec.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/of.h>
|
||||
|
||||
#include <asm/bootinfo.h>
|
||||
|
||||
const char *get_system_type(void)
|
||||
{
|
||||
const char *str;
|
||||
int err;
|
||||
|
||||
err = of_property_read_string(of_root, "model", &str);
|
||||
if (!err)
|
||||
return str;
|
||||
|
||||
err = of_property_read_string_index(of_root, "compatible", 0, &str);
|
||||
if (!err)
|
||||
return str;
|
||||
|
||||
return "Unknown";
|
||||
}
|
||||
31
arch/mips/generic/vmlinux.its.S
Normal file
31
arch/mips/generic/vmlinux.its.S
Normal file
|
|
@ -0,0 +1,31 @@
|
|||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
description = KERNEL_NAME;
|
||||
#address-cells = <ADDR_CELLS>;
|
||||
|
||||
images {
|
||||
kernel@0 {
|
||||
description = KERNEL_NAME;
|
||||
data = /incbin/(VMLINUX_BINARY);
|
||||
type = "kernel";
|
||||
arch = "mips";
|
||||
os = "linux";
|
||||
compression = VMLINUX_COMPRESSION;
|
||||
load = /bits/ ADDR_BITS <VMLINUX_LOAD_ADDRESS>;
|
||||
entry = /bits/ ADDR_BITS <VMLINUX_ENTRY_ADDRESS>;
|
||||
hash@0 {
|
||||
algo = "sha1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
configurations {
|
||||
default = "conf@default";
|
||||
|
||||
conf@default {
|
||||
description = "Generic Linux kernel";
|
||||
kernel = "kernel@0";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -126,8 +126,7 @@
|
|||
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
|
||||
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
|
||||
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
|
||||
#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \
|
||||
(_CONST64_(cm) << 59) | (a))
|
||||
#define PHYS_TO_XKPHYS(cm, a) (XKPHYS | (_ACAST64_(cm) << 59) | (a))
|
||||
|
||||
/*
|
||||
* The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting
|
||||
|
|
|
|||
|
|
@ -10,6 +10,102 @@
|
|||
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
/*
|
||||
* Sync types defined by the MIPS architecture (document MD00087 table 6.5)
|
||||
* These values are used with the sync instruction to perform memory barriers.
|
||||
* Types of ordering guarantees available through the SYNC instruction:
|
||||
* - Completion Barriers
|
||||
* - Ordering Barriers
|
||||
* As compared to the completion barrier, the ordering barrier is a
|
||||
* lighter-weight operation as it does not require the specified instructions
|
||||
* before the SYNC to be already completed. Instead it only requires that those
|
||||
* specified instructions which are subsequent to the SYNC in the instruction
|
||||
* stream are never re-ordered for processing ahead of the specified
|
||||
* instructions which are before the SYNC in the instruction stream.
|
||||
* This potentially reduces how many cycles the barrier instruction must stall
|
||||
* before it completes.
|
||||
* Implementations that do not use any of the non-zero values of stype to define
|
||||
* different barriers, such as ordering barriers, must make those stype values
|
||||
* act the same as stype zero.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Completion barriers:
|
||||
* - Every synchronizable specified memory instruction (loads or stores or both)
|
||||
* that occurs in the instruction stream before the SYNC instruction must be
|
||||
* already globally performed before any synchronizable specified memory
|
||||
* instructions that occur after the SYNC are allowed to be performed, with
|
||||
* respect to any other processor or coherent I/O module.
|
||||
*
|
||||
* - The barrier does not guarantee the order in which instruction fetches are
|
||||
* performed.
|
||||
*
|
||||
* - A stype value of zero will always be defined such that it performs the most
|
||||
* complete set of synchronization operations that are defined.This means
|
||||
* stype zero always does a completion barrier that affects both loads and
|
||||
* stores preceding the SYNC instruction and both loads and stores that are
|
||||
* subsequent to the SYNC instruction. Non-zero values of stype may be defined
|
||||
* by the architecture or specific implementations to perform synchronization
|
||||
* behaviors that are less complete than that of stype zero. If an
|
||||
* implementation does not use one of these non-zero values to define a
|
||||
* different synchronization behavior, then that non-zero value of stype must
|
||||
* act the same as stype zero completion barrier. This allows software written
|
||||
* for an implementation with a lighter-weight barrier to work on another
|
||||
* implementation which only implements the stype zero completion barrier.
|
||||
*
|
||||
* - A completion barrier is required, potentially in conjunction with SSNOP (in
|
||||
* Release 1 of the Architecture) or EHB (in Release 2 of the Architecture),
|
||||
* to guarantee that memory reference results are visible across operating
|
||||
* mode changes. For example, a completion barrier is required on some
|
||||
* implementations on entry to and exit from Debug Mode to guarantee that
|
||||
* memory effects are handled correctly.
|
||||
*/
|
||||
|
||||
/*
|
||||
* stype 0 - A completion barrier that affects preceding loads and stores and
|
||||
* subsequent loads and stores.
|
||||
* Older instructions which must reach the load/store ordering point before the
|
||||
* SYNC instruction completes: Loads, Stores
|
||||
* Younger instructions which must reach the load/store ordering point only
|
||||
* after the SYNC instruction completes: Loads, Stores
|
||||
* Older instructions which must be globally performed when the SYNC instruction
|
||||
* completes: Loads, Stores
|
||||
*/
|
||||
#define STYPE_SYNC 0x0
|
||||
|
||||
/*
|
||||
* Ordering barriers:
|
||||
* - Every synchronizable specified memory instruction (loads or stores or both)
|
||||
* that occurs in the instruction stream before the SYNC instruction must
|
||||
* reach a stage in the load/store datapath after which no instruction
|
||||
* re-ordering is possible before any synchronizable specified memory
|
||||
* instruction which occurs after the SYNC instruction in the instruction
|
||||
* stream reaches the same stage in the load/store datapath.
|
||||
*
|
||||
* - If any memory instruction before the SYNC instruction in program order,
|
||||
* generates a memory request to the external memory and any memory
|
||||
* instruction after the SYNC instruction in program order also generates a
|
||||
* memory request to external memory, the memory request belonging to the
|
||||
* older instruction must be globally performed before the time the memory
|
||||
* request belonging to the younger instruction is globally performed.
|
||||
*
|
||||
* - The barrier does not guarantee the order in which instruction fetches are
|
||||
* performed.
|
||||
*/
|
||||
|
||||
/*
|
||||
* stype 0x10 - An ordering barrier that affects preceding loads and stores and
|
||||
* subsequent loads and stores.
|
||||
* Older instructions which must reach the load/store ordering point before the
|
||||
* SYNC instruction completes: Loads, Stores
|
||||
* Younger instructions which must reach the load/store ordering point only
|
||||
* after the SYNC instruction completes: Loads, Stores
|
||||
* Older instructions which must be globally performed when the SYNC instruction
|
||||
* completes: N/A
|
||||
*/
|
||||
#define STYPE_SYNC_MB 0x10
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_SYNC
|
||||
#define __sync() \
|
||||
__asm__ __volatile__( \
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
* - flush_cache_sigtramp() flush signal trampoline
|
||||
* - flush_icache_all() flush the entire instruction cache
|
||||
* - flush_data_cache_page() flushes a page from the data cache
|
||||
* - __flush_icache_user_range(start, end) flushes range of user instructions
|
||||
*/
|
||||
|
||||
/*
|
||||
|
|
@ -80,6 +81,10 @@ static inline void flush_icache_page(struct vm_area_struct *vma,
|
|||
|
||||
extern void (*flush_icache_range)(unsigned long start, unsigned long end);
|
||||
extern void (*local_flush_icache_range)(unsigned long start, unsigned long end);
|
||||
extern void (*__flush_icache_user_range)(unsigned long start,
|
||||
unsigned long end);
|
||||
extern void (*__local_flush_icache_user_range)(unsigned long start,
|
||||
unsigned long end);
|
||||
|
||||
extern void (*__flush_cache_vmap)(void);
|
||||
|
||||
|
|
|
|||
|
|
@ -24,7 +24,8 @@ static inline int __pure __get_cpu_type(const int cpu_type)
|
|||
case CPU_LOONGSON3:
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
|
||||
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON1B) || \
|
||||
defined(CONFIG_SYS_HAS_CPU_LOONGSON1C)
|
||||
case CPU_LOONGSON1:
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -240,6 +240,7 @@
|
|||
#define PRID_REV_VR4130 0x0080
|
||||
#define PRID_REV_34K_V1_0_2 0x0022
|
||||
#define PRID_REV_LOONGSON1B 0x0020
|
||||
#define PRID_REV_LOONGSON1C 0x0020 /* Same as Loongson-1B */
|
||||
#define PRID_REV_LOONGSON2E 0x0002
|
||||
#define PRID_REV_LOONGSON2F 0x0003
|
||||
#define PRID_REV_LOONGSON3A_R1 0x0005
|
||||
|
|
|
|||
|
|
@ -11,6 +11,11 @@ struct dma_map_ops;
|
|||
struct dev_archdata {
|
||||
/* DMA operations on that device */
|
||||
struct dma_map_ops *dma_ops;
|
||||
|
||||
#ifdef CONFIG_DMA_PERDEV_COHERENT
|
||||
/* Non-zero if DMA is coherent with CPU caches */
|
||||
bool dma_coherent;
|
||||
#endif
|
||||
};
|
||||
|
||||
struct pdev_archdata {
|
||||
|
|
|
|||
|
|
@ -9,14 +9,22 @@
|
|||
#ifndef __ASM_DMA_COHERENCE_H
|
||||
#define __ASM_DMA_COHERENCE_H
|
||||
|
||||
#ifdef CONFIG_DMA_MAYBE_COHERENT
|
||||
extern int coherentio;
|
||||
enum coherent_io_user_state {
|
||||
IO_COHERENCE_DEFAULT,
|
||||
IO_COHERENCE_ENABLED,
|
||||
IO_COHERENCE_DISABLED,
|
||||
};
|
||||
|
||||
#if defined(CONFIG_DMA_PERDEV_COHERENT)
|
||||
/* Don't provide (hw_)coherentio to avoid misuse */
|
||||
#elif defined(CONFIG_DMA_MAYBE_COHERENT)
|
||||
extern enum coherent_io_user_state coherentio;
|
||||
extern int hw_coherentio;
|
||||
#else
|
||||
#ifdef CONFIG_DMA_COHERENT
|
||||
#define coherentio 1
|
||||
#define coherentio IO_COHERENCE_ENABLED
|
||||
#else
|
||||
#define coherentio 0
|
||||
#define coherentio IO_COHERENCE_DISABLED
|
||||
#endif
|
||||
#define hw_coherentio 0
|
||||
#endif /* CONFIG_DMA_MAYBE_COHERENT */
|
||||
|
|
|
|||
|
|
@ -32,4 +32,14 @@ static inline void dma_mark_clean(void *addr, size_t size) {}
|
|||
extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
|
||||
enum dma_data_direction direction);
|
||||
|
||||
#define arch_setup_dma_ops arch_setup_dma_ops
|
||||
static inline void arch_setup_dma_ops(struct device *dev, u64 dma_base,
|
||||
u64 size, const struct iommu_ops *iommu,
|
||||
bool coherent)
|
||||
{
|
||||
#ifdef CONFIG_DMA_PERDEV_COHERENT
|
||||
dev->archdata.dma_coherent = coherent;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* _ASM_DMA_MAPPING_H */
|
||||
|
|
|
|||
|
|
@ -37,12 +37,22 @@
|
|||
|
||||
extern raw_spinlock_t i8259A_lock;
|
||||
|
||||
extern int i8259A_irq_pending(unsigned int irq);
|
||||
extern void make_8259A_irq(unsigned int irq);
|
||||
|
||||
extern void init_i8259_irqs(void);
|
||||
extern int i8259_of_init(struct device_node *node, struct device_node *parent);
|
||||
|
||||
/**
|
||||
* i8159_set_poll() - Override the i8259 polling function
|
||||
* @poll: pointer to platform-specific polling function
|
||||
*
|
||||
* Call this to override the generic i8259 polling function, which directly
|
||||
* accesses i8259 registers, with a platform specific one which may be faster
|
||||
* in cases where hardware provides a more optimal means of polling for an
|
||||
* interrupt.
|
||||
*/
|
||||
extern void i8259_set_poll(int (*poll)(void));
|
||||
|
||||
/*
|
||||
* Do the traditional i8259 interrupt polling thing. This is for the few
|
||||
* cases where no better interrupt acknowledge method is available and we
|
||||
|
|
|
|||
|
|
@ -49,7 +49,19 @@ static inline int plat_dma_supported(struct device *dev, u64 mask)
|
|||
|
||||
static inline int plat_device_is_coherent(struct device *dev)
|
||||
{
|
||||
return coherentio;
|
||||
#ifdef CONFIG_DMA_PERDEV_COHERENT
|
||||
return dev->archdata.dma_coherent;
|
||||
#else
|
||||
switch (coherentio) {
|
||||
default:
|
||||
case IO_COHERENCE_DEFAULT:
|
||||
return hw_coherentio;
|
||||
case IO_COHERENCE_ENABLED:
|
||||
return 1;
|
||||
case IO_COHERENCE_DISABLED:
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifndef plat_post_dma_flush
|
||||
|
|
|
|||
|
|
@ -115,11 +115,7 @@ static inline unsigned long fd_getfdaddr1(void)
|
|||
|
||||
static inline unsigned long fd_dma_mem_alloc(unsigned long size)
|
||||
{
|
||||
unsigned long mem;
|
||||
|
||||
mem = __get_dma_pages(GFP_KERNEL, get_order(size));
|
||||
|
||||
return mem;
|
||||
return __get_dma_pages(GFP_KERNEL, get_order(size));
|
||||
}
|
||||
|
||||
static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
|
||||
|
|
|
|||
|
|
@ -12,6 +12,8 @@
|
|||
|
||||
#include <linux/const.h>
|
||||
|
||||
#include <asm/mipsregs.h>
|
||||
|
||||
/*
|
||||
* This gives the physical RAM offset.
|
||||
*/
|
||||
|
|
@ -52,11 +54,7 @@
|
|||
#ifdef CONFIG_64BIT
|
||||
|
||||
#ifndef CAC_BASE
|
||||
#ifdef CONFIG_DMA_NONCOHERENT
|
||||
#define CAC_BASE _AC(0x9800000000000000, UL)
|
||||
#else
|
||||
#define CAC_BASE _AC(0xa800000000000000, UL)
|
||||
#endif
|
||||
#define CAC_BASE PHYS_TO_XKPHYS(read_c0_config() & CONF_CM_CMASK, 0)
|
||||
#endif
|
||||
|
||||
#ifndef IO_BASE
|
||||
|
|
|
|||
|
|
@ -19,6 +19,7 @@
|
|||
#define IO_BASE 0x9200000000000000
|
||||
#define MSPEC_BASE 0x9400000000000000
|
||||
#define UNCAC_BASE 0x9600000000000000
|
||||
#define CAC_BASE 0xa800000000000000
|
||||
|
||||
#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
|
||||
#define TO_HSPEC(x) (HSPEC_BASE | ((x) & TO_PHYS_MASK))
|
||||
|
|
|
|||
|
|
@ -36,9 +36,14 @@
|
|||
#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
|
||||
|
||||
#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
|
||||
#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
|
||||
#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
|
||||
#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
|
||||
#endif
|
||||
#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
|
||||
#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
|
||||
#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
|
||||
|
|
@ -47,6 +52,9 @@
|
|||
#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
|
||||
#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
|
||||
#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
|
||||
#if defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
|
||||
#endif
|
||||
#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
|
||||
#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
|
||||
#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
|
||||
|
|
@ -54,18 +62,49 @@
|
|||
#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
|
||||
#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
|
||||
#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
|
||||
#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
|
||||
#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
|
||||
#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
|
||||
#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
|
||||
#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
|
||||
#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
|
||||
#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
|
||||
#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
|
||||
#endif
|
||||
|
||||
#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
|
||||
#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
|
||||
#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
|
||||
#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
|
||||
#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
|
||||
#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
|
||||
#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
|
||||
#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
|
||||
#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
|
||||
#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
|
||||
#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
|
||||
#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
|
||||
#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
|
||||
#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
|
||||
#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
|
||||
#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
|
||||
#endif
|
||||
|
||||
#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE)
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
#define INTN 4
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define INTN 5
|
||||
#endif
|
||||
|
||||
#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
|
||||
|
||||
#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,11 @@
|
|||
#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
|
||||
#define __ASM_MACH_LOONGSON32_LOONGSON1_H
|
||||
|
||||
#if defined(CONFIG_LOONGSON1_LS1B)
|
||||
#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
|
||||
#elif defined(CONFIG_LOONGSON1_LS1C)
|
||||
#define DEFAULT_MEMSIZE 32
|
||||
#endif
|
||||
|
||||
/* Loongson 1 Register Bases */
|
||||
#define LS1X_MUX_BASE 0x1fd00420
|
||||
|
|
@ -20,6 +24,7 @@
|
|||
#define LS1X_GPIO0_BASE 0x1fd010c0
|
||||
#define LS1X_GPIO1_BASE 0x1fd010c4
|
||||
#define LS1X_DMAC_BASE 0x1fd01160
|
||||
#define LS1X_CBUS_BASE 0x1fd011c0
|
||||
#define LS1X_EHCI_BASE 0x1fe00000
|
||||
#define LS1X_OHCI_BASE 0x1fe08000
|
||||
#define LS1X_GMAC0_BASE 0x1fe10000
|
||||
|
|
|
|||
|
|
@ -30,5 +30,6 @@ void __init ls1x_clk_init(void);
|
|||
void __init ls1x_dma_set_platdata(struct plat_ls1x_dma *pdata);
|
||||
void __init ls1x_nand_set_platdata(struct plat_ls1x_nand *pdata);
|
||||
void __init ls1x_serial_set_uartclk(struct platform_device *pdev);
|
||||
void __init ls1x_rtc_set_extclk(struct platform_device *pdev);
|
||||
|
||||
#endif /* __ASM_MACH_LOONGSON32_PLATFORM_H */
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue