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[MIPS] No need to write c0_compare in plat_timer_setup

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If R4k counter was used for hpt_timer and interrupt source,
c0_hpt_timer_init() initializes the c0_compare register.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Atsushi Nemoto 2007-03-01 01:53:13 +09:00 • committed by Ralf Baechle
parent a0574e0480
commit 12e4396bf0
5 changed files with 0 additions and 26 deletions
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1
arch/mips/lasat/setup.c
View file

@ -116,7 +116,6 @@ static void lasat_time_init(void)
void __init plat_timer_setup(struct irqaction *irq) void __init plat_timer_setup(struct irqaction *irq)
{ {
write_c0_compare( read_c0_count() + mips_hpt_frequency / HZ);
change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5); change_c0_status(ST0_IM, IE_IRQ0 | IE_IRQ5);
} }

3
arch/mips/mips-boards/generic/time.c
View file

@ -295,7 +295,4 @@ void __init plat_timer_setup(struct irqaction *irq)
irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU; irq_desc[mips_cpu_timer_irq].status |= IRQ_PER_CPU;
set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
#endif #endif
/* to generate the first timer interrupt */
write_c0_compare (read_c0_count() + mips_hpt_frequency/HZ);
} }

3
arch/mips/mips-boards/sim/sim_time.c
View file

@ -199,7 +199,4 @@ void __init plat_timer_setup(struct irqaction *irq)
irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU; irq_desc[mips_cpu_timer_irq].flags |= IRQ_PER_CPU;
set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq); set_irq_handler(mips_cpu_timer_irq, handle_percpu_irq);
#endif #endif
/* to generate the first timer interrupt */
write_c0_compare(read_c0_count() + (mips_hpt_frequency/HZ));
} }

10
arch/mips/tx4927/common/tx4927_setup.c
View file

@ -81,18 +81,8 @@ void __init tx4927_time_init(void)
void __init plat_timer_setup(struct irqaction *irq) void __init plat_timer_setup(struct irqaction *irq)
{ {
u32 count;
u32 c1;
u32 c2;
setup_irq(TX4927_IRQ_CPU_TIMER, irq); setup_irq(TX4927_IRQ_CPU_TIMER, irq);
/* to generate the first timer interrupt */
c1 = read_c0_count();
count = c1 + (mips_hpt_frequency / HZ);
write_c0_compare(count);
c2 = read_c0_count();
#ifdef CONFIG_TOSHIBA_RBTX4927 #ifdef CONFIG_TOSHIBA_RBTX4927
{ {
extern void toshiba_rbtx4927_timer_setup(struct irqaction extern void toshiba_rbtx4927_timer_setup(struct irqaction

9
arch/mips/tx4938/common/setup.c
View file

@ -55,14 +55,5 @@ tx4938_time_init(void)
void __init plat_timer_setup(struct irqaction *irq) void __init plat_timer_setup(struct irqaction *irq)
{ {
u32 count;
u32 c1;
u32 c2;
setup_irq(TX4938_IRQ_CPU_TIMER, irq); setup_irq(TX4938_IRQ_CPU_TIMER, irq);
c1 = read_c0_count();
count = c1 + (mips_hpt_frequency / HZ);
write_c0_compare(count);
c2 = read_c0_count();
} }