[media] IR: ene_ir: updates
* Add support for newer firmware version that uses different buffer format. Makes hardware work for many users. * Register name updates * Lot of refactoring * Lots of fixes as a result of full testing * Idle mode is done now by resetting the device, and this eliminates the ugly sample_period = 75 hack. Every feature of the driver is now well tested. Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Maxim Levitsky
Mauro Carvalho Chehab
parent
991369e33f
commit
11b64d31c0
3 changed files with 713 additions and 532 deletions
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@ -102,15 +102,15 @@ config IR_LIRC_CODEC
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the LIRC interface.
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config IR_ENE
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tristate "ENE eHome Receiver/Transciever (pnp id: ENE0100/ENE02xxx)"
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tristate "ENE eHome Receiver/Transceiver (pnp id: ENE0100/ENE02xxx)"
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depends on PNP
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depends on IR_CORE
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---help---
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Say Y here to enable support for integrated infrared receiver
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/transciever made by ENE.
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/transceiver made by ENE.
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You can see if you have it by looking at lspnp output.
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Output should include ENE0100 ENE0200 or something similiar.
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Output should include ENE0100 ENE0200 or something similar.
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To compile this driver as a module, choose M here: the
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module will be called ene_ir.
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File diff suppressed because it is too large
Load diff
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@ -1,5 +1,5 @@
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/*
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* driver for ENE KB3926 B/C/D CIR (also known as ENE0XXX)
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* driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
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*
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* Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
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*
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@ -26,43 +26,50 @@
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#define ENE_ADDR_HI 1 /* hi byte of register address */
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#define ENE_ADDR_LO 2 /* low byte of register address */
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#define ENE_IO 3 /* read/write window */
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#define ENE_MAX_IO 4
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#define ENE_IO_SIZE 4
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/* 8 bytes of samples, divided in 2 halfs*/
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#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */
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#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */
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#define ENE_SAMPLE_VALUE_MASK 0x7F
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#define ENE_SAMPLE_OVERFLOW 0x7F
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#define ENE_SAMPLES_SIZE 4
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/* 8 bytes of samples, divided in 2 packets*/
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#define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
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#define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
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#define ENE_FW_PACKET_SIZE 4
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/* fan input sample buffer */
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#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
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/* each sample of normal buffer */
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#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
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/* if set, says that sample is pulse */
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#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
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/* first firmware register */
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#define ENE_FW1 0xF8F8
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/* first firmware flag register */
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#define ENE_FW1 0xF8F8 /* flagr */
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#define ENE_FW1_ENABLE 0x01 /* enable fw processing */
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#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
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#define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
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#define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
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#define ENE_FW1_LED_ON 0x10 /* turn on a led */
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#define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
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#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
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#define ENE_FW1_IRQ 0x80 /* enable interrupt */
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/* second firmware register */
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#define ENE_FW2 0xF8F9
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#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */
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#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */
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#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */
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/* learning input */
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#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */
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/* second firmware flag register */
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#define ENE_FW2 0xF8F9 /* flagw */
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#define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
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#define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
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#define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
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#define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
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#define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
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#define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
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#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
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/* firmware RX pointer for new style buffer */
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#define ENE_FW_RX_POINTER 0xF8FA
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/* high parts of samples for fan input (8 samples)*/
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#define ENE_FW_SMPL_BUF_FAN 0xF8FB
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#define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
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#define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
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#define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
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/* transmitter ports */
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#define ENE_TX_PORT2 0xFC01 /* this enables one or both */
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#define ENE_TX_PORT2_EN 0x20 /* TX ports */
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#define ENE_TX_PORT1 0xFC08
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#define ENE_TX_PORT1_EN 0x02
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#define ENE_GPIOFS1 0xFC01
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#define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
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#define ENE_GPIOFS8 0xFC08
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#define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
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/* IRQ registers block (for revision B) */
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#define ENEB_IRQ 0xFD09 /* IRQ number */
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@ -70,98 +77,100 @@
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#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
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#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
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/* fan as input settings - only if learning capable */
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/* fan as input settings */
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#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
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#define ENE_FAN_AS_IN1_EN 0xCD
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#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
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#define ENE_FAN_AS_IN2_EN 0x03
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#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
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/* IRQ registers block (for revision C,D) */
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#define ENEC_IRQ 0xFE9B /* new irq settings register */
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#define ENEC_IRQ_MASK 0x0F /* irq number mask */
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#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */
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#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */
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#define ENE_IRQ 0xFE9B /* new irq settings register */
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#define ENE_IRQ_MASK 0x0F /* irq number mask */
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#define ENE_IRQ_UNK_EN 0x10 /* always enabled */
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#define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
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/* CIR block settings */
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#define ENE_CIR_CONF1 0xFEC0
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#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */
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/* while transmitting */
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#define ENE_CIR_CONF1_RX_ON 0x07 /* normal receiver enabled */
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#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */
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#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */
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#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */
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/* CIR Config register #1 */
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#define ENE_CIRCFG 0xFEC0
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#define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
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#define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
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#define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
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#define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
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#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */
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#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */
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#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */
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#define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
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#define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
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#define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
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#define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
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#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */
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#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */
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/* CIR config register #2 */
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#define ENE_CIRCFG2 0xFEC1
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#define ENE_CIRCFG2_RLC 0x00
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#define ENE_CIRCFG2_RC5 0x01
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#define ENE_CIRCFG2_RC6 0x02
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#define ENE_CIRCFG2_NEC 0x03
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#define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
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#define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
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#define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
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#define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
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/* Knobs for protocol decoding - will document when/if will use them */
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#define ENE_CIRPF 0xFEC2
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#define ENE_CIRHIGH 0xFEC3
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#define ENE_CIRBIT 0xFEC4
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#define ENE_CIRSTART 0xFEC5
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#define ENE_CIRSTART2 0xFEC6
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/* Actual register which contains RLC RX data - read by firmware */
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#define ENE_CIRDAT_IN 0xFEC7
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/* Two byte tx buffer */
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#define ENE_TX_INPUT1 0xFEC9
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#define ENE_TX_INPUT2 0xFECA
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#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */
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#define ENE_TX_SMLP_MASK 0x7F
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#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */
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/* RLC configuration - sample period (1us resulution) + idle mode */
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#define ENE_CIRRLC_CFG 0xFEC8
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#define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
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#define ENE_DEFAULT_SAMPLE_PERIOD 50
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/* Two byte RLC TX buffer */
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#define ENE_CIRRLC_OUT0 0xFEC9
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#define ENE_CIRRLC_OUT1 0xFECA
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#define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
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#define ENE_CIRRLC_OUT_MASK 0x7F
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/* Unknown TX setting - TX sample period ??? */
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#define ENE_TX_UNK1 0xFECB /* set to 0x63 */
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/* Carrier detect setting
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* Low nibble - number of carrier pulses to average
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* High nibble - number of initial carrier pulses to discard
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*/
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#define ENE_CIRCAR_PULS 0xFECB
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/* Current received carrier period */
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#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */
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#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */
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/* detected RX carrier period (resolution: 500 ns) */
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#define ENE_CIRCAR_PRD 0xFECC
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#define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
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/* detected RX carrier pulse width (resolution: 500 ns) */
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#define ENE_CIRCAR_HPRD 0xFECD
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/* TX period (1/carrier) */
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#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */
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#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/
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#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/
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/* TX period (resolution: 500 ns, minimum 2)*/
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#define ENE_CIRMOD_PRD 0xFECE
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#define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
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#define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
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#define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
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/* TX pulse width (resolution: 500 ns)*/
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#define ENE_CIRMOD_HPRD 0xFECF
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/* Hardware versions */
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#define ENE_HW_VERSION 0xFF00 /* hardware revision */
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#define ENE_ECHV 0xFF00 /* hardware revision */
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#define ENE_PLLFRH 0xFF16
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#define ENE_PLLFRL 0xFF17
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#define ENE_DEFAULT_PLL_FREQ 1000
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#define ENE_HW_UNK 0xFF1D
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#define ENE_HW_UNK_CLR 0x04
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#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
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#define ENE_HW_VER_MINOR 0xFF1F
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#define ENE_ECSTS 0xFF1D
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#define ENE_ECSTS_RSRVD 0x04
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#define ENE_ECVER_MAJOR 0xFF1E /* chip version */
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#define ENE_ECVER_MINOR 0xFF1F
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#define ENE_HW_VER_OLD 0xFD00
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/* Normal/Learning carrier ranges - only valid if we have learning input*/
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/* TODO: test */
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#define ENE_NORMAL_RX_LOW 34
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#define ENE_NORMAL_RX_HI 38
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/* Tx carrier range */
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/* Hardware might be able to do more, but this range is enough for
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all purposes */
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#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */
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#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */
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/* Minimal and maximal gaps */
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/* Normal case:
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Minimal gap is 0x7F * sample period
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Maximum gap depends on hardware.
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For KB3926B, it is unlimited, for newer models its around
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250000, after which HW stops sending samples, and that is
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not possible to change */
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/* Fan case:
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Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
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And there is nothing to change this setting
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*/
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#define ENE_MAXGAP 250000
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#define ENE_MINGAP (127 * sample_period)
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/******************************************************************************/
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#define ENE_DRIVER_NAME "ene_ir"
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@ -171,46 +180,60 @@
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#define ENE_HW_B 1 /* 3926B */
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#define ENE_HW_C 2 /* 3926C */
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#define ENE_HW_D 3 /* 3926D */
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#define ENE_HW_D 3 /* 3926D or later */
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#define ene_printk(level, text, ...) \
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printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__)
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printk(level ENE_DRIVER_NAME ": " text "\n", ## __VA_ARGS__)
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#define ene_dbg(text, ...) \
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if (debug) \
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printk(KERN_DEBUG \
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ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
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#define ene_notice(text, ...) ene_printk(KERN_NOTICE, text, ## __VA_ARGS__)
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#define ene_warn(text, ...) ene_printk(KERN_WARNING, text, ## __VA_ARGS__)
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#define ene_dbg_verbose(text, ...) \
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if (debug > 1) \
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printk(KERN_DEBUG \
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ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
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#define __dbg(level, format, ...) \
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do { \
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if (debug >= level) \
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printk(KERN_DEBUG ENE_DRIVER_NAME \
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": " format "\n", ## __VA_ARGS__); \
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} while (0)
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#define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
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#define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
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#define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
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#define MS_TO_NS(msec) ((msec) * 1000)
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struct ene_device {
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struct pnp_dev *pnp_dev;
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struct input_dev *idev;
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struct ir_dev_props *props;
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int in_use;
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/* hw IO settings */
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unsigned long hw_io;
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long hw_io;
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int irq;
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spinlock_t hw_lock;
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/* HW features */
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int hw_revision; /* hardware revision */
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bool hw_learning_and_tx_capable; /* learning capable */
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bool hw_gpio40_learning; /* gpio40 is learning */
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bool hw_fan_as_normal_input; /* fan input is used as */
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/* regular input */
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bool hw_use_gpio_0a; /* gpio40 is demodulated input*/
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bool hw_extra_buffer; /* hardware has 'extra buffer' */
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bool hw_fan_input; /* fan input is IR data source */
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bool hw_learning_and_tx_capable; /* learning & tx capable */
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int pll_freq;
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int buffer_len;
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/* Extra RX buffer location */
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int extra_buf1_address;
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int extra_buf1_len;
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int extra_buf2_address;
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int extra_buf2_len;
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/* HW state*/
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int rx_pointer; /* hw pointer to rx buffer */
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int r_pointer; /* pointer to next sample to read */
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int w_pointer; /* pointer to next sample hw will write */
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bool rx_fan_input_inuse; /* is fan input in use for rx*/
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int tx_reg; /* current reg used for TX */
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u8 saved_conf1; /* saved FEC0 reg */
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/* TX sample handling */
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unsigned int tx_sample; /* current sample for TX */
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bool tx_sample_pulse; /* current sample is pulse */
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@ -232,4 +255,8 @@ struct ene_device {
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bool learning_enabled; /* learning input enabled */
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bool carrier_detect_enabled; /* carrier detect enabled */
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int rx_period_adjust;
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bool rx_enabled;
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};
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static int ene_irq_status(struct ene_device *dev);
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static void ene_read_hw_pointer(struct ene_device *dev);
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