rt2x00: rt2800pci: move initialization functions to the rt2800mmio module
Move the functions into a separate module, in order to make those usable from other modules. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Gabor Juhos
John W. Linville
parent
7573afdf80
commit
1052e3a6ae
3 changed files with 169 additions and 159 deletions
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@ -689,6 +689,169 @@ void rt2800mmio_queue_init(struct data_queue *queue)
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_queue_init);
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/*
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* Initialization functions.
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*/
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bool rt2800mmio_get_entry_state(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
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}
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_get_entry_state);
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void rt2800mmio_clear_entry(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 0, &word);
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rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
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rt2x00_desc_write(entry_priv->desc, 0, word);
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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/*
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* Set RX IDX in register to inform hardware that we have
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* handled this entry and it is available for reuse again.
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*/
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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entry->entry_idx);
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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}
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_clear_entry);
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int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev)
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{
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struct queue_entry_priv_mmio *entry_priv;
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/*
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* Initialize registers.
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*/
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entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
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rt2x00dev->tx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
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entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
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rt2x00dev->tx[1].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
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entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
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rt2x00dev->tx[2].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
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entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
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rt2x00dev->tx[3].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
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entry_priv = rt2x00dev->rx->entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
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rt2x00dev->rx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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rt2x00dev->rx[0].limit - 1);
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rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
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rt2800_disable_wpdma(rt2x00dev);
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rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_init_queues);
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int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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/*
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* Reset DMA indexes
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*/
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rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
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rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
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if (rt2x00_is_pcie(rt2x00dev) &&
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(rt2x00_rt(rt2x00dev, RT3090) ||
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rt2x00_rt(rt2x00dev, RT3390) ||
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rt2x00_rt(rt2x00dev, RT3572) ||
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rt2x00_rt(rt2x00dev, RT3593) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392) ||
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rt2x00_rt(rt2x00dev, RT5592))) {
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rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®);
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rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
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rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
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rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
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}
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rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
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reg = 0;
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt2800mmio_init_registers);
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MODULE_AUTHOR(DRV_PROJECT);
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MODULE_VERSION(DRV_VERSION);
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MODULE_DESCRIPTION("rt2800 MMIO library");
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@ -153,4 +153,10 @@ void rt2800mmio_kick_queue(struct data_queue *queue);
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void rt2800mmio_stop_queue(struct data_queue *queue);
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void rt2800mmio_queue_init(struct data_queue *queue);
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/* Initialization functions */
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bool rt2800mmio_get_entry_state(struct queue_entry *entry);
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void rt2800mmio_clear_entry(struct queue_entry *entry);
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int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev);
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int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev);
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#endif /* RT2800MMIO_H */
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@ -242,168 +242,9 @@ static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
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return 0;
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}
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/*
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* Initialization functions.
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*/
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static bool rt2800mmio_get_entry_state(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
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}
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}
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static void rt2800mmio_clear_entry(struct queue_entry *entry)
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{
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struct queue_entry_priv_mmio *entry_priv = entry->priv_data;
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struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
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struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
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u32 word;
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if (entry->queue->qid == QID_RX) {
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rt2x00_desc_read(entry_priv->desc, 0, &word);
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rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
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rt2x00_desc_write(entry_priv->desc, 0, word);
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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/*
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* Set RX IDX in register to inform hardware that we have
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* handled this entry and it is available for reuse again.
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*/
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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entry->entry_idx);
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} else {
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rt2x00_desc_read(entry_priv->desc, 1, &word);
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rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
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rt2x00_desc_write(entry_priv->desc, 1, word);
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}
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}
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static int rt2800mmio_init_queues(struct rt2x00_dev *rt2x00dev)
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{
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struct queue_entry_priv_mmio *entry_priv;
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/*
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* Initialize registers.
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*/
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entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR0,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT0,
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rt2x00dev->tx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX0, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX0, 0);
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entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR1,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT1,
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rt2x00dev->tx[1].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX1, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX1, 0);
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entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR2,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT2,
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rt2x00dev->tx[2].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX2, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX2, 0);
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entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR3,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT3,
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rt2x00dev->tx[3].limit);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX3, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX4, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_BASE_PTR5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_MAX_CNT5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_CTX_IDX5, 0);
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rt2x00mmio_register_write(rt2x00dev, TX_DTX_IDX5, 0);
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entry_priv = rt2x00dev->rx->entries[0].priv_data;
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rt2x00mmio_register_write(rt2x00dev, RX_BASE_PTR,
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entry_priv->desc_dma);
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rt2x00mmio_register_write(rt2x00dev, RX_MAX_CNT,
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rt2x00dev->rx[0].limit);
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rt2x00mmio_register_write(rt2x00dev, RX_CRX_IDX,
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rt2x00dev->rx[0].limit - 1);
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rt2x00mmio_register_write(rt2x00dev, RX_DRX_IDX, 0);
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rt2800_disable_wpdma(rt2x00dev);
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rt2x00mmio_register_write(rt2x00dev, DELAY_INT_CFG, 0);
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return 0;
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}
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/*
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* Device state switch handlers.
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*/
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static int rt2800mmio_init_registers(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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/*
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* Reset DMA indexes
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*/
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rt2x00mmio_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
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rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
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rt2x00mmio_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
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if (rt2x00_is_pcie(rt2x00dev) &&
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(rt2x00_rt(rt2x00dev, RT3090) ||
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rt2x00_rt(rt2x00dev, RT3390) ||
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rt2x00_rt(rt2x00dev, RT3572) ||
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rt2x00_rt(rt2x00dev, RT3593) ||
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rt2x00_rt(rt2x00dev, RT5390) ||
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rt2x00_rt(rt2x00dev, RT5392) ||
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rt2x00_rt(rt2x00dev, RT5592))) {
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rt2x00mmio_register_read(rt2x00dev, AUX_CTRL, ®);
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rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
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rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
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rt2x00mmio_register_write(rt2x00dev, AUX_CTRL, reg);
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}
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rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
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reg = 0;
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
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rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
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rt2x00mmio_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
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return 0;
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}
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static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
|
||||
{
|
||||
int retval;
|
||||
|
|
|
|||
Loading…
Reference in a new issue