phy: rockchip-inno-usb2: add a new driver for Rockchip usb2phy
The newer SoCs (rk3366, rk3399) take a different usb-phy IP block than rk3288 and before, and most of phy-related registers are also different from the past, so a new phy driver is required necessarily. Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Suggested-by: Heiko Stuebner <heiko@sntech.de> Suggested-by: Guenter Roeck <linux@roeck-us.net> Suggested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Frank Wang
Kishon Vijay Abraham I
parent
72580a49a8
commit
0e08d2a727
3 changed files with 715 additions and 0 deletions
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@ -367,6 +367,13 @@ config PHY_ROCKCHIP_USB
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help
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Enable this to support the Rockchip USB 2.0 PHY.
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config PHY_ROCKCHIP_INNO_USB2
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tristate "Rockchip INNO USB2PHY Driver"
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depends on (ARCH_ROCKCHIP || COMPILE_TEST) && OF
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select GENERIC_PHY
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help
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Support for Rockchip USB2.0 PHY with Innosilicon IP block.
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config PHY_ROCKCHIP_EMMC
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tristate "Rockchip EMMC PHY Driver"
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depends on ARCH_ROCKCHIP && OF
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@ -40,6 +40,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
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obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
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obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
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obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
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obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
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obj-$(CONFIG_PHY_ROCKCHIP_EMMC) += phy-rockchip-emmc.o
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obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
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obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
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707
drivers/phy/phy-rockchip-inno-usb2.c
Normal file
707
drivers/phy/phy-rockchip-inno-usb2.c
Normal file
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@ -0,0 +1,707 @@
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/*
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* Rockchip USB2.0 PHY with Innosilicon IP block driver
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*
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* Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/gpio/consumer.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#define BIT_WRITEABLE_SHIFT 16
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#define SCHEDULE_DELAY (60 * HZ)
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enum rockchip_usb2phy_port_id {
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USB2PHY_PORT_OTG,
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USB2PHY_PORT_HOST,
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USB2PHY_NUM_PORTS,
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};
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enum rockchip_usb2phy_host_state {
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PHY_STATE_HS_ONLINE = 0,
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PHY_STATE_DISCONNECT = 1,
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PHY_STATE_CONNECT = 2,
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PHY_STATE_FS_LS_ONLINE = 4,
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};
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struct usb2phy_reg {
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unsigned int offset;
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unsigned int bitend;
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unsigned int bitstart;
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unsigned int disable;
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unsigned int enable;
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};
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/**
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* struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
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* @phy_sus: phy suspend register.
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* @ls_det_en: linestate detection enable register.
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* @ls_det_st: linestate detection state register.
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* @ls_det_clr: linestate detection clear register.
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* @utmi_ls: utmi linestate state register.
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* @utmi_hstdet: utmi host disconnect register.
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*/
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struct rockchip_usb2phy_port_cfg {
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struct usb2phy_reg phy_sus;
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struct usb2phy_reg ls_det_en;
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struct usb2phy_reg ls_det_st;
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struct usb2phy_reg ls_det_clr;
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struct usb2phy_reg utmi_ls;
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struct usb2phy_reg utmi_hstdet;
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};
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/**
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* struct rockchip_usb2phy_cfg: usb-phy configuration.
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* @reg: the address offset of grf for usb-phy config.
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* @num_ports: specify how many ports that the phy has.
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* @clkout_ctl: keep on/turn off output clk of phy.
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*/
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struct rockchip_usb2phy_cfg {
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unsigned int reg;
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unsigned int num_ports;
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struct usb2phy_reg clkout_ctl;
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const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
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};
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/**
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* struct rockchip_usb2phy_port: usb-phy port data.
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* @port_id: flag for otg port or host port.
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* @suspended: phy suspended flag.
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* @ls_irq: IRQ number assigned for linestate detection.
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* @mutex: for register updating in sm_work.
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* @sm_work: OTG state machine work.
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* @phy_cfg: port register configuration, assigned by driver data.
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*/
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struct rockchip_usb2phy_port {
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struct phy *phy;
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unsigned int port_id;
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bool suspended;
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int ls_irq;
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struct mutex mutex;
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struct delayed_work sm_work;
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const struct rockchip_usb2phy_port_cfg *port_cfg;
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};
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/**
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* struct rockchip_usb2phy: usb2.0 phy driver data.
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* @grf: General Register Files regmap.
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* @clk: clock struct of phy input clk.
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* @clk480m: clock struct of phy output clk.
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* @clk_hw: clock struct of phy output clk management.
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* @phy_cfg: phy register configuration, assigned by driver data.
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* @ports: phy port instance.
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*/
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struct rockchip_usb2phy {
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struct device *dev;
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struct regmap *grf;
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struct clk *clk;
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struct clk *clk480m;
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struct clk_hw clk480m_hw;
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const struct rockchip_usb2phy_cfg *phy_cfg;
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struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
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};
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static inline int property_enable(struct rockchip_usb2phy *rphy,
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const struct usb2phy_reg *reg, bool en)
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{
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unsigned int val, mask, tmp;
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tmp = en ? reg->enable : reg->disable;
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mask = GENMASK(reg->bitend, reg->bitstart);
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val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
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return regmap_write(rphy->grf, reg->offset, val);
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}
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static inline bool property_enabled(struct rockchip_usb2phy *rphy,
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const struct usb2phy_reg *reg)
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{
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int ret;
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unsigned int tmp, orig;
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unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
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ret = regmap_read(rphy->grf, reg->offset, &orig);
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if (ret)
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return false;
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tmp = (orig & mask) >> reg->bitstart;
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return tmp == reg->enable;
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}
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static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
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{
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struct rockchip_usb2phy *rphy =
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container_of(hw, struct rockchip_usb2phy, clk480m_hw);
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int ret;
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/* turn on 480m clk output if it is off */
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if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
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ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
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if (ret)
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return ret;
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/* waitting for the clk become stable */
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mdelay(1);
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}
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return 0;
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}
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static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
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{
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struct rockchip_usb2phy *rphy =
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container_of(hw, struct rockchip_usb2phy, clk480m_hw);
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/* turn off 480m clk output */
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property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
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}
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static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
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{
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struct rockchip_usb2phy *rphy =
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container_of(hw, struct rockchip_usb2phy, clk480m_hw);
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return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
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}
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static unsigned long
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rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return 480000000;
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}
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static const struct clk_ops rockchip_usb2phy_clkout_ops = {
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.enable = rockchip_usb2phy_clk480m_enable,
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.disable = rockchip_usb2phy_clk480m_disable,
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.is_enabled = rockchip_usb2phy_clk480m_enabled,
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.recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
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};
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static void rockchip_usb2phy_clk480m_unregister(void *data)
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{
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struct rockchip_usb2phy *rphy = data;
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of_clk_del_provider(rphy->dev->of_node);
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clk_unregister(rphy->clk480m);
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}
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static int
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rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
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{
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struct device_node *node = rphy->dev->of_node;
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struct clk_init_data init;
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const char *clk_name;
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int ret;
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init.flags = 0;
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init.name = "clk_usbphy_480m";
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init.ops = &rockchip_usb2phy_clkout_ops;
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/* optional override of the clockname */
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of_property_read_string(node, "clock-output-names", &init.name);
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if (rphy->clk) {
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clk_name = __clk_get_name(rphy->clk);
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init.parent_names = &clk_name;
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init.num_parents = 1;
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} else {
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init.parent_names = NULL;
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init.num_parents = 0;
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}
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rphy->clk480m_hw.init = &init;
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/* register the clock */
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rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
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if (IS_ERR(rphy->clk480m)) {
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ret = PTR_ERR(rphy->clk480m);
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goto err_ret;
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}
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ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
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if (ret < 0)
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goto err_clk_provider;
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ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
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rphy);
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if (ret < 0)
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goto err_unreg_action;
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return 0;
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err_unreg_action:
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of_clk_del_provider(node);
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err_clk_provider:
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clk_unregister(rphy->clk480m);
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err_ret:
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return ret;
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}
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static int rockchip_usb2phy_init(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
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int ret;
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if (rport->port_id == USB2PHY_PORT_HOST) {
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/* clear linestate and enable linestate detect irq */
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mutex_lock(&rport->mutex);
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ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
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if (ret) {
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mutex_unlock(&rport->mutex);
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return ret;
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}
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ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
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if (ret) {
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mutex_unlock(&rport->mutex);
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return ret;
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}
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mutex_unlock(&rport->mutex);
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schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
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}
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return 0;
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}
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static int rockchip_usb2phy_power_on(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
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int ret;
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dev_dbg(&rport->phy->dev, "port power on\n");
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if (!rport->suspended)
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return 0;
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ret = clk_prepare_enable(rphy->clk480m);
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if (ret)
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return ret;
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ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
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if (ret)
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return ret;
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rport->suspended = false;
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return 0;
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}
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static int rockchip_usb2phy_power_off(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
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int ret;
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dev_dbg(&rport->phy->dev, "port power off\n");
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if (rport->suspended)
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return 0;
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ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
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if (ret)
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return ret;
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rport->suspended = true;
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clk_disable_unprepare(rphy->clk480m);
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return 0;
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}
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static int rockchip_usb2phy_exit(struct phy *phy)
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{
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struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
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if (rport->port_id == USB2PHY_PORT_HOST)
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cancel_delayed_work_sync(&rport->sm_work);
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return 0;
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}
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static const struct phy_ops rockchip_usb2phy_ops = {
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.init = rockchip_usb2phy_init,
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.exit = rockchip_usb2phy_exit,
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.power_on = rockchip_usb2phy_power_on,
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.power_off = rockchip_usb2phy_power_off,
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.owner = THIS_MODULE,
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};
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/*
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* The function manage host-phy port state and suspend/resume phy port
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* to save power.
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*
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* we rely on utmi_linestate and utmi_hostdisconnect to identify whether
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* devices is disconnect or not. Besides, we do not need care it is FS/LS
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* disconnected or HS disconnected, actually, we just only need get the
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* device is disconnected at last through rearm the delayed work,
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* to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
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*
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* NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
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* some clk related APIs, so do not invoke it from interrupt context directly.
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*/
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static void rockchip_usb2phy_sm_work(struct work_struct *work)
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{
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struct rockchip_usb2phy_port *rport =
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container_of(work, struct rockchip_usb2phy_port, sm_work.work);
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struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
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unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
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rport->port_cfg->utmi_hstdet.bitstart + 1;
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unsigned int ul, uhd, state;
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unsigned int ul_mask, uhd_mask;
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int ret;
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mutex_lock(&rport->mutex);
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ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
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if (ret < 0)
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goto next_schedule;
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ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
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&uhd);
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if (ret < 0)
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goto next_schedule;
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uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
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rport->port_cfg->utmi_hstdet.bitstart);
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ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
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rport->port_cfg->utmi_ls.bitstart);
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/* stitch on utmi_ls and utmi_hstdet as phy state */
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state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
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(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
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switch (state) {
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case PHY_STATE_HS_ONLINE:
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dev_dbg(&rport->phy->dev, "HS online\n");
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break;
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case PHY_STATE_FS_LS_ONLINE:
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/*
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* For FS/LS device, the online state share with connect state
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* from utmi_ls and utmi_hstdet register, so we distinguish
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* them via suspended flag.
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*
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* Plus, there are two cases, one is D- Line pull-up, and D+
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* line pull-down, the state is 4; another is D+ line pull-up,
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* and D- line pull-down, the state is 2.
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*/
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if (!rport->suspended) {
|
||||
/* D- line pull-up, D+ line pull-down */
|
||||
dev_dbg(&rport->phy->dev, "FS/LS online\n");
|
||||
break;
|
||||
}
|
||||
/* fall through */
|
||||
case PHY_STATE_CONNECT:
|
||||
if (rport->suspended) {
|
||||
dev_dbg(&rport->phy->dev, "Connected\n");
|
||||
rockchip_usb2phy_power_on(rport->phy);
|
||||
rport->suspended = false;
|
||||
} else {
|
||||
/* D+ line pull-up, D- line pull-down */
|
||||
dev_dbg(&rport->phy->dev, "FS/LS online\n");
|
||||
}
|
||||
break;
|
||||
case PHY_STATE_DISCONNECT:
|
||||
if (!rport->suspended) {
|
||||
dev_dbg(&rport->phy->dev, "Disconnected\n");
|
||||
rockchip_usb2phy_power_off(rport->phy);
|
||||
rport->suspended = true;
|
||||
}
|
||||
|
||||
/*
|
||||
* activate the linestate detection to get the next device
|
||||
* plug-in irq.
|
||||
*/
|
||||
property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
|
||||
property_enable(rphy, &rport->port_cfg->ls_det_en, true);
|
||||
|
||||
/*
|
||||
* we don't need to rearm the delayed work when the phy port
|
||||
* is suspended.
|
||||
*/
|
||||
mutex_unlock(&rport->mutex);
|
||||
return;
|
||||
default:
|
||||
dev_dbg(&rport->phy->dev, "unknown phy state\n");
|
||||
break;
|
||||
}
|
||||
|
||||
next_schedule:
|
||||
mutex_unlock(&rport->mutex);
|
||||
schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
|
||||
}
|
||||
|
||||
static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
|
||||
{
|
||||
struct rockchip_usb2phy_port *rport = data;
|
||||
struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
|
||||
|
||||
if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
|
||||
return IRQ_NONE;
|
||||
|
||||
mutex_lock(&rport->mutex);
|
||||
|
||||
/* disable linestate detect irq and clear its status */
|
||||
property_enable(rphy, &rport->port_cfg->ls_det_en, false);
|
||||
property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
|
||||
|
||||
mutex_unlock(&rport->mutex);
|
||||
|
||||
/*
|
||||
* In this case for host phy port, a new device is plugged in,
|
||||
* meanwhile, if the phy port is suspended, we need rearm the work to
|
||||
* resume it and mange its states; otherwise, we do nothing about that.
|
||||
*/
|
||||
if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
|
||||
rockchip_usb2phy_sm_work(&rport->sm_work.work);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
|
||||
struct rockchip_usb2phy_port *rport,
|
||||
struct device_node *child_np)
|
||||
{
|
||||
int ret;
|
||||
|
||||
rport->port_id = USB2PHY_PORT_HOST;
|
||||
rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
|
||||
rport->suspended = true;
|
||||
|
||||
mutex_init(&rport->mutex);
|
||||
INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
|
||||
|
||||
rport->ls_irq = of_irq_get_byname(child_np, "linestate");
|
||||
if (rport->ls_irq < 0) {
|
||||
dev_err(rphy->dev, "no linestate irq provided\n");
|
||||
return rport->ls_irq;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
|
||||
rockchip_usb2phy_linestate_irq,
|
||||
IRQF_ONESHOT,
|
||||
"rockchip_usb2phy", rport);
|
||||
if (ret) {
|
||||
dev_err(rphy->dev, "failed to request irq handle\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rockchip_usb2phy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *child_np;
|
||||
struct phy_provider *provider;
|
||||
struct rockchip_usb2phy *rphy;
|
||||
const struct rockchip_usb2phy_cfg *phy_cfgs;
|
||||
const struct of_device_id *match;
|
||||
unsigned int reg;
|
||||
int index, ret;
|
||||
|
||||
rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
|
||||
if (!rphy)
|
||||
return -ENOMEM;
|
||||
|
||||
match = of_match_device(dev->driver->of_match_table, dev);
|
||||
if (!match || !match->data) {
|
||||
dev_err(dev, "phy configs are not assigned!\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!dev->parent || !dev->parent->of_node)
|
||||
return -EINVAL;
|
||||
|
||||
rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
|
||||
if (IS_ERR(rphy->grf))
|
||||
return PTR_ERR(rphy->grf);
|
||||
|
||||
if (of_property_read_u32(np, "reg", ®)) {
|
||||
dev_err(dev, "the reg property is not assigned in %s node\n",
|
||||
np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rphy->dev = dev;
|
||||
phy_cfgs = match->data;
|
||||
platform_set_drvdata(pdev, rphy);
|
||||
|
||||
/* find out a proper config which can be matched with dt. */
|
||||
index = 0;
|
||||
while (phy_cfgs[index].reg) {
|
||||
if (phy_cfgs[index].reg == reg) {
|
||||
rphy->phy_cfg = &phy_cfgs[index];
|
||||
break;
|
||||
}
|
||||
|
||||
++index;
|
||||
}
|
||||
|
||||
if (!rphy->phy_cfg) {
|
||||
dev_err(dev, "no phy-config can be matched with %s node\n",
|
||||
np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
rphy->clk = of_clk_get_by_name(np, "phyclk");
|
||||
if (!IS_ERR(rphy->clk)) {
|
||||
clk_prepare_enable(rphy->clk);
|
||||
} else {
|
||||
dev_info(&pdev->dev, "no phyclk specified\n");
|
||||
rphy->clk = NULL;
|
||||
}
|
||||
|
||||
ret = rockchip_usb2phy_clk480m_register(rphy);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register 480m output clock\n");
|
||||
goto disable_clks;
|
||||
}
|
||||
|
||||
index = 0;
|
||||
for_each_available_child_of_node(np, child_np) {
|
||||
struct rockchip_usb2phy_port *rport = &rphy->ports[index];
|
||||
struct phy *phy;
|
||||
|
||||
/*
|
||||
* This driver aim to support both otg-port and host-port,
|
||||
* but unfortunately, the otg part is not ready in current,
|
||||
* so this comments and below codes are interim, which should
|
||||
* be changed after otg-port is supplied soon.
|
||||
*/
|
||||
if (of_node_cmp(child_np->name, "host-port"))
|
||||
goto next_child;
|
||||
|
||||
phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create phy\n");
|
||||
ret = PTR_ERR(phy);
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
rport->phy = phy;
|
||||
phy_set_drvdata(rport->phy, rport);
|
||||
|
||||
ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
|
||||
if (ret)
|
||||
goto put_child;
|
||||
|
||||
next_child:
|
||||
/* to prevent out of boundary */
|
||||
if (++index >= rphy->phy_cfg->num_ports)
|
||||
break;
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
||||
of_node_put(child_np);
|
||||
disable_clks:
|
||||
if (rphy->clk) {
|
||||
clk_disable_unprepare(rphy->clk);
|
||||
clk_put(rphy->clk);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0x700,
|
||||
.num_ports = 2,
|
||||
.clkout_ctl = { 0x0724, 15, 15, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
|
||||
.ls_det_en = { 0x0680, 4, 4, 0, 1 },
|
||||
.ls_det_st = { 0x0690, 4, 4, 0, 1 },
|
||||
.ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
|
||||
.utmi_ls = { 0x049c, 14, 13, 0, 1 },
|
||||
.utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
|
||||
}
|
||||
},
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
|
||||
{
|
||||
.reg = 0xe450,
|
||||
.num_ports = 2,
|
||||
.clkout_ctl = { 0xe450, 4, 4, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
|
||||
.ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
|
||||
.ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
|
||||
.ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
|
||||
.utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
|
||||
.utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
|
||||
}
|
||||
},
|
||||
},
|
||||
{
|
||||
.reg = 0xe460,
|
||||
.num_ports = 2,
|
||||
.clkout_ctl = { 0xe460, 4, 4, 1, 0 },
|
||||
.port_cfgs = {
|
||||
[USB2PHY_PORT_HOST] = {
|
||||
.phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
|
||||
.ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
|
||||
.ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
|
||||
.ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
|
||||
.utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
|
||||
.utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
|
||||
}
|
||||
},
|
||||
},
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static const struct of_device_id rockchip_usb2phy_dt_match[] = {
|
||||
{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
|
||||
{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
|
||||
|
||||
static struct platform_driver rockchip_usb2phy_driver = {
|
||||
.probe = rockchip_usb2phy_probe,
|
||||
.driver = {
|
||||
.name = "rockchip-usb2phy",
|
||||
.of_match_table = rockchip_usb2phy_dt_match,
|
||||
},
|
||||
};
|
||||
module_platform_driver(rockchip_usb2phy_driver);
|
||||
|
||||
MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
|
||||
MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in a new issue