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Renesas ARM Based SoC Clock Fixes For v3.17

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* ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
 
   This resolves a problem introduced by 4bfb358b1d
   ("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
   which was included in v3.15.
 
   This fix does not have any run-time affect at this time.
 
 * ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
 
   This resolves a problem introduced by 9f13ee6f83
   ("ARM: shmobile: r8a7790: add div4 clocks")
   which was included in v3.11.
 
   This fix does not have any run-time affect at this time.
 
 * ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name
 
   This resolves a problem introduced by a0f7e7496d
   ("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
   which was included in v3.17-rc1.
 
   This fix does not have any run-time affect at this time as the clock in
   question is used by a SCIF device that is not enabled by default.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJT+oE/AAoJENfPZGlqN0++6eYQAK8LStttSbAjBHONrCQpj1/n
 fBu+S9RjzYOKLtG4L7pVXOJSFuIiPB03y4IeiFRflIS6TQyopl7DmTZvN/AztIjE
 dOamQ+Z2ePrLcNUG1ZNfpEUSxfImOqtcm38R58HRDOnMYTszLOaVxtU0Dre9Y3Me
 cYHEN/17PUQWdQ7j5tcaDwXtl4oVjS+1RmzkODKpP2N+1w4l0rcXHEXuNJC6NpW8
 1i2CWnlb64hQ0L1tOBVabmUXmlwbasV5dBnysupn3IZHOMO+liNSb9T2RHpvtKSw
 U4hu4cZXSGNWoFlWzrs7SoJf1uFF0h5GlrgUm5TGPA1oUPsRzJKRS6D70daElmpi
 e5OszD89bs/LftHY4wpcwQ3ic/PSCqMGdF4aFAzVtfseND9tzrK+8aa8GX18bb9R
 hGfEeiXzp2EnIEtBMUmrrk0cV9thx1zuwaGoai0P2E82SXbMglrKYVAm0xN3yxRc
 77u47S479o7xGSdT2/EBX+EIWnFrGZheT10iPc+aEWRRTxWFf5e10j1i3F1Lw7cL
 5P3PNrMUv3s1Vf82gHKfdtlaYZZoMuF3r03ezt2EScg9MDxhytBDHxiokfw7NRdA
 OA8IaXuoU4MSXArgkdJ89kzV1AnK8aMGlQY/BXfjPqgPUGRQ8TK/sEDp2I5poMeZ
 t2xCtxUvCA39NM/xBDyS
 =jurT
 -----END PGP SIGNATURE-----

Merge tag 'renesas-clock-fixes-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes

Merge "Renesas ARM Based SoC Clock Fixes For v3.17" from Simon Horman:

* ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR

  This resolves a problem introduced by 4bfb358b1d
  ("ARM: shmobile: Add r8a7791 legacy SDHI clocks")
  which was included in v3.15.

  This fix does not have any run-time affect at this time.

* ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR

  This resolves a problem introduced by 9f13ee6f83
  ("ARM: shmobile: r8a7790: add div4 clocks")
  which was included in v3.11.

  This fix does not have any run-time affect at this time.

* ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name

  This resolves a problem introduced by a0f7e7496d
  ("ARM: shmobile: sh73a0: add CMT1 clock support for DT")
  which was included in v3.17-rc1.

  This fix does not have any run-time affect at this time as the clock in
  question is used by a SCIF device that is not enabled by default.

* tag 'renesas-clock-fixes-for-v3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7791: add missing 0x0100 for SDCKCR
  ARM: shmobile: r8a7790: add missing 0x0100 for SDCKCR
  ARM: shmobile: sh73a0: Remove spurious 0x from SCIFB clock name

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2014-08-27 15:13:51 -07:00
commit 0dc0d9e18e
3 changed files with 4 additions and 4 deletions
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4
arch/arm/mach-shmobile/clock-r8a7790.c
View file

@ -183,8 +183,8 @@ enum {
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1df0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */

2
arch/arm/mach-shmobile/clock-r8a7791.c
View file

@ -152,7 +152,7 @@ enum {
static struct clk div4_clks[DIV4_NR] = {
[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1df0, CLK_ENABLE_ON_INIT),
};
/* DIV6 clocks */

2
arch/arm/mach-shmobile/clock-sh73a0.c
View file

@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("e6cb0000.serial", &mstp_clks[MSTP207]), /* SCIFA5 */
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("0xe6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("e6c3000.serial", &mstp_clks[MSTP206]), /* SCIFB */
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("e6c40000.serial", &mstp_clks[MSTP204]), /* SCIFA0 */
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */