[ARM] 3820/1: iop3xx: factor out shared pci code
Merge the iop32x PCI code and iop33x PCI code into plat-iop/pci.c. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Lennert Buytenhek
Russell King
parent
e25d64f124
commit
0cb015f9de
4 changed files with 312 additions and 1 deletions
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@ -2,7 +2,7 @@
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# Makefile for the linux kernel.
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#
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obj-y := i2c.o setup.o
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obj-y := i2c.o pci.o setup.o
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obj-m :=
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obj-n :=
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obj- :=
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247
arch/arm/plat-iop/pci.c
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247
arch/arm/plat-iop/pci.c
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@ -0,0 +1,247 @@
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/*
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* arch/arm/plat-iop/pci.c
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*
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* PCI support for the Intel IOP32X and IOP33X processors
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/hardware.h>
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#include <asm/mach/pci.h>
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#include <asm/hardware/iop3xx.h>
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// #define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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#define DBG(x...) do { } while (0)
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#endif
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/*
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* This routine builds either a type0 or type1 configuration command. If the
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* bus is on the 803xx then a type0 made, else a type1 is created.
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*/
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static u32 iop3xx_cfg_address(struct pci_bus *bus, int devfn, int where)
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{
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struct pci_sys_data *sys = bus->sysdata;
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u32 addr;
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if (sys->busnr == bus->number)
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addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
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else
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addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
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addr |= PCI_FUNC(devfn) << 8 | (where & ~3);
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return addr;
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}
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/*
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* This routine checks the status of the last configuration cycle. If an error
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* was detected it returns a 1, else it returns a 0. The errors being checked
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* are parity, master abort, target abort (master and target). These types of
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* errors occure during a config cycle where there is no device, like during
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* the discovery stage.
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*/
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static int iop3xx_pci_status(void)
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{
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unsigned int status;
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int ret = 0;
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/*
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* Check the status registers.
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*/
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status = *IOP3XX_ATUSR;
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if (status & 0xf900) {
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DBG("\t\t\tPCI: P0 - status = 0x%08x\n", status);
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*IOP3XX_ATUSR = status & 0xf900;
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ret = 1;
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}
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status = *IOP3XX_ATUISR;
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if (status & 0x679f) {
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DBG("\t\t\tPCI: P1 - status = 0x%08x\n", status);
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*IOP3XX_ATUISR = status & 0x679f;
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ret = 1;
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}
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return ret;
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}
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/*
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* Simply write the address register and read the configuration
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* data. Note that the 4 nop's ensure that we are able to handle
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* a delayed abort (in theory.)
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*/
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static inline u32 iop3xx_read(unsigned long addr)
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{
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u32 val;
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__asm__ __volatile__(
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"str %1, [%2]\n\t"
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"ldr %0, [%3]\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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: "=r" (val)
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: "r" (addr), "r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
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return val;
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}
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/*
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* The read routines must check the error status of the last configuration
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* cycle. If there was an error, the routine returns all hex f's.
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*/
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static int
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iop3xx_read_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
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u32 val = iop3xx_read(addr) >> ((where & 3) * 8);
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if (iop3xx_pci_status())
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val = 0xffffffff;
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*value = val;
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return PCIBIOS_SUCCESSFUL;
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}
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static int
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iop3xx_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr = iop3xx_cfg_address(bus, devfn, where);
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u32 val;
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if (size != 4) {
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val = iop3xx_read(addr);
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if (iop3xx_pci_status())
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return PCIBIOS_SUCCESSFUL;
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where = (where & 3) * 8;
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if (size == 1)
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val &= ~(0xff << where);
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else
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val &= ~(0xffff << where);
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*IOP3XX_OCCDR = val | value << where;
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} else {
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asm volatile(
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"str %1, [%2]\n\t"
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"str %0, [%3]\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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"nop\n\t"
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:
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: "r" (value), "r" (addr),
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"r" (IOP3XX_OCCAR), "r" (IOP3XX_OCCDR));
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops iop3xx_ops = {
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.read = iop3xx_read_config,
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.write = iop3xx_write_config,
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};
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/*
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* When a PCI device does not exist during config cycles, the 80200 gets a
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* bus error instead of returning 0xffffffff. This handler simply returns.
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*/
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static int
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iop3xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
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{
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DBG("PCI abort: address = 0x%08lx fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx\n",
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addr, fsr, regs->ARM_pc, regs->ARM_lr);
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/*
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* If it was an imprecise abort, then we need to correct the
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* return address to be _after_ the instruction.
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*/
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if (fsr & (1 << 10))
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regs->ARM_pc += 4;
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return 0;
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}
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int iop3xx_pci_setup(int nr, struct pci_sys_data *sys)
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{
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struct resource *res;
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if (nr != 0)
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return 0;
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res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
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if (!res)
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panic("PCI: unable to alloc resources");
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res[0].start = IOP3XX_PCI_LOWER_IO_VA;
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res[0].end = IOP3XX_PCI_LOWER_IO_VA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
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res[0].name = "IOP3XX PCI I/O Space";
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res[0].flags = IORESOURCE_IO;
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request_resource(&ioport_resource, &res[0]);
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res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
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res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
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res[1].name = "IOP3XX PCI Memory Space";
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res[1].flags = IORESOURCE_MEM;
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request_resource(&iomem_resource, &res[1]);
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sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - IOP3XX_PCI_LOWER_MEM_BA;
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sys->io_offset = IOP3XX_PCI_LOWER_IO_VA - IOP3XX_PCI_LOWER_IO_BA;
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sys->resource[0] = &res[0];
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sys->resource[1] = &res[1];
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sys->resource[2] = NULL;
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return 1;
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}
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struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
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{
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return pci_scan_bus(sys->busnr, &iop3xx_ops, sys);
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}
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void iop3xx_pci_preinit(void)
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{
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DBG("PCI: Intel 803xx PCI init code.\n");
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DBG("ATU: IOP3XX_ATUCMD=0x%04x\n", *IOP3XX_ATUCMD);
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DBG("ATU: IOP3XX_OMWTVR0=0x%04x, IOP3XX_OIOWTVR=0x%04x\n",
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*IOP3XX_OMWTVR0,
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*IOP3XX_OIOWTVR);
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DBG("ATU: IOP3XX_ATUCR=0x%08x\n", *IOP3XX_ATUCR);
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DBG("ATU: IOP3XX_IABAR0=0x%08x IOP3XX_IALR0=0x%08x IOP3XX_IATVR0=%08x\n",
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*IOP3XX_IABAR0, *IOP3XX_IALR0, *IOP3XX_IATVR0);
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DBG("ATU: IOP3XX_OMWTVR0=0x%08x\n", *IOP3XX_OMWTVR0);
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DBG("ATU: IOP3XX_IABAR1=0x%08x IOP3XX_IALR1=0x%08x\n",
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*IOP3XX_IABAR1, *IOP3XX_IALR1);
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DBG("ATU: IOP3XX_ERBAR=0x%08x IOP3XX_ERLR=0x%08x IOP3XX_ERTVR=%08x\n",
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*IOP3XX_ERBAR, *IOP3XX_ERLR, *IOP3XX_ERTVR);
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DBG("ATU: IOP3XX_IABAR2=0x%08x IOP3XX_IALR2=0x%08x IOP3XX_IATVR2=%08x\n",
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*IOP3XX_IABAR2, *IOP3XX_IALR2, *IOP3XX_IATVR2);
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DBG("ATU: IOP3XX_IABAR3=0x%08x IOP3XX_IALR3=0x%08x IOP3XX_IATVR3=%08x\n",
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*IOP3XX_IABAR3, *IOP3XX_IALR3, *IOP3XX_IATVR3);
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hook_fault_code(16+6, iop3xx_pci_abort, SIGBUS, "imprecise external abort");
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}
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@ -23,6 +23,64 @@
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#define IOP3XX_PERIPHERAL_SIZE 0x00002000
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#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
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/* Address Translation Unit */
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#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
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#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
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#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
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#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
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#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
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#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
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#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
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#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
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#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
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#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
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#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
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#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
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#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
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#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
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#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
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#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
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#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
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#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
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#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
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#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
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#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
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#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
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#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
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#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
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#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
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#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
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#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
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#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
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#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
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#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
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#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
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#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
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#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
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#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
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#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
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#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
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#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
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#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
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#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
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#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
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#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
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#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
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#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
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#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
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#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
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#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
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#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
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#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
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#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
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#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
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#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
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#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
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#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
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#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
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#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
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#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
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/* I2C bus interface unit */
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#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
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#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
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@ -41,10 +99,12 @@
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*/
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#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
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#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
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#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
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#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
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#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
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#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
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#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
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#ifndef __ASSEMBLY__
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@ -52,6 +52,10 @@ void pci_common_init(struct hw_pci *);
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/*
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* PCI controllers
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*/
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extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
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extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
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extern void iop3xx_pci_preinit(void);
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extern int iop321_setup(int nr, struct pci_sys_data *);
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extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
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extern void iop321_init(void);
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