Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6
This commit is contained in:
Russell King
commit
0b7d5170dc
8 changed files with 187 additions and 25 deletions
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@ -119,6 +119,11 @@ static unsigned long get_rate_nfc(struct clk *clk)
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return get_rate_per(8);
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}
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static unsigned long get_rate_gpt(struct clk *clk)
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{
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return get_rate_per(5);
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}
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static unsigned long get_rate_otg(struct clk *clk)
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{
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return 48000000; /* FIXME */
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@ -144,7 +149,7 @@ static void clk_cgcr_disable(struct clk *clk)
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__raw_writel(reg, clk->enable_reg);
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}
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#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
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#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
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static struct clk name = { \
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.id = i, \
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.enable_reg = CRM_BASE + er, \
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@ -153,27 +158,30 @@ static void clk_cgcr_disable(struct clk *clk)
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.set_rate = sr, \
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.enable = clk_cgcr_enable, \
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.disable = clk_cgcr_disable, \
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.secondary = s, \
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}
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DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_ipg, NULL);
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DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL);
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DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL);
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DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL);
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DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL);
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DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL);
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DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL);
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DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
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DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL);
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DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL);
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DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL);
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DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL);
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DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL);
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DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL);
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DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL);
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DEFINE_CLOCK(fec_clk, 0, CCM_CGCR0, 23, get_rate_ipg, NULL);
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DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
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DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
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DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
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DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
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DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
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DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
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DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
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DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
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DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
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#define _REGISTER_CLOCK(d, n, c) \
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{ \
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@ -208,13 +216,21 @@ static struct clk_lookup lookups[] = {
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_REGISTER_CLOCK("fec.0", NULL, fec_clk)
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};
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int __init mx25_clocks_init(unsigned long fref)
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int __init mx25_clocks_init(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(lookups); i++)
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clkdev_add(&lookups[i]);
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/* Turn off all clocks except the ones we need to survive, namely:
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* EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
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* SCC
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*/
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__raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
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__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
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__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
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mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
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return 0;
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@ -91,7 +91,7 @@ static void __init mx25pdk_init(void)
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static void __init mx25pdk_timer_init(void)
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{
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mx25_clocks_init(26000000);
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mx25_clocks_init();
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}
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static struct sys_timer mx25pdk_timer = {
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@ -173,6 +173,7 @@ static void expio_unmask_irq(u32 irq)
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}
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static struct irq_chip expio_irq_chip = {
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.name = "EXPIO(CPLD)",
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.ack = expio_ack_irq,
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.mask = expio_mask_irq,
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.unmask = expio_unmask_irq,
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@ -302,6 +303,7 @@ static struct regulator_init_data ldo1_data = {
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.min_uV = 2800000,
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.max_uV = 2800000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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.apply_uV = 1,
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},
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};
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@ -322,6 +324,7 @@ static struct regulator_init_data ldo2_data = {
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.min_uV = 3300000,
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.max_uV = 3300000,
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.valid_modes_mask = REGULATOR_MODE_NORMAL,
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.valid_ops_mask = REGULATOR_CHANGE_STATUS,
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.apply_uV = 1,
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},
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.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
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@ -459,6 +462,7 @@ static int mx31_wm8350_init(struct wm8350 *wm8350)
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static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
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.init = mx31_wm8350_init,
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.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
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};
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#endif
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@ -23,6 +23,7 @@
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <mach/audmux.h>
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#include <mach/hardware.h>
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@ -32,6 +33,140 @@ static void __iomem *audmux_base;
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#define MXC_AUDMUX_V2_PTCR(x) ((x) * 8)
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#define MXC_AUDMUX_V2_PDCR(x) ((x) * 8 + 4)
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#ifdef CONFIG_DEBUG_FS
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static struct dentry *audmux_debugfs_root;
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static int audmux_open_file(struct inode *inode, struct file *file)
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{
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file->private_data = inode->i_private;
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return 0;
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}
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/* There is an annoying discontinuity in the SSI numbering with regard
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* to the Linux number of the devices */
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static const char *audmux_port_string(int port)
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{
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switch (port) {
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case MX31_AUDMUX_PORT1_SSI0:
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return "imx-ssi.0";
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case MX31_AUDMUX_PORT2_SSI1:
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return "imx-ssi.1";
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case MX31_AUDMUX_PORT3_SSI_PINS_3:
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return "SSI3";
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case MX31_AUDMUX_PORT4_SSI_PINS_4:
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return "SSI4";
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case MX31_AUDMUX_PORT5_SSI_PINS_5:
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return "SSI5";
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case MX31_AUDMUX_PORT6_SSI_PINS_6:
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return "SSI6";
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default:
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return "UNKNOWN";
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}
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}
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static ssize_t audmux_read_file(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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ssize_t ret;
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char *buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
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int port = (int)file->private_data;
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u32 pdcr, ptcr;
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if (!buf)
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return -ENOMEM;
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if (audmux_clk)
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clk_enable(audmux_clk);
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ptcr = readl(audmux_base + MXC_AUDMUX_V2_PTCR(port));
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pdcr = readl(audmux_base + MXC_AUDMUX_V2_PDCR(port));
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if (audmux_clk)
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clk_disable(audmux_clk);
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ret = snprintf(buf, PAGE_SIZE, "PDCR: %08x\nPTCR: %08x\n",
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pdcr, ptcr);
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if (ptcr & MXC_AUDMUX_V2_PTCR_TFSDIR)
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"TxFS output from %s, ",
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audmux_port_string((ptcr >> 27) & 0x7));
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else
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"TxFS input, ");
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if (ptcr & MXC_AUDMUX_V2_PTCR_TCLKDIR)
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"TxClk output from %s",
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audmux_port_string((ptcr >> 22) & 0x7));
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else
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"TxClk input");
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ret += snprintf(buf + ret, PAGE_SIZE - ret, "\n");
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if (ptcr & MXC_AUDMUX_V2_PTCR_SYN) {
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"Port is symmetric");
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} else {
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if (ptcr & MXC_AUDMUX_V2_PTCR_RFSDIR)
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"RxFS output from %s, ",
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audmux_port_string((ptcr >> 17) & 0x7));
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else
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"RxFS input, ");
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if (ptcr & MXC_AUDMUX_V2_PTCR_RCLKDIR)
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"RxClk output from %s",
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audmux_port_string((ptcr >> 12) & 0x7));
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else
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"RxClk input");
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}
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ret += snprintf(buf + ret, PAGE_SIZE - ret,
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"\nData received from %s\n",
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audmux_port_string((pdcr >> 13) & 0x7));
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ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
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kfree(buf);
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return ret;
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}
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static const struct file_operations audmux_debugfs_fops = {
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.open = audmux_open_file,
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.read = audmux_read_file,
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};
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static void audmux_debugfs_init(void)
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{
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int i;
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char buf[20];
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audmux_debugfs_root = debugfs_create_dir("audmux", NULL);
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if (!audmux_debugfs_root) {
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pr_warning("Failed to create AUDMUX debugfs root\n");
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return;
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}
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for (i = 1; i < 8; i++) {
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snprintf(buf, sizeof(buf), "ssi%d", i);
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if (!debugfs_create_file(buf, 0444, audmux_debugfs_root,
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(void *)i, &audmux_debugfs_fops))
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pr_warning("Failed to create AUDMUX port %d debugfs file\n",
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i);
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}
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}
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#else
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static inline void audmux_debugfs_init(void)
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{
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}
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#endif
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int mxc_audmux_v2_configure_port(unsigned int port, unsigned int ptcr,
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unsigned int pdcr)
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{
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@ -68,6 +203,8 @@ static int mxc_audmux_v2_init(void)
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if (cpu_is_mx31() || cpu_is_mx35())
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audmux_base = IO_ADDRESS(AUDMUX_BASE_ADDR);
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audmux_debugfs_init();
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return 0;
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}
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@ -25,7 +25,7 @@
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#ifndef __ASSEMBLY__
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enum mx31lilly_boards {
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enum mx31lite_boards {
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MX31LITE_NOBOARD = 0,
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MX31LITE_DB = 1,
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};
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@ -32,7 +32,7 @@ extern void mxc91231_init_irq(void);
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extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
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extern int mx1_clocks_init(unsigned long fref);
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extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
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extern int mx25_clocks_init(unsigned long fref);
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extern int mx25_clocks_init(void);
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extern int mx27_clocks_init(unsigned long fref);
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extern int mx31_clocks_init(unsigned long fref);
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extern int mx35_clocks_init(void);
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@ -671,7 +671,7 @@
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#define MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8 IOMUX_PAD(0x634, 0x1d0, 6, 0x0, 0, NO_PAD_CTRL)
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#define MX35_PAD_LD9__IPU_DISPB_DAT_9 IOMUX_PAD(0x638, 0x1d4, 0, 0x0, 0, NO_PAD_CTRL)
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#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4 0, NO_PAD_CTRL)
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#define MX35_PAD_LD9__GPIO2_9 IOMUX_PAD(0x638, 0x1d4, 5, 0x8e4, 0, NO_PAD_CTRL)
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#define MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9 IOMUX_PAD(0x638, 0x1d4, 6, 0x0, 0, NO_PAD_CTRL)
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#define MX35_PAD_LD10__IPU_DISPB_DAT_10 IOMUX_PAD(0x63c, 0x1d8, 0, 0x0, 0, NO_PAD_CTRL)
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@ -37,7 +37,12 @@
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* within sensible limits.
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*/
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#define MXC_BOARD_IRQ_START (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
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#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
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#define MXC_BOARD_IRQS 80
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#else
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#define MXC_BOARD_IRQS 16
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#endif
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#define MXC_IPU_IRQ_START (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS)
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