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[AVR32] Define ARCH_KMALLOC_MINALIGN to L1_CACHE_BYTES

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This allows SLUB debugging to be used without fear of messing up DMA
transfers. SPI is one example that easily breaks without this patch.

Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen 2007-06-11 17:17:14 +02:00
parent 2fdfe8d9a2
commit 093d0faf57
1 changed files with 9 additions and 0 deletions
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9
include/asm-avr32/cache.h
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@ -4,6 +4,15 @@
#define L1_CACHE_SHIFT 5 #define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/*
* Memory returned by kmalloc() may be used for DMA, so we must make
* sure that all such allocations are cache aligned. Otherwise,
* unrelated code may cause parts of the buffer to be read into the
* cache before the transfer is done, causing old data to be seen by
* the CPU.
*/
#define ARCH_KMALLOC_MINALIGN L1_CACHE_BYTES
#ifndef __ASSEMBLER__ #ifndef __ASSEMBLER__
struct cache_info { struct cache_info {
unsigned int ways; unsigned int ways;