ath9k: enable the baseband watchdog events for AR9003
This enables the baseband watchdog events for the AR9003 family on ath9k. Upon an a baseband watchdog interrupt we reset the hardware, this should address corner case conditions where normal operation can stall. Enable ATH_DBG_RESET to be able to review details of the bb watchdog interrupt once it happens. If you're curious how often this happens just grep the debugfs interrupt file. Cc: Sam Ng <sam.ng@atheros.com> Cc: Paul Shaw <paul.shaw@atheros.com> Cc: Don Breslin <don.breslin@atheros.com> Cc: Cliff Holden <cliff.holden@atheros.com Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com Signed-off-by: John W. Linville <linville@tuxdriver.com>
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aea702b70a
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08578b8f16
3 changed files with 16 additions and 1 deletions
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@ -269,6 +269,8 @@ void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status)
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sc->debug.stats.istats.rxlp++;
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if (status & ATH9K_INT_RXHP)
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sc->debug.stats.istats.rxhp++;
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if (status & ATH9K_INT_BB_WATCHDOG)
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sc->debug.stats.istats.bb_watchdog++;
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} else {
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if (status & ATH9K_INT_RX)
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sc->debug.stats.istats.rxok++;
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@ -319,6 +321,9 @@ static ssize_t read_file_interrupt(struct file *file, char __user *user_buf,
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"%8s: %10u\n", "RXLP", sc->debug.stats.istats.rxlp);
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len += snprintf(buf + len, sizeof(buf) - len,
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"%8s: %10u\n", "RXHP", sc->debug.stats.istats.rxhp);
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len += snprintf(buf + len, sizeof(buf) - len,
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"%8s: %10u\n", "WATCHDOG",
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sc->debug.stats.istats.bb_watchdog);
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} else {
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len += snprintf(buf + len, sizeof(buf) - len,
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"%8s: %10u\n", "RX", sc->debug.stats.istats.rxok);
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@ -53,6 +53,7 @@ struct ath_buf;
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* @cabend: RX End of CAB traffic
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* @dtimsync: DTIM sync lossage
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* @dtim: RX Beacon with DTIM
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* @bb_watchdog: Baseband watchdog
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*/
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struct ath_interrupt_stats {
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u32 total;
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@ -76,6 +77,7 @@ struct ath_interrupt_stats {
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u32 cabend;
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u32 dtimsync;
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u32 dtim;
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u32 bb_watchdog;
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};
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struct ath_rc_stats {
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@ -520,6 +520,12 @@ irqreturn_t ath_isr(int irq, void *dev)
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!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
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goto chip_reset;
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if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
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(status & ATH9K_INT_BB_WATCHDOG)) {
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ar9003_hw_bb_watchdog_dbg_info(ah);
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goto chip_reset;
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}
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if (status & ATH9K_INT_SWBA)
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tasklet_schedule(&sc->bcon_tasklet);
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@ -1195,7 +1201,9 @@ static int ath9k_start(struct ieee80211_hw *hw)
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ATH9K_INT_GLOBAL;
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if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
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ah->imask |= ATH9K_INT_RXHP | ATH9K_INT_RXLP;
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ah->imask |= ATH9K_INT_RXHP |
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ATH9K_INT_RXLP |
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ATH9K_INT_BB_WATCHDOG;
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else
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ah->imask |= ATH9K_INT_RX;
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