igb: restore EEPROM values of MDICNFG on reset with 82580
On a reset the MDICNFG.Destination and MDICNFG.COM_MDIO register fields are not restored to the EEPROM default. This patch modifies the reset code to read the EEPROM and restore the default values. Signed-off-by: Nicholas Nunley <nicholas.d.nunley@intel.com> Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2 changed files with 45 additions and 0 deletions
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@ -1548,6 +1548,43 @@ static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
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return ret_val;
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}
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/**
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* igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
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* @hw: pointer to the HW structure
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*
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* This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
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* the values found in the EEPROM. This addresses an issue in which these
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* bits are not restored from EEPROM after reset.
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**/
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static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw)
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{
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s32 ret_val = 0;
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u32 mdicnfg;
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u16 nvm_data;
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if (hw->mac.type != e1000_82580)
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goto out;
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if (!igb_sgmii_active_82575(hw))
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goto out;
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ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
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NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
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&nvm_data);
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if (ret_val) {
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hw_dbg("NVM Read Error\n");
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goto out;
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}
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mdicnfg = rd32(E1000_MDICNFG);
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if (nvm_data & NVM_WORD24_EXT_MDIO)
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mdicnfg |= E1000_MDICNFG_EXT_MDIO;
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if (nvm_data & NVM_WORD24_COM_MDIO)
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mdicnfg |= E1000_MDICNFG_COM_MDIO;
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wr32(E1000_MDICNFG, mdicnfg);
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out:
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return ret_val;
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}
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/**
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* igb_reset_hw_82580 - Reset hardware
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* @hw: pointer to the HW structure
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@ -1623,6 +1660,10 @@ static s32 igb_reset_hw_82580(struct e1000_hw *hw)
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wr32(E1000_IMC, 0xffffffff);
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icr = rd32(E1000_ICR);
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ret_val = igb_reset_mdicnfg_82580(hw);
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if (ret_val)
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hw_dbg("Could not reset MDICNFG based on EEPROM\n");
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/* Install any alternate MAC address into RAR0 */
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ret_val = igb_check_alt_mac_addr(hw);
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@ -570,6 +570,10 @@
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#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0)
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/* Mask bits for fields in Word 0x24 of the NVM */
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#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */
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#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */
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/* Mask bits for fields in Word 0x0f of the NVM */
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#define NVM_WORD0F_PAUSE_MASK 0x3000
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#define NVM_WORD0F_ASM_DIR 0x2000
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